1 /**************************************************************************
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include "intel_batchbuffer.h"
29 #include "intel_buffer_objects.h"
30 #include "intel_reg.h"
31 #include "intel_bufmgr.h"
32 #include "intel_buffers.h"
33 #include "brw_context.h"
36 intel_batchbuffer_reset(struct brw_context
*brw
);
38 struct cached_batch_item
{
39 struct cached_batch_item
*next
;
45 intel_batchbuffer_clear_cache(struct brw_context
*brw
)
47 struct cached_batch_item
*item
= brw
->batch
.cached_items
;
50 struct cached_batch_item
*next
= item
->next
;
55 brw
->batch
.cached_items
= NULL
;
59 intel_batchbuffer_init(struct brw_context
*brw
)
61 intel_batchbuffer_reset(brw
);
64 /* We can't just use brw_state_batch to get a chunk of space for
65 * the gen6 workaround because it involves actually writing to
66 * the buffer, and the kernel doesn't let us write to the batch.
68 brw
->batch
.workaround_bo
= drm_intel_bo_alloc(brw
->bufmgr
,
69 "pipe_control workaround",
73 brw
->batch
.need_workaround_flush
= true;
76 brw
->batch
.cpu_map
= malloc(BATCH_SZ
);
77 brw
->batch
.map
= brw
->batch
.cpu_map
;
82 intel_batchbuffer_reset(struct brw_context
*brw
)
84 if (brw
->batch
.last_bo
!= NULL
) {
85 drm_intel_bo_unreference(brw
->batch
.last_bo
);
86 brw
->batch
.last_bo
= NULL
;
88 brw
->batch
.last_bo
= brw
->batch
.bo
;
90 intel_batchbuffer_clear_cache(brw
);
92 brw
->batch
.bo
= drm_intel_bo_alloc(brw
->bufmgr
, "batchbuffer",
95 drm_intel_bo_map(brw
->batch
.bo
, true);
96 brw
->batch
.map
= brw
->batch
.bo
->virtual;
99 brw
->batch
.reserved_space
= BATCH_RESERVED
;
100 brw
->batch
.state_batch_offset
= brw
->batch
.bo
->size
;
102 brw
->batch
.needs_sol_reset
= false;
104 /* We don't know what ring the new batch will be sent to until we see the
105 * first BEGIN_BATCH or BEGIN_BATCH_BLT. Mark it as unknown.
107 brw
->batch
.ring
= UNKNOWN_RING
;
111 intel_batchbuffer_save_state(struct brw_context
*brw
)
113 brw
->batch
.saved
.used
= brw
->batch
.used
;
114 brw
->batch
.saved
.reloc_count
=
115 drm_intel_gem_bo_get_reloc_count(brw
->batch
.bo
);
119 intel_batchbuffer_reset_to_saved(struct brw_context
*brw
)
121 drm_intel_gem_bo_clear_relocs(brw
->batch
.bo
, brw
->batch
.saved
.reloc_count
);
123 brw
->batch
.used
= brw
->batch
.saved
.used
;
124 if (brw
->batch
.used
== 0)
125 brw
->batch
.ring
= UNKNOWN_RING
;
127 /* Cached batch state is dead, since we just cleared some unknown part of the
128 * batchbuffer. Assume that the caller resets any other state necessary.
130 intel_batchbuffer_clear_cache(brw
);
134 intel_batchbuffer_free(struct brw_context
*brw
)
136 free(brw
->batch
.cpu_map
);
137 drm_intel_bo_unreference(brw
->batch
.last_bo
);
138 drm_intel_bo_unreference(brw
->batch
.bo
);
139 drm_intel_bo_unreference(brw
->batch
.workaround_bo
);
140 intel_batchbuffer_clear_cache(brw
);
144 do_batch_dump(struct brw_context
*brw
)
146 struct drm_intel_decode
*decode
;
147 struct intel_batchbuffer
*batch
= &brw
->batch
;
150 decode
= drm_intel_decode_context_alloc(brw
->intelScreen
->deviceID
);
154 ret
= drm_intel_bo_map(batch
->bo
, false);
156 drm_intel_decode_set_batch_pointer(decode
,
162 "WARNING: failed to map batchbuffer (%s), "
163 "dumping uploaded data instead.\n", strerror(ret
));
165 drm_intel_decode_set_batch_pointer(decode
,
171 drm_intel_decode(decode
);
173 drm_intel_decode_context_free(decode
);
176 drm_intel_bo_unmap(batch
->bo
);
178 brw_debug_batch(brw
);
183 intel_batchbuffer_emit_render_ring_prelude(struct brw_context
*brw
)
185 /* Without hardware contexts, we need to capture the pipeline statistics
186 * registers at the start and end of each render ring batch, so we can see
187 * what that batch contributed. Emit state packets to write them to a BO.
189 brw_emit_query_begin(brw
);
193 * Called when starting a new batch buffer.
196 brw_new_batch(struct brw_context
*brw
)
198 /* Create a new batchbuffer and reset the associated state: */
199 intel_batchbuffer_reset(brw
);
201 /* If the kernel supports hardware contexts, then most hardware state is
202 * preserved between batches; we only need to re-emit state that is required
203 * to be in every batch. Otherwise we need to re-emit all the state that
204 * would otherwise be stored in the context (which for all intents and
205 * purposes means everything).
207 if (brw
->hw_ctx
== NULL
)
208 brw
->state
.dirty
.brw
|= BRW_NEW_CONTEXT
;
210 brw
->state
.dirty
.brw
|= BRW_NEW_BATCH
;
212 /* Assume that the last command before the start of our batch was a
213 * primitive, for safety.
215 brw
->batch
.need_workaround_flush
= true;
217 brw
->state_batch_count
= 0;
221 /* We need to periodically reap the shader time results, because rollover
222 * happens every few seconds. We also want to see results every once in a
223 * while, because many programs won't cleanly destroy our context, so the
224 * end-of-run printout may not happen.
226 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
227 brw_collect_and_report_shader_time(brw
);
231 * Called from intel_batchbuffer_flush before emitting MI_BATCHBUFFER_END and
234 * This function can emit state (say, to preserve registers that aren't saved
235 * between batches). All of this state MUST fit in the reserved space at the
236 * end of the batchbuffer. If you add more GPU state, increase the reserved
237 * space by updating the BATCH_RESERVED macro.
240 brw_finish_batch(struct brw_context
*brw
)
242 /* Capture the closing pipeline statistics register values necessary to
243 * support query objects (in the non-hardware context world).
245 brw_emit_query_end(brw
);
247 if (brw
->curbe
.curbe_bo
) {
248 drm_intel_gem_bo_unmap_gtt(brw
->curbe
.curbe_bo
);
249 drm_intel_bo_unreference(brw
->curbe
.curbe_bo
);
250 brw
->curbe
.curbe_bo
= NULL
;
253 /* Mark that the current program cache BO has been used by the GPU.
254 * It will be reallocated if we need to put new programs in for the
257 brw
->cache
.bo_used_by_gpu
= true;
260 /* TODO: Push this whole function into bufmgr.
263 do_flush_locked(struct brw_context
*brw
)
265 struct intel_batchbuffer
*batch
= &brw
->batch
;
269 drm_intel_bo_unmap(batch
->bo
);
271 ret
= drm_intel_bo_subdata(batch
->bo
, 0, 4*batch
->used
, batch
->map
);
272 if (ret
== 0 && batch
->state_batch_offset
!= batch
->bo
->size
) {
273 ret
= drm_intel_bo_subdata(batch
->bo
,
274 batch
->state_batch_offset
,
275 batch
->bo
->size
- batch
->state_batch_offset
,
276 (char *)batch
->map
+ batch
->state_batch_offset
);
280 if (!brw
->intelScreen
->no_hw
) {
283 if (brw
->gen
>= 6 && batch
->ring
== BLT_RING
) {
284 flags
= I915_EXEC_BLT
;
286 flags
= I915_EXEC_RENDER
;
288 if (batch
->needs_sol_reset
)
289 flags
|= I915_EXEC_GEN7_SOL_RESET
;
292 if (unlikely(INTEL_DEBUG
& DEBUG_AUB
))
293 brw_annotate_aub(brw
);
294 if (brw
->hw_ctx
== NULL
|| batch
->ring
!= RENDER_RING
) {
295 ret
= drm_intel_bo_mrb_exec(batch
->bo
, 4 * batch
->used
, NULL
, 0, 0,
298 ret
= drm_intel_gem_bo_context_exec(batch
->bo
, brw
->hw_ctx
,
299 4 * batch
->used
, flags
);
304 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
))
308 fprintf(stderr
, "intel_do_flush_locked failed: %s\n", strerror(-ret
));
316 _intel_batchbuffer_flush(struct brw_context
*brw
,
317 const char *file
, int line
)
321 if (brw
->batch
.used
== 0)
324 if (brw
->first_post_swapbuffers_batch
== NULL
) {
325 brw
->first_post_swapbuffers_batch
= brw
->batch
.bo
;
326 drm_intel_bo_reference(brw
->first_post_swapbuffers_batch
);
329 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
330 int bytes_for_commands
= 4 * brw
->batch
.used
;
331 int bytes_for_state
= brw
->batch
.bo
->size
- brw
->batch
.state_batch_offset
;
332 int total_bytes
= bytes_for_commands
+ bytes_for_state
;
333 fprintf(stderr
, "%s:%d: Batchbuffer flush with %4db (pkt) + "
334 "%4db (state) = %4db (%0.1f%%)\n", file
, line
,
335 bytes_for_commands
, bytes_for_state
,
337 100.0f
* total_bytes
/ BATCH_SZ
);
340 brw
->batch
.reserved_space
= 0;
342 brw_finish_batch(brw
);
344 /* Mark the end of the buffer. */
345 intel_batchbuffer_emit_dword(brw
, MI_BATCH_BUFFER_END
);
346 if (brw
->batch
.used
& 1) {
347 /* Round batchbuffer usage to 2 DWORDs. */
348 intel_batchbuffer_emit_dword(brw
, MI_NOOP
);
351 intel_upload_finish(brw
);
353 /* Check that we didn't just wrap our batchbuffer at a bad time. */
354 assert(!brw
->no_batch_wrap
);
356 ret
= do_flush_locked(brw
);
358 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
359 fprintf(stderr
, "waiting for idle\n");
360 drm_intel_bo_wait_rendering(brw
->batch
.bo
);
363 /* Start a new batch buffer. */
370 /* This is the only way buffers get added to the validate list.
373 intel_batchbuffer_emit_reloc(struct brw_context
*brw
,
374 drm_intel_bo
*buffer
,
375 uint32_t read_domains
, uint32_t write_domain
,
380 ret
= drm_intel_bo_emit_reloc(brw
->batch
.bo
, 4*brw
->batch
.used
,
382 read_domains
, write_domain
);
387 * Using the old buffer offset, write in what the right data would be, in case
388 * the buffer doesn't move and we can short-circuit the relocation processing
391 intel_batchbuffer_emit_dword(brw
, buffer
->offset
+ delta
);
397 intel_batchbuffer_emit_reloc_fenced(struct brw_context
*brw
,
398 drm_intel_bo
*buffer
,
399 uint32_t read_domains
,
400 uint32_t write_domain
,
405 ret
= drm_intel_bo_emit_reloc_fence(brw
->batch
.bo
, 4*brw
->batch
.used
,
407 read_domains
, write_domain
);
412 * Using the old buffer offset, write in what the right data would
413 * be, in case the buffer doesn't move and we can short-circuit the
414 * relocation processing in the kernel
416 intel_batchbuffer_emit_dword(brw
, buffer
->offset
+ delta
);
422 intel_batchbuffer_data(struct brw_context
*brw
,
423 const void *data
, GLuint bytes
, enum brw_gpu_ring ring
)
425 assert((bytes
& 3) == 0);
426 intel_batchbuffer_require_space(brw
, bytes
, ring
);
427 __memcpy(brw
->batch
.map
+ brw
->batch
.used
, data
, bytes
);
428 brw
->batch
.used
+= bytes
>> 2;
432 intel_batchbuffer_cached_advance(struct brw_context
*brw
)
434 struct cached_batch_item
**prev
= &brw
->batch
.cached_items
, *item
;
435 uint32_t sz
= (brw
->batch
.used
- brw
->batch
.emit
) * sizeof(uint32_t);
436 uint32_t *start
= brw
->batch
.map
+ brw
->batch
.emit
;
437 uint16_t op
= *start
>> 16;
443 old
= brw
->batch
.map
+ item
->header
;
444 if (op
== *old
>> 16) {
445 if (item
->size
== sz
&& memcmp(old
, start
, sz
) == 0) {
446 if (prev
!= &brw
->batch
.cached_items
) {
448 item
->next
= brw
->batch
.cached_items
;
449 brw
->batch
.cached_items
= item
;
451 brw
->batch
.used
= brw
->batch
.emit
;
452 assert(brw
->batch
.used
> 0);
461 item
= malloc(sizeof(struct cached_batch_item
));
465 item
->next
= brw
->batch
.cached_items
;
466 brw
->batch
.cached_items
= item
;
470 item
->header
= brw
->batch
.emit
;
474 * Restriction [DevSNB, DevIVB]:
476 * Prior to changing Depth/Stencil Buffer state (i.e. any combination of
477 * 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS, 3DSTATE_STENCIL_BUFFER,
478 * 3DSTATE_HIER_DEPTH_BUFFER) SW must first issue a pipelined depth stall
479 * (PIPE_CONTROL with Depth Stall bit set), followed by a pipelined depth
480 * cache flush (PIPE_CONTROL with Depth Flush Bit set), followed by
481 * another pipelined depth stall (PIPE_CONTROL with Depth Stall bit set),
482 * unless SW can otherwise guarantee that the pipeline from WM onwards is
483 * already flushed (e.g., via a preceding MI_FLUSH).
486 intel_emit_depth_stall_flushes(struct brw_context
*brw
)
488 assert(brw
->gen
>= 6 && brw
->gen
<= 7);
491 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
492 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL
);
493 OUT_BATCH(0); /* address */
494 OUT_BATCH(0); /* write data */
498 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
499 OUT_BATCH(PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
500 OUT_BATCH(0); /* address */
501 OUT_BATCH(0); /* write data */
505 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
506 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL
);
507 OUT_BATCH(0); /* address */
508 OUT_BATCH(0); /* write data */
513 * From the Ivybridge PRM, Volume 2 Part 1, Section 3.2 (VS Stage Input):
514 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
515 * stall needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
516 * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
517 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL needs
518 * to be sent before any combination of VS associated 3DSTATE."
521 gen7_emit_vs_workaround_flush(struct brw_context
*brw
)
523 assert(brw
->gen
== 7);
526 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
527 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL
| PIPE_CONTROL_WRITE_IMMEDIATE
);
528 OUT_RELOC(brw
->batch
.workaround_bo
,
529 I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
, 0);
530 OUT_BATCH(0); /* write data */
536 * Emit a PIPE_CONTROL command for gen7 with the CS Stall bit set.
539 gen7_emit_cs_stall_flush(struct brw_context
*brw
)
542 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
543 /* From p61 of the Ivy Bridge PRM (1.10.4 PIPE_CONTROL Command: DW1[20]
546 * One of the following must also be set:
547 * - Render Target Cache Flush Enable ([12] of DW1)
548 * - Depth Cache Flush Enable ([0] of DW1)
549 * - Stall at Pixel Scoreboard ([1] of DW1)
550 * - Depth Stall ([13] of DW1)
551 * - Post-Sync Operation ([13] of DW1)
553 * We choose to do a Post-Sync Operation (Write Immediate Data), since
554 * it seems like it will incur the least additional performance penalty.
556 OUT_BATCH(PIPE_CONTROL_CS_STALL
| PIPE_CONTROL_WRITE_IMMEDIATE
);
557 OUT_RELOC(brw
->batch
.workaround_bo
,
558 I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
, 0);
565 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
566 * implementing two workarounds on gen6. From section 1.4.7.1
567 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
569 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
570 * produced by non-pipelined state commands), software needs to first
571 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
574 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
575 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
577 * And the workaround for these two requires this workaround first:
579 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
580 * BEFORE the pipe-control with a post-sync op and no write-cache
583 * And this last workaround is tricky because of the requirements on
584 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
587 * "1 of the following must also be set:
588 * - Render Target Cache Flush Enable ([12] of DW1)
589 * - Depth Cache Flush Enable ([0] of DW1)
590 * - Stall at Pixel Scoreboard ([1] of DW1)
591 * - Depth Stall ([13] of DW1)
592 * - Post-Sync Operation ([13] of DW1)
593 * - Notify Enable ([8] of DW1)"
595 * The cache flushes require the workaround flush that triggered this
596 * one, so we can't use it. Depth stall would trigger the same.
597 * Post-sync nonzero is what triggered this second workaround, so we
598 * can't use that one either. Notify enable is IRQs, which aren't
599 * really our business. That leaves only stall at scoreboard.
602 intel_emit_post_sync_nonzero_flush(struct brw_context
*brw
)
604 if (!brw
->batch
.need_workaround_flush
)
608 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
609 OUT_BATCH(PIPE_CONTROL_CS_STALL
|
610 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
611 OUT_BATCH(0); /* address */
612 OUT_BATCH(0); /* write data */
616 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
617 OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE
);
618 OUT_RELOC(brw
->batch
.workaround_bo
,
619 I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
, 0);
620 OUT_BATCH(0); /* write data */
623 brw
->batch
.need_workaround_flush
= false;
626 /* Emit a pipelined flush to either flush render and texture cache for
627 * reading from a FBO-drawn texture, or flush so that frontbuffer
628 * render appears on the screen in DRI1.
630 * This is also used for the always_flush_cache driconf debug option.
633 intel_batchbuffer_emit_mi_flush(struct brw_context
*brw
)
636 if (brw
->batch
.ring
== BLT_RING
) {
638 OUT_BATCH(MI_FLUSH_DW
);
645 /* Hardware workaround: SNB B-Spec says:
647 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache
648 * Flush Enable =1, a PIPE_CONTROL with any non-zero
649 * post-sync-op is required.
651 intel_emit_post_sync_nonzero_flush(brw
);
655 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2));
656 OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH
|
657 PIPE_CONTROL_WRITE_FLUSH
|
658 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
659 PIPE_CONTROL_VF_CACHE_INVALIDATE
|
660 PIPE_CONTROL_TC_FLUSH
|
661 PIPE_CONTROL_NO_WRITE
|
662 PIPE_CONTROL_CS_STALL
);
663 OUT_BATCH(0); /* write address */
664 OUT_BATCH(0); /* write data */
669 OUT_BATCH(_3DSTATE_PIPE_CONTROL
| (4 - 2) |
670 PIPE_CONTROL_WRITE_FLUSH
|
671 PIPE_CONTROL_NO_WRITE
);
672 OUT_BATCH(0); /* write address */
673 OUT_BATCH(0); /* write data */
674 OUT_BATCH(0); /* write data */