2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "intel_batchbuffer.h"
27 #include "intel_buffer_objects.h"
28 #include "brw_bufmgr.h"
29 #include "intel_buffers.h"
30 #include "intel_fbo.h"
31 #include "brw_context.h"
32 #include "brw_defines.h"
33 #include "brw_state.h"
34 #include "common/gen_decoder.h"
36 #include "util/hash_table.h"
41 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
44 intel_batchbuffer_reset(struct intel_batchbuffer
*batch
,
45 struct brw_bufmgr
*bufmgr
,
49 uint_key_compare(const void *a
, const void *b
)
55 uint_key_hash(const void *key
)
57 return (uintptr_t) key
;
61 intel_batchbuffer_init(struct intel_screen
*screen
,
62 struct intel_batchbuffer
*batch
)
64 struct brw_bufmgr
*bufmgr
= screen
->bufmgr
;
65 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
67 if (!devinfo
->has_llc
) {
68 batch
->cpu_map
= malloc(BATCH_SZ
);
69 batch
->map
= batch
->cpu_map
;
70 batch
->map_next
= batch
->cpu_map
;
73 batch
->reloc_count
= 0;
74 batch
->reloc_array_size
= 250;
75 batch
->relocs
= malloc(batch
->reloc_array_size
*
76 sizeof(struct drm_i915_gem_relocation_entry
));
77 batch
->exec_count
= 0;
78 batch
->exec_array_size
= 100;
80 malloc(batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
81 batch
->validation_list
=
82 malloc(batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
84 if (INTEL_DEBUG
& DEBUG_BATCH
) {
85 batch
->state_batch_sizes
=
86 _mesa_hash_table_create(NULL
, uint_key_hash
, uint_key_compare
);
89 batch
->use_batch_first
=
90 screen
->kernel_features
& KERNEL_ALLOWS_EXEC_BATCH_FIRST
;
92 /* PIPE_CONTROL needs a w/a but only on gen6 */
93 batch
->valid_reloc_flags
= EXEC_OBJECT_WRITE
;
94 if (devinfo
->gen
== 6)
95 batch
->valid_reloc_flags
|= EXEC_OBJECT_NEEDS_GTT
;
97 intel_batchbuffer_reset(batch
, bufmgr
, devinfo
->has_llc
);
100 #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
103 add_exec_bo(struct intel_batchbuffer
*batch
, struct brw_bo
*bo
)
105 unsigned index
= READ_ONCE(bo
->index
);
107 if (index
< batch
->exec_count
&& batch
->exec_bos
[index
] == bo
)
110 /* May have been shared between multiple active batches */
111 for (index
= 0; index
< batch
->exec_count
; index
++) {
112 if (batch
->exec_bos
[index
] == bo
)
117 brw_bo_reference(bo
);
119 if (batch
->exec_count
== batch
->exec_array_size
) {
120 batch
->exec_array_size
*= 2;
122 realloc(batch
->exec_bos
,
123 batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
124 batch
->validation_list
=
125 realloc(batch
->validation_list
,
126 batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
129 batch
->validation_list
[batch
->exec_count
] =
130 (struct drm_i915_gem_exec_object2
) {
131 .handle
= bo
->gem_handle
,
132 .alignment
= bo
->align
,
133 .offset
= bo
->offset64
,
137 bo
->index
= batch
->exec_count
;
138 batch
->exec_bos
[batch
->exec_count
] = bo
;
139 batch
->aperture_space
+= bo
->size
;
141 return batch
->exec_count
++;
145 intel_batchbuffer_reset(struct intel_batchbuffer
*batch
,
146 struct brw_bufmgr
*bufmgr
,
149 if (batch
->last_bo
!= NULL
) {
150 brw_bo_unreference(batch
->last_bo
);
151 batch
->last_bo
= NULL
;
153 batch
->last_bo
= batch
->bo
;
155 batch
->bo
= brw_bo_alloc(bufmgr
, "batchbuffer", BATCH_SZ
, 4096);
157 batch
->map
= brw_bo_map(NULL
, batch
->bo
, MAP_READ
| MAP_WRITE
);
159 batch
->map_next
= batch
->map
;
161 add_exec_bo(batch
, batch
->bo
);
162 assert(batch
->bo
->index
== 0);
164 batch
->reserved_space
= BATCH_RESERVED
;
165 batch
->state_batch_offset
= batch
->bo
->size
;
166 batch
->needs_sol_reset
= false;
167 batch
->state_base_address_emitted
= false;
169 /* We don't know what ring the new batch will be sent to until we see the
170 * first BEGIN_BATCH or BEGIN_BATCH_BLT. Mark it as unknown.
172 batch
->ring
= UNKNOWN_RING
;
174 if (batch
->state_batch_sizes
)
175 _mesa_hash_table_clear(batch
->state_batch_sizes
, NULL
);
179 intel_batchbuffer_reset_and_clear_render_cache(struct brw_context
*brw
)
181 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
183 intel_batchbuffer_reset(&brw
->batch
, brw
->bufmgr
, devinfo
->has_llc
);
184 brw_render_cache_set_clear(brw
);
188 intel_batchbuffer_save_state(struct brw_context
*brw
)
190 brw
->batch
.saved
.map_next
= brw
->batch
.map_next
;
191 brw
->batch
.saved
.reloc_count
= brw
->batch
.reloc_count
;
192 brw
->batch
.saved
.exec_count
= brw
->batch
.exec_count
;
196 intel_batchbuffer_reset_to_saved(struct brw_context
*brw
)
198 for (int i
= brw
->batch
.saved
.exec_count
;
199 i
< brw
->batch
.exec_count
; i
++) {
200 if (brw
->batch
.exec_bos
[i
] != brw
->batch
.bo
) {
201 brw_bo_unreference(brw
->batch
.exec_bos
[i
]);
204 brw
->batch
.reloc_count
= brw
->batch
.saved
.reloc_count
;
205 brw
->batch
.exec_count
= brw
->batch
.saved
.exec_count
;
207 brw
->batch
.map_next
= brw
->batch
.saved
.map_next
;
208 if (USED_BATCH(brw
->batch
) == 0)
209 brw
->batch
.ring
= UNKNOWN_RING
;
213 intel_batchbuffer_free(struct intel_batchbuffer
*batch
)
215 free(batch
->cpu_map
);
217 for (int i
= 0; i
< batch
->exec_count
; i
++) {
218 if (batch
->exec_bos
[i
] != batch
->bo
) {
219 brw_bo_unreference(batch
->exec_bos
[i
]);
223 free(batch
->exec_bos
);
224 free(batch
->validation_list
);
226 brw_bo_unreference(batch
->last_bo
);
227 brw_bo_unreference(batch
->bo
);
228 if (batch
->state_batch_sizes
)
229 _mesa_hash_table_destroy(batch
->state_batch_sizes
, NULL
);
233 intel_batchbuffer_require_space(struct brw_context
*brw
, GLuint sz
,
234 enum brw_gpu_ring ring
)
236 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
238 /* If we're switching rings, implicitly flush the batch. */
239 if (unlikely(ring
!= brw
->batch
.ring
) && brw
->batch
.ring
!= UNKNOWN_RING
&&
241 intel_batchbuffer_flush(brw
);
245 assert(sz
< BATCH_SZ
- BATCH_RESERVED
);
247 if (intel_batchbuffer_space(&brw
->batch
) < sz
)
248 intel_batchbuffer_flush(brw
);
250 /* The intel_batchbuffer_flush() calls above might have changed
251 * brw->batch.ring to UNKNOWN_RING, so we need to set it here at the end.
253 brw
->batch
.ring
= ring
;
258 #define BLUE_HEADER CSI "0;44m"
259 #define NORMAL CSI "0m"
263 decode_struct(struct brw_context
*brw
, struct gen_spec
*spec
,
264 const char *struct_name
, uint32_t *data
,
265 uint32_t gtt_offset
, uint32_t offset
, bool color
)
267 struct gen_group
*group
= gen_spec_find_struct(spec
, struct_name
);
271 fprintf(stderr
, "%s\n", struct_name
);
272 gen_print_group(stderr
, group
, gtt_offset
+ offset
,
273 &data
[offset
/ 4], color
);
277 decode_structs(struct brw_context
*brw
, struct gen_spec
*spec
,
278 const char *struct_name
,
279 uint32_t *data
, uint32_t gtt_offset
, uint32_t offset
,
280 int struct_size
, bool color
)
282 struct gen_group
*group
= gen_spec_find_struct(spec
, struct_name
);
286 int entries
= brw_state_batch_size(brw
, offset
) / struct_size
;
287 for (int i
= 0; i
< entries
; i
++) {
288 fprintf(stderr
, "%s %d\n", struct_name
, i
);
289 gen_print_group(stderr
, group
, gtt_offset
+ offset
,
290 &data
[(offset
+ i
* struct_size
) / 4], color
);
295 do_batch_dump(struct brw_context
*brw
)
297 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
298 struct intel_batchbuffer
*batch
= &brw
->batch
;
299 struct gen_spec
*spec
= gen_spec_load(&brw
->screen
->devinfo
);
301 if (batch
->ring
!= RENDER_RING
)
304 void *map
= brw_bo_map(brw
, batch
->bo
, MAP_READ
);
307 "WARNING: failed to map batchbuffer, "
308 "dumping uploaded data instead.\n");
311 uint32_t *data
= map
? map
: batch
->map
;
312 uint32_t *end
= data
+ USED_BATCH(*batch
);
313 uint32_t gtt_offset
= map
? batch
->bo
->offset64
: 0;
316 bool color
= INTEL_DEBUG
& DEBUG_COLOR
;
317 const char *header_color
= color
? BLUE_HEADER
: "";
318 const char *reset_color
= color
? NORMAL
: "";
320 for (uint32_t *p
= data
; p
< end
; p
+= length
) {
321 struct gen_group
*inst
= gen_spec_find_instruction(spec
, p
);
322 length
= gen_group_get_length(inst
, p
);
323 assert(inst
== NULL
|| length
> 0);
324 length
= MAX2(1, length
);
326 fprintf(stderr
, "unknown instruction %08x\n", p
[0]);
330 uint64_t offset
= gtt_offset
+ 4 * (p
- data
);
332 fprintf(stderr
, "%s0x%08"PRIx64
": 0x%08x: %-80s%s\n", header_color
,
333 offset
, p
[0], gen_group_get_name(inst
), reset_color
);
335 gen_print_group(stderr
, inst
, offset
, p
, color
);
337 switch (gen_group_get_opcode(inst
) >> 16) {
338 case _3DSTATE_PIPELINED_POINTERS
:
339 /* Note: these Gen4-5 pointers are full relocations rather than
340 * offsets from the start of the batch. So we need to subtract
341 * gtt_offset (the start of the batch) to obtain an offset we
342 * can add to the map and get at the data.
344 decode_struct(brw
, spec
, "VS_STATE", data
, gtt_offset
,
345 (p
[1] & ~0x1fu
) - gtt_offset
, color
);
347 decode_struct(brw
, spec
, "GS_STATE", data
, gtt_offset
,
348 (p
[2] & ~0x1fu
) - gtt_offset
, color
);
351 decode_struct(brw
, spec
, "CLIP_STATE", data
, gtt_offset
,
352 (p
[3] & ~0x1fu
) - gtt_offset
, color
);
354 decode_struct(brw
, spec
, "SF_STATE", data
, gtt_offset
,
355 (p
[4] & ~0x1fu
) - gtt_offset
, color
);
356 decode_struct(brw
, spec
, "WM_STATE", data
, gtt_offset
,
357 (p
[5] & ~0x1fu
) - gtt_offset
, color
);
358 decode_struct(brw
, spec
, "COLOR_CALC_STATE", data
, gtt_offset
,
359 (p
[6] & ~0x3fu
) - gtt_offset
, color
);
361 case _3DSTATE_BINDING_TABLE_POINTERS_VS
:
362 case _3DSTATE_BINDING_TABLE_POINTERS_HS
:
363 case _3DSTATE_BINDING_TABLE_POINTERS_DS
:
364 case _3DSTATE_BINDING_TABLE_POINTERS_GS
:
365 case _3DSTATE_BINDING_TABLE_POINTERS_PS
: {
366 struct gen_group
*group
=
367 gen_spec_find_struct(spec
, "RENDER_SURFACE_STATE");
371 uint32_t bt_offset
= p
[1] & ~0x1fu
;
372 int bt_entries
= brw_state_batch_size(brw
, bt_offset
) / 4;
373 uint32_t *bt_pointers
= &data
[bt_offset
/ 4];
374 for (int i
= 0; i
< bt_entries
; i
++) {
375 fprintf(stderr
, "SURFACE_STATE - BTI = %d\n", i
);
376 gen_print_group(stderr
, group
, gtt_offset
+ bt_pointers
[i
],
377 &data
[bt_pointers
[i
] / 4], color
);
381 case _3DSTATE_SAMPLER_STATE_POINTERS_VS
:
382 case _3DSTATE_SAMPLER_STATE_POINTERS_HS
:
383 case _3DSTATE_SAMPLER_STATE_POINTERS_DS
:
384 case _3DSTATE_SAMPLER_STATE_POINTERS_GS
:
385 case _3DSTATE_SAMPLER_STATE_POINTERS_PS
:
386 decode_structs(brw
, spec
, "SAMPLER_STATE", data
,
387 gtt_offset
, p
[1] & ~0x1fu
, 4 * 4, color
);
389 case _3DSTATE_VIEWPORT_STATE_POINTERS
:
390 decode_structs(brw
, spec
, "CLIP_VIEWPORT", data
,
391 gtt_offset
, p
[1] & ~0x3fu
, 4 * 4, color
);
392 decode_structs(brw
, spec
, "SF_VIEWPORT", data
,
393 gtt_offset
, p
[1] & ~0x3fu
, 8 * 4, color
);
394 decode_structs(brw
, spec
, "CC_VIEWPORT", data
,
395 gtt_offset
, p
[3] & ~0x3fu
, 2 * 4, color
);
397 case _3DSTATE_VIEWPORT_STATE_POINTERS_CC
:
398 decode_structs(brw
, spec
, "CC_VIEWPORT", data
,
399 gtt_offset
, p
[1] & ~0x3fu
, 2 * 4, color
);
401 case _3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL
:
402 decode_structs(brw
, spec
, "SF_CLIP_VIEWPORT", data
,
403 gtt_offset
, p
[1] & ~0x3fu
, 16 * 4, color
);
405 case _3DSTATE_SCISSOR_STATE_POINTERS
:
406 decode_structs(brw
, spec
, "SCISSOR_RECT", data
,
407 gtt_offset
, p
[1] & ~0x1fu
, 2 * 4, color
);
409 case _3DSTATE_BLEND_STATE_POINTERS
:
410 /* TODO: handle Gen8+ extra dword at the beginning */
411 decode_structs(brw
, spec
, "BLEND_STATE", data
,
412 gtt_offset
, p
[1] & ~0x3fu
, 8 * 4, color
);
414 case _3DSTATE_CC_STATE_POINTERS
:
415 if (devinfo
->gen
>= 7) {
416 decode_struct(brw
, spec
, "COLOR_CALC_STATE", data
,
417 gtt_offset
, p
[1] & ~0x3fu
, color
);
418 } else if (devinfo
->gen
== 6) {
419 decode_structs(brw
, spec
, "BLEND_STATE", data
,
420 gtt_offset
, p
[1] & ~0x3fu
, 2 * 4, color
);
421 decode_struct(brw
, spec
, "DEPTH_STENCIL_STATE", data
,
422 gtt_offset
, p
[2] & ~0x3fu
, color
);
423 decode_struct(brw
, spec
, "COLOR_CALC_STATE", data
,
424 gtt_offset
, p
[3] & ~0x3fu
, color
);
427 case _3DSTATE_DEPTH_STENCIL_STATE_POINTERS
:
428 decode_struct(brw
, spec
, "DEPTH_STENCIL_STATE", data
,
429 gtt_offset
, p
[1] & ~0x3fu
, color
);
435 brw_bo_unmap(batch
->bo
);
439 static void do_batch_dump(struct brw_context
*brw
) { }
443 * Called when starting a new batch buffer.
446 brw_new_batch(struct brw_context
*brw
)
448 /* Unreference any BOs held by the previous batch, and reset counts. */
449 for (int i
= 0; i
< brw
->batch
.exec_count
; i
++) {
450 if (brw
->batch
.exec_bos
[i
] != brw
->batch
.bo
) {
451 brw_bo_unreference(brw
->batch
.exec_bos
[i
]);
453 brw
->batch
.exec_bos
[i
] = NULL
;
455 brw
->batch
.reloc_count
= 0;
456 brw
->batch
.exec_count
= 0;
457 brw
->batch
.aperture_space
= BATCH_SZ
;
459 /* Create a new batchbuffer and reset the associated state: */
460 intel_batchbuffer_reset_and_clear_render_cache(brw
);
462 /* If the kernel supports hardware contexts, then most hardware state is
463 * preserved between batches; we only need to re-emit state that is required
464 * to be in every batch. Otherwise we need to re-emit all the state that
465 * would otherwise be stored in the context (which for all intents and
466 * purposes means everything).
468 if (brw
->hw_ctx
== 0)
469 brw
->ctx
.NewDriverState
|= BRW_NEW_CONTEXT
;
471 brw
->ctx
.NewDriverState
|= BRW_NEW_BATCH
;
473 brw
->ib
.index_size
= -1;
475 /* We need to periodically reap the shader time results, because rollover
476 * happens every few seconds. We also want to see results every once in a
477 * while, because many programs won't cleanly destroy our context, so the
478 * end-of-run printout may not happen.
480 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
481 brw_collect_and_report_shader_time(brw
);
485 * Called from intel_batchbuffer_flush before emitting MI_BATCHBUFFER_END and
488 * This function can emit state (say, to preserve registers that aren't saved
489 * between batches). All of this state MUST fit in the reserved space at the
490 * end of the batchbuffer. If you add more GPU state, increase the reserved
491 * space by updating the BATCH_RESERVED macro.
494 brw_finish_batch(struct brw_context
*brw
)
496 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
498 /* Capture the closing pipeline statistics register values necessary to
499 * support query objects (in the non-hardware context world).
501 brw_emit_query_end(brw
);
503 if (brw
->batch
.ring
== RENDER_RING
) {
504 /* Work around L3 state leaks into contexts set MI_RESTORE_INHIBIT which
505 * assume that the L3 cache is configured according to the hardware
508 if (devinfo
->gen
>= 7)
509 gen7_restore_default_l3_config(brw
);
511 if (devinfo
->is_haswell
) {
512 /* From the Haswell PRM, Volume 2b, Command Reference: Instructions,
513 * 3DSTATE_CC_STATE_POINTERS > "Note":
515 * "SW must program 3DSTATE_CC_STATE_POINTERS command at the end of every
516 * 3D batch buffer followed by a PIPE_CONTROL with RC flush and CS stall."
518 * From the example in the docs, it seems to expect a regular pipe control
519 * flush here as well. We may have done it already, but meh.
521 * See also WaAvoidRCZCounterRollover.
523 brw_emit_mi_flush(brw
);
525 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (2 - 2));
526 OUT_BATCH(brw
->cc
.state_offset
| 1);
528 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
|
529 PIPE_CONTROL_CS_STALL
);
535 throttle(struct brw_context
*brw
)
537 /* Wait for the swapbuffers before the one we just emitted, so we
538 * don't get too many swaps outstanding for apps that are GPU-heavy
541 * We're using intelDRI2Flush (called from the loader before
542 * swapbuffer) and glFlush (for front buffer rendering) as the
543 * indicator that a frame is done and then throttle when we get
544 * here as we prepare to render the next frame. At this point for
545 * round trips for swap/copy and getting new buffers are done and
546 * we'll spend less time waiting on the GPU.
548 * Unfortunately, we don't have a handle to the batch containing
549 * the swap, and getting our hands on that doesn't seem worth it,
550 * so we just use the first batch we emitted after the last swap.
552 if (brw
->need_swap_throttle
&& brw
->throttle_batch
[0]) {
553 if (brw
->throttle_batch
[1]) {
554 if (!brw
->disable_throttling
) {
555 /* Pass NULL rather than brw so we avoid perf_debug warnings;
556 * stalling is common and expected here...
558 brw_bo_wait_rendering(brw
->throttle_batch
[1]);
560 brw_bo_unreference(brw
->throttle_batch
[1]);
562 brw
->throttle_batch
[1] = brw
->throttle_batch
[0];
563 brw
->throttle_batch
[0] = NULL
;
564 brw
->need_swap_throttle
= false;
565 /* Throttling here is more precise than the throttle ioctl, so skip it */
566 brw
->need_flush_throttle
= false;
569 if (brw
->need_flush_throttle
) {
570 __DRIscreen
*dri_screen
= brw
->screen
->driScrnPriv
;
571 drmCommandNone(dri_screen
->fd
, DRM_I915_GEM_THROTTLE
);
572 brw
->need_flush_throttle
= false;
578 struct intel_batchbuffer
*batch
,
585 struct drm_i915_gem_execbuffer2 execbuf
= {
586 .buffers_ptr
= (uintptr_t) batch
->validation_list
,
587 .buffer_count
= batch
->exec_count
,
588 .batch_start_offset
= 0,
591 .rsvd1
= ctx_id
, /* rsvd1 is actually the context ID */
594 unsigned long cmd
= DRM_IOCTL_I915_GEM_EXECBUFFER2
;
596 if (in_fence
!= -1) {
597 execbuf
.rsvd2
= in_fence
;
598 execbuf
.flags
|= I915_EXEC_FENCE_IN
;
601 if (out_fence
!= NULL
) {
602 cmd
= DRM_IOCTL_I915_GEM_EXECBUFFER2_WR
;
604 execbuf
.flags
|= I915_EXEC_FENCE_OUT
;
607 int ret
= drmIoctl(fd
, cmd
, &execbuf
);
611 for (int i
= 0; i
< batch
->exec_count
; i
++) {
612 struct brw_bo
*bo
= batch
->exec_bos
[i
];
617 /* Update brw_bo::offset64 */
618 if (batch
->validation_list
[i
].offset
!= bo
->offset64
) {
619 DBG("BO %d migrated: 0x%" PRIx64
" -> 0x%llx\n",
620 bo
->gem_handle
, bo
->offset64
, batch
->validation_list
[i
].offset
);
621 bo
->offset64
= batch
->validation_list
[i
].offset
;
625 if (ret
== 0 && out_fence
!= NULL
)
626 *out_fence
= execbuf
.rsvd2
>> 32;
632 do_flush_locked(struct brw_context
*brw
, int in_fence_fd
, int *out_fence_fd
)
634 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
635 __DRIscreen
*dri_screen
= brw
->screen
->driScrnPriv
;
636 struct intel_batchbuffer
*batch
= &brw
->batch
;
639 if (devinfo
->has_llc
) {
640 brw_bo_unmap(batch
->bo
);
642 ret
= brw_bo_subdata(batch
->bo
, 0, 4 * USED_BATCH(*batch
), batch
->map
);
643 if (ret
== 0 && batch
->state_batch_offset
!= batch
->bo
->size
) {
644 ret
= brw_bo_subdata(batch
->bo
,
645 batch
->state_batch_offset
,
646 batch
->bo
->size
- batch
->state_batch_offset
,
647 (char *)batch
->map
+ batch
->state_batch_offset
);
651 if (!brw
->screen
->no_hw
) {
652 /* The requirement for using I915_EXEC_NO_RELOC are:
654 * The addresses written in the objects must match the corresponding
655 * reloc.presumed_offset which in turn must match the corresponding
658 * Any render targets written to in the batch must be flagged with
661 * To avoid stalling, execobject.offset should match the current
662 * address of that object within the active context.
664 int flags
= I915_EXEC_NO_RELOC
;
666 if (devinfo
->gen
>= 6 && batch
->ring
== BLT_RING
) {
667 flags
|= I915_EXEC_BLT
;
669 flags
|= I915_EXEC_RENDER
;
671 if (batch
->needs_sol_reset
)
672 flags
|= I915_EXEC_GEN7_SOL_RESET
;
675 uint32_t hw_ctx
= batch
->ring
== RENDER_RING
? brw
->hw_ctx
: 0;
677 struct drm_i915_gem_exec_object2
*entry
= &batch
->validation_list
[0];
678 assert(entry
->handle
== batch
->bo
->gem_handle
);
679 entry
->relocation_count
= batch
->reloc_count
;
680 entry
->relocs_ptr
= (uintptr_t) batch
->relocs
;
682 if (batch
->use_batch_first
) {
683 flags
|= I915_EXEC_BATCH_FIRST
| I915_EXEC_HANDLE_LUT
;
685 /* Move the batch to the end of the validation list */
686 struct drm_i915_gem_exec_object2 tmp
;
687 const unsigned index
= batch
->exec_count
- 1;
690 *entry
= batch
->validation_list
[index
];
691 batch
->validation_list
[index
] = tmp
;
694 ret
= execbuffer(dri_screen
->fd
, batch
, hw_ctx
,
695 4 * USED_BATCH(*batch
),
696 in_fence_fd
, out_fence_fd
, flags
);
702 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
))
705 if (brw
->ctx
.Const
.ResetStrategy
== GL_LOSE_CONTEXT_ON_RESET_ARB
)
706 brw_check_for_reset(brw
);
709 fprintf(stderr
, "intel_do_flush_locked failed: %s\n", strerror(-ret
));
717 * The in_fence_fd is ignored if -1. Otherwise this function takes ownership
720 * The out_fence_fd is ignored if NULL. Otherwise, the caller takes ownership
721 * of the returned fd.
724 _intel_batchbuffer_flush_fence(struct brw_context
*brw
,
725 int in_fence_fd
, int *out_fence_fd
,
726 const char *file
, int line
)
730 if (USED_BATCH(brw
->batch
) == 0)
733 if (brw
->throttle_batch
[0] == NULL
) {
734 brw
->throttle_batch
[0] = brw
->batch
.bo
;
735 brw_bo_reference(brw
->throttle_batch
[0]);
738 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
739 int bytes_for_commands
= 4 * USED_BATCH(brw
->batch
);
740 int bytes_for_state
= brw
->batch
.bo
->size
- brw
->batch
.state_batch_offset
;
741 int total_bytes
= bytes_for_commands
+ bytes_for_state
;
742 fprintf(stderr
, "%s:%d: Batchbuffer flush with %4db (pkt) + "
743 "%4db (state) = %4db (%0.1f%%)\n", file
, line
,
744 bytes_for_commands
, bytes_for_state
,
746 100.0f
* total_bytes
/ BATCH_SZ
);
749 brw
->batch
.reserved_space
= 0;
751 brw_finish_batch(brw
);
753 /* Mark the end of the buffer. */
754 intel_batchbuffer_emit_dword(&brw
->batch
, MI_BATCH_BUFFER_END
);
755 if (USED_BATCH(brw
->batch
) & 1) {
756 /* Round batchbuffer usage to 2 DWORDs. */
757 intel_batchbuffer_emit_dword(&brw
->batch
, MI_NOOP
);
760 intel_upload_finish(brw
);
762 /* Check that we didn't just wrap our batchbuffer at a bad time. */
763 assert(!brw
->no_batch_wrap
);
765 ret
= do_flush_locked(brw
, in_fence_fd
, out_fence_fd
);
767 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
768 fprintf(stderr
, "waiting for idle\n");
769 brw_bo_wait_rendering(brw
->batch
.bo
);
772 /* Start a new batch buffer. */
779 brw_batch_has_aperture_space(struct brw_context
*brw
, unsigned extra_space
)
781 return brw
->batch
.aperture_space
+ extra_space
<=
782 brw
->screen
->aperture_threshold
;
786 brw_batch_references(struct intel_batchbuffer
*batch
, struct brw_bo
*bo
)
788 unsigned index
= READ_ONCE(bo
->index
);
789 if (index
< batch
->exec_count
&& batch
->exec_bos
[index
] == bo
)
792 for (int i
= 0; i
< batch
->exec_count
; i
++) {
793 if (batch
->exec_bos
[i
] == bo
)
799 /* This is the only way buffers get added to the validate list.
802 brw_emit_reloc(struct intel_batchbuffer
*batch
, uint32_t batch_offset
,
803 struct brw_bo
*target
, uint32_t target_offset
,
804 unsigned int reloc_flags
)
806 assert(target
!= NULL
);
808 if (batch
->reloc_count
== batch
->reloc_array_size
) {
809 batch
->reloc_array_size
*= 2;
810 batch
->relocs
= realloc(batch
->relocs
,
811 batch
->reloc_array_size
*
812 sizeof(struct drm_i915_gem_relocation_entry
));
816 assert(batch_offset
<= BATCH_SZ
- sizeof(uint32_t));
818 unsigned int index
= add_exec_bo(batch
, target
);
819 struct drm_i915_gem_exec_object2
*entry
= &batch
->validation_list
[index
];
822 entry
->flags
|= reloc_flags
& batch
->valid_reloc_flags
;
824 batch
->relocs
[batch
->reloc_count
++] =
825 (struct drm_i915_gem_relocation_entry
) {
826 .offset
= batch_offset
,
827 .delta
= target_offset
,
828 .target_handle
= batch
->use_batch_first
? index
: target
->gem_handle
,
829 .presumed_offset
= entry
->offset
,
832 /* Using the old buffer offset, write in what the right data would be, in
833 * case the buffer doesn't move and we can short-circuit the relocation
834 * processing in the kernel
836 return entry
->offset
+ target_offset
;
840 intel_batchbuffer_data(struct brw_context
*brw
,
841 const void *data
, GLuint bytes
, enum brw_gpu_ring ring
)
843 assert((bytes
& 3) == 0);
844 intel_batchbuffer_require_space(brw
, bytes
, ring
);
845 memcpy(brw
->batch
.map_next
, data
, bytes
);
846 brw
->batch
.map_next
+= bytes
>> 2;
850 load_sized_register_mem(struct brw_context
*brw
,
856 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
859 /* MI_LOAD_REGISTER_MEM only exists on Gen7+. */
860 assert(devinfo
->gen
>= 7);
862 if (devinfo
->gen
>= 8) {
863 BEGIN_BATCH(4 * size
);
864 for (i
= 0; i
< size
; i
++) {
865 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (4 - 2));
866 OUT_BATCH(reg
+ i
* 4);
867 OUT_RELOC64(bo
, 0, offset
+ i
* 4);
871 BEGIN_BATCH(3 * size
);
872 for (i
= 0; i
< size
; i
++) {
873 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (3 - 2));
874 OUT_BATCH(reg
+ i
* 4);
875 OUT_RELOC(bo
, 0, offset
+ i
* 4);
882 brw_load_register_mem(struct brw_context
*brw
,
887 load_sized_register_mem(brw
, reg
, bo
, offset
, 1);
891 brw_load_register_mem64(struct brw_context
*brw
,
896 load_sized_register_mem(brw
, reg
, bo
, offset
, 2);
900 * Write an arbitrary 32-bit register to a buffer via MI_STORE_REGISTER_MEM.
903 brw_store_register_mem32(struct brw_context
*brw
,
904 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
)
906 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
908 assert(devinfo
->gen
>= 6);
910 if (devinfo
->gen
>= 8) {
912 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
914 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
918 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
920 OUT_RELOC(bo
, RELOC_WRITE
| RELOC_NEEDS_GGTT
, offset
);
926 * Write an arbitrary 64-bit register to a buffer via MI_STORE_REGISTER_MEM.
929 brw_store_register_mem64(struct brw_context
*brw
,
930 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
)
932 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
934 assert(devinfo
->gen
>= 6);
936 /* MI_STORE_REGISTER_MEM only stores a single 32-bit value, so to
937 * read a full 64-bit register, we need to do two of them.
939 if (devinfo
->gen
>= 8) {
941 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
943 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
944 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
945 OUT_BATCH(reg
+ sizeof(uint32_t));
946 OUT_RELOC64(bo
, RELOC_WRITE
, offset
+ sizeof(uint32_t));
950 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
952 OUT_RELOC(bo
, RELOC_WRITE
| RELOC_NEEDS_GGTT
, offset
);
953 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
954 OUT_BATCH(reg
+ sizeof(uint32_t));
955 OUT_RELOC(bo
, RELOC_WRITE
| RELOC_NEEDS_GGTT
, offset
+ sizeof(uint32_t));
961 * Write a 32-bit register using immediate data.
964 brw_load_register_imm32(struct brw_context
*brw
, uint32_t reg
, uint32_t imm
)
966 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
968 assert(devinfo
->gen
>= 6);
971 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
978 * Write a 64-bit register using immediate data.
981 brw_load_register_imm64(struct brw_context
*brw
, uint32_t reg
, uint64_t imm
)
983 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
985 assert(devinfo
->gen
>= 6);
988 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (5 - 2));
990 OUT_BATCH(imm
& 0xffffffff);
992 OUT_BATCH(imm
>> 32);
997 * Copies a 32-bit register.
1000 brw_load_register_reg(struct brw_context
*brw
, uint32_t src
, uint32_t dest
)
1002 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1004 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
);
1007 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1014 * Copies a 64-bit register.
1017 brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
, uint32_t dest
)
1019 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1021 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
);
1024 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1027 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1028 OUT_BATCH(src
+ sizeof(uint32_t));
1029 OUT_BATCH(dest
+ sizeof(uint32_t));
1034 * Write 32-bits of immediate data to a GPU memory buffer.
1037 brw_store_data_imm32(struct brw_context
*brw
, struct brw_bo
*bo
,
1038 uint32_t offset
, uint32_t imm
)
1040 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1042 assert(devinfo
->gen
>= 6);
1045 OUT_BATCH(MI_STORE_DATA_IMM
| (4 - 2));
1046 if (devinfo
->gen
>= 8)
1047 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
1049 OUT_BATCH(0); /* MBZ */
1050 OUT_RELOC(bo
, RELOC_WRITE
, offset
);
1057 * Write 64-bits of immediate data to a GPU memory buffer.
1060 brw_store_data_imm64(struct brw_context
*brw
, struct brw_bo
*bo
,
1061 uint32_t offset
, uint64_t imm
)
1063 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1065 assert(devinfo
->gen
>= 6);
1068 OUT_BATCH(MI_STORE_DATA_IMM
| (5 - 2));
1069 if (devinfo
->gen
>= 8)
1070 OUT_RELOC64(bo
, 0, offset
);
1072 OUT_BATCH(0); /* MBZ */
1073 OUT_RELOC(bo
, RELOC_WRITE
, offset
);
1075 OUT_BATCH(imm
& 0xffffffffu
);
1076 OUT_BATCH(imm
>> 32);