2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "intel_batchbuffer.h"
27 #include "intel_buffer_objects.h"
28 #include "brw_bufmgr.h"
29 #include "intel_buffers.h"
30 #include "intel_fbo.h"
31 #include "brw_context.h"
32 #include "brw_defines.h"
33 #include "brw_state.h"
34 #include "common/gen_decoder.h"
36 #include "util/hash_table.h"
41 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
44 * Target sizes of the batch and state buffers. We create the initial
45 * buffers at these sizes, and flush when they're nearly full. If we
46 * underestimate how close we are to the end, and suddenly need more space
47 * in the middle of a draw, we can grow the buffers, and finish the draw.
48 * At that point, we'll be over our target size, so the next operation
49 * should flush. Each time we flush the batch, we recreate both buffers
50 * at the original target size, so it doesn't grow without bound.
52 #define BATCH_SZ (20 * 1024)
53 #define STATE_SZ (16 * 1024)
56 intel_batchbuffer_reset(struct brw_context
*brw
);
59 uint_key_compare(const void *a
, const void *b
)
65 uint_key_hash(const void *key
)
67 return (uintptr_t) key
;
71 init_reloc_list(struct brw_reloc_list
*rlist
, int count
)
73 rlist
->reloc_count
= 0;
74 rlist
->reloc_array_size
= count
;
75 rlist
->relocs
= malloc(rlist
->reloc_array_size
*
76 sizeof(struct drm_i915_gem_relocation_entry
));
80 intel_batchbuffer_init(struct brw_context
*brw
)
82 struct intel_screen
*screen
= brw
->screen
;
83 struct intel_batchbuffer
*batch
= &brw
->batch
;
84 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
86 if (!devinfo
->has_llc
) {
87 batch
->batch_cpu_map
= malloc(BATCH_SZ
);
88 batch
->map
= batch
->batch_cpu_map
;
89 batch
->map_next
= batch
->map
;
90 batch
->state_cpu_map
= malloc(STATE_SZ
);
91 batch
->state_map
= batch
->state_cpu_map
;
94 init_reloc_list(&batch
->batch_relocs
, 250);
95 init_reloc_list(&batch
->state_relocs
, 250);
97 batch
->exec_count
= 0;
98 batch
->exec_array_size
= 100;
100 malloc(batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
101 batch
->validation_list
=
102 malloc(batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
104 if (INTEL_DEBUG
& DEBUG_BATCH
) {
105 batch
->state_batch_sizes
=
106 _mesa_hash_table_create(NULL
, uint_key_hash
, uint_key_compare
);
109 batch
->use_batch_first
=
110 screen
->kernel_features
& KERNEL_ALLOWS_EXEC_BATCH_FIRST
;
112 /* PIPE_CONTROL needs a w/a but only on gen6 */
113 batch
->valid_reloc_flags
= EXEC_OBJECT_WRITE
;
114 if (devinfo
->gen
== 6)
115 batch
->valid_reloc_flags
|= EXEC_OBJECT_NEEDS_GTT
;
117 intel_batchbuffer_reset(brw
);
120 #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
123 add_exec_bo(struct intel_batchbuffer
*batch
, struct brw_bo
*bo
)
125 unsigned index
= READ_ONCE(bo
->index
);
127 if (index
< batch
->exec_count
&& batch
->exec_bos
[index
] == bo
)
130 /* May have been shared between multiple active batches */
131 for (index
= 0; index
< batch
->exec_count
; index
++) {
132 if (batch
->exec_bos
[index
] == bo
)
136 brw_bo_reference(bo
);
138 if (batch
->exec_count
== batch
->exec_array_size
) {
139 batch
->exec_array_size
*= 2;
141 realloc(batch
->exec_bos
,
142 batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
143 batch
->validation_list
=
144 realloc(batch
->validation_list
,
145 batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
148 batch
->validation_list
[batch
->exec_count
] =
149 (struct drm_i915_gem_exec_object2
) {
150 .handle
= bo
->gem_handle
,
151 .alignment
= bo
->align
,
152 .offset
= bo
->gtt_offset
,
156 bo
->index
= batch
->exec_count
;
157 batch
->exec_bos
[batch
->exec_count
] = bo
;
158 batch
->aperture_space
+= bo
->size
;
160 return batch
->exec_count
++;
164 intel_batchbuffer_reset(struct brw_context
*brw
)
166 struct intel_screen
*screen
= brw
->screen
;
167 struct intel_batchbuffer
*batch
= &brw
->batch
;
168 struct brw_bufmgr
*bufmgr
= screen
->bufmgr
;
170 if (batch
->last_bo
!= NULL
) {
171 brw_bo_unreference(batch
->last_bo
);
172 batch
->last_bo
= NULL
;
174 batch
->last_bo
= batch
->bo
;
176 batch
->bo
= brw_bo_alloc(bufmgr
, "batchbuffer", BATCH_SZ
, 4096);
177 if (!batch
->batch_cpu_map
) {
178 batch
->map
= brw_bo_map(brw
, batch
->bo
, MAP_READ
| MAP_WRITE
);
180 batch
->map_next
= batch
->map
;
182 batch
->state_bo
= brw_bo_alloc(bufmgr
, "statebuffer", STATE_SZ
, 4096);
183 batch
->state_bo
->kflags
=
184 can_do_exec_capture(screen
) ? EXEC_OBJECT_CAPTURE
: 0;
185 if (!batch
->state_cpu_map
) {
187 brw_bo_map(brw
, batch
->state_bo
, MAP_READ
| MAP_WRITE
);
190 /* Avoid making 0 a valid state offset - otherwise the decoder will try
191 * and decode data when we use offset 0 as a null pointer.
193 batch
->state_used
= 1;
195 add_exec_bo(batch
, batch
->bo
);
196 assert(batch
->bo
->index
== 0);
198 batch
->needs_sol_reset
= false;
199 batch
->state_base_address_emitted
= false;
201 /* We don't know what ring the new batch will be sent to until we see the
202 * first BEGIN_BATCH or BEGIN_BATCH_BLT. Mark it as unknown.
204 batch
->ring
= UNKNOWN_RING
;
206 if (batch
->state_batch_sizes
)
207 _mesa_hash_table_clear(batch
->state_batch_sizes
, NULL
);
211 intel_batchbuffer_reset_and_clear_render_cache(struct brw_context
*brw
)
213 intel_batchbuffer_reset(brw
);
214 brw_cache_sets_clear(brw
);
218 intel_batchbuffer_save_state(struct brw_context
*brw
)
220 brw
->batch
.saved
.map_next
= brw
->batch
.map_next
;
221 brw
->batch
.saved
.batch_reloc_count
= brw
->batch
.batch_relocs
.reloc_count
;
222 brw
->batch
.saved
.state_reloc_count
= brw
->batch
.state_relocs
.reloc_count
;
223 brw
->batch
.saved
.exec_count
= brw
->batch
.exec_count
;
227 intel_batchbuffer_reset_to_saved(struct brw_context
*brw
)
229 for (int i
= brw
->batch
.saved
.exec_count
;
230 i
< brw
->batch
.exec_count
; i
++) {
231 brw_bo_unreference(brw
->batch
.exec_bos
[i
]);
233 brw
->batch
.batch_relocs
.reloc_count
= brw
->batch
.saved
.batch_reloc_count
;
234 brw
->batch
.state_relocs
.reloc_count
= brw
->batch
.saved
.state_reloc_count
;
235 brw
->batch
.exec_count
= brw
->batch
.saved
.exec_count
;
237 brw
->batch
.map_next
= brw
->batch
.saved
.map_next
;
238 if (USED_BATCH(brw
->batch
) == 0)
239 brw
->batch
.ring
= UNKNOWN_RING
;
243 intel_batchbuffer_free(struct intel_batchbuffer
*batch
)
245 free(batch
->batch_cpu_map
);
246 free(batch
->state_cpu_map
);
248 for (int i
= 0; i
< batch
->exec_count
; i
++) {
249 brw_bo_unreference(batch
->exec_bos
[i
]);
251 free(batch
->batch_relocs
.relocs
);
252 free(batch
->state_relocs
.relocs
);
253 free(batch
->exec_bos
);
254 free(batch
->validation_list
);
256 brw_bo_unreference(batch
->last_bo
);
257 brw_bo_unreference(batch
->bo
);
258 brw_bo_unreference(batch
->state_bo
);
259 if (batch
->state_batch_sizes
)
260 _mesa_hash_table_destroy(batch
->state_batch_sizes
, NULL
);
264 replace_bo_in_reloc_list(struct brw_reloc_list
*rlist
,
265 uint32_t old_handle
, uint32_t new_handle
)
267 for (int i
= 0; i
< rlist
->reloc_count
; i
++) {
268 if (rlist
->relocs
[i
].target_handle
== old_handle
)
269 rlist
->relocs
[i
].target_handle
= new_handle
;
274 * Grow either the batch or state buffer to a new larger size.
276 * We can't actually grow buffers, so we allocate a new one, copy over
277 * the existing contents, and update our lists to refer to the new one.
279 * Note that this is only temporary - each new batch recreates the buffers
280 * at their original target size (BATCH_SZ or STATE_SZ).
283 grow_buffer(struct brw_context
*brw
,
284 struct brw_bo
**bo_ptr
,
286 uint32_t **cpu_map_ptr
,
287 unsigned existing_bytes
,
290 struct intel_batchbuffer
*batch
= &brw
->batch
;
291 struct brw_bufmgr
*bufmgr
= brw
->bufmgr
;
293 uint32_t *old_map
= *map_ptr
;
294 struct brw_bo
*old_bo
= *bo_ptr
;
296 struct brw_bo
*new_bo
=
297 brw_bo_alloc(bufmgr
, old_bo
->name
, new_size
, old_bo
->align
);
300 perf_debug("Growing %s - ran out of space\n", old_bo
->name
);
302 /* Copy existing data to the new larger buffer */
304 *cpu_map_ptr
= new_map
= realloc(*cpu_map_ptr
, new_size
);
306 new_map
= brw_bo_map(brw
, new_bo
, MAP_READ
| MAP_WRITE
);
307 memcpy(new_map
, old_map
, existing_bytes
);
310 /* Try to put the new BO at the same GTT offset as the old BO (which
311 * we're throwing away, so it doesn't need to be there).
313 * This guarantees that our relocations continue to work: values we've
314 * already written into the buffer, values we're going to write into the
315 * buffer, and the validation/relocation lists all will match.
317 * Also preserve kflags for EXEC_OBJECT_CAPTURE.
319 new_bo
->gtt_offset
= old_bo
->gtt_offset
;
320 new_bo
->index
= old_bo
->index
;
321 new_bo
->kflags
= old_bo
->kflags
;
323 /* Batch/state buffers are per-context, and if we've run out of space,
324 * we must have actually used them before, so...they will be in the list.
326 assert(old_bo
->index
< batch
->exec_count
);
327 assert(batch
->exec_bos
[old_bo
->index
] == old_bo
);
329 /* Update the validation list to use the new BO. */
330 batch
->exec_bos
[old_bo
->index
] = new_bo
;
331 batch
->validation_list
[old_bo
->index
].handle
= new_bo
->gem_handle
;
332 brw_bo_reference(new_bo
);
333 brw_bo_unreference(old_bo
);
335 if (!batch
->use_batch_first
) {
336 /* We're not using I915_EXEC_HANDLE_LUT, which means we need to go
337 * update the relocation list entries to point at the new BO as well.
338 * (With newer kernels, the "handle" is an offset into the validation
339 * list, which remains unchanged, so we can skip this.)
341 replace_bo_in_reloc_list(&batch
->batch_relocs
,
342 old_bo
->gem_handle
, new_bo
->gem_handle
);
343 replace_bo_in_reloc_list(&batch
->state_relocs
,
344 old_bo
->gem_handle
, new_bo
->gem_handle
);
347 /* Drop the *bo_ptr reference. This should free the old BO. */
348 brw_bo_unreference(old_bo
);
355 intel_batchbuffer_require_space(struct brw_context
*brw
, GLuint sz
,
356 enum brw_gpu_ring ring
)
358 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
359 struct intel_batchbuffer
*batch
= &brw
->batch
;
361 /* If we're switching rings, implicitly flush the batch. */
362 if (unlikely(ring
!= brw
->batch
.ring
) && brw
->batch
.ring
!= UNKNOWN_RING
&&
364 intel_batchbuffer_flush(brw
);
367 const unsigned batch_used
= USED_BATCH(*batch
) * 4;
368 if (batch_used
+ sz
>= BATCH_SZ
&& !batch
->no_wrap
) {
369 intel_batchbuffer_flush(brw
);
370 } else if (batch_used
+ sz
>= batch
->bo
->size
) {
371 const unsigned new_size
=
372 MIN2(batch
->bo
->size
+ batch
->bo
->size
/ 2, MAX_BATCH_SIZE
);
373 grow_buffer(brw
, &batch
->bo
, &batch
->map
, &batch
->batch_cpu_map
,
374 batch_used
, new_size
);
375 batch
->map_next
= (void *) batch
->map
+ batch_used
;
376 assert(batch_used
+ sz
< batch
->bo
->size
);
379 /* The intel_batchbuffer_flush() calls above might have changed
380 * brw->batch.ring to UNKNOWN_RING, so we need to set it here at the end.
382 brw
->batch
.ring
= ring
;
387 #define BLUE_HEADER CSI "0;44m"
388 #define NORMAL CSI "0m"
392 decode_struct(struct brw_context
*brw
, struct gen_spec
*spec
,
393 const char *struct_name
, uint32_t *data
,
394 uint32_t gtt_offset
, uint32_t offset
, bool color
)
396 struct gen_group
*group
= gen_spec_find_struct(spec
, struct_name
);
400 fprintf(stderr
, "%s\n", struct_name
);
401 gen_print_group(stderr
, group
, gtt_offset
+ offset
,
402 &data
[offset
/ 4], color
);
406 decode_structs(struct brw_context
*brw
, struct gen_spec
*spec
,
407 const char *struct_name
,
408 uint32_t *data
, uint32_t gtt_offset
, uint32_t offset
,
409 int struct_size
, bool color
)
411 struct gen_group
*group
= gen_spec_find_struct(spec
, struct_name
);
415 int entries
= brw_state_batch_size(brw
, offset
) / struct_size
;
416 for (int i
= 0; i
< entries
; i
++) {
417 fprintf(stderr
, "%s %d\n", struct_name
, i
);
418 gen_print_group(stderr
, group
, gtt_offset
+ offset
,
419 &data
[(offset
+ i
* struct_size
) / 4], color
);
424 do_batch_dump(struct brw_context
*brw
)
426 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
427 struct intel_batchbuffer
*batch
= &brw
->batch
;
428 struct gen_spec
*spec
= gen_spec_load(&brw
->screen
->devinfo
);
430 if (batch
->ring
!= RENDER_RING
)
433 uint32_t *batch_data
= brw_bo_map(brw
, batch
->bo
, MAP_READ
);
434 uint32_t *state
= brw_bo_map(brw
, batch
->state_bo
, MAP_READ
);
435 if (batch_data
== NULL
|| state
== NULL
) {
436 fprintf(stderr
, "WARNING: failed to map batchbuffer/statebuffer\n");
440 uint32_t *end
= batch_data
+ USED_BATCH(*batch
);
441 uint32_t batch_gtt_offset
= batch
->bo
->gtt_offset
;
442 uint32_t state_gtt_offset
= batch
->state_bo
->gtt_offset
;
445 bool color
= INTEL_DEBUG
& DEBUG_COLOR
;
446 const char *header_color
= color
? BLUE_HEADER
: "";
447 const char *reset_color
= color
? NORMAL
: "";
449 for (uint32_t *p
= batch_data
; p
< end
; p
+= length
) {
450 struct gen_group
*inst
= gen_spec_find_instruction(spec
, p
);
451 length
= gen_group_get_length(inst
, p
);
452 assert(inst
== NULL
|| length
> 0);
453 length
= MAX2(1, length
);
455 fprintf(stderr
, "unknown instruction %08x\n", p
[0]);
459 uint64_t offset
= batch_gtt_offset
+ 4 * (p
- batch_data
);
461 fprintf(stderr
, "%s0x%08"PRIx64
": 0x%08x: %-80s%s\n", header_color
,
462 offset
, p
[0], gen_group_get_name(inst
), reset_color
);
464 gen_print_group(stderr
, inst
, offset
, p
, color
);
466 switch (gen_group_get_opcode(inst
) >> 16) {
467 case _3DSTATE_PIPELINED_POINTERS
:
468 /* Note: these Gen4-5 pointers are full relocations rather than
469 * offsets from the start of the statebuffer. So we need to subtract
470 * gtt_offset (the start of the statebuffer) to obtain an offset we
471 * can add to the map and get at the data.
473 decode_struct(brw
, spec
, "VS_STATE", state
, state_gtt_offset
,
474 (p
[1] & ~0x1fu
) - state_gtt_offset
, color
);
476 decode_struct(brw
, spec
, "GS_STATE", state
, state_gtt_offset
,
477 (p
[2] & ~0x1fu
) - state_gtt_offset
, color
);
480 decode_struct(brw
, spec
, "CLIP_STATE", state
, state_gtt_offset
,
481 (p
[3] & ~0x1fu
) - state_gtt_offset
, color
);
483 decode_struct(brw
, spec
, "SF_STATE", state
, state_gtt_offset
,
484 (p
[4] & ~0x1fu
) - state_gtt_offset
, color
);
485 decode_struct(brw
, spec
, "WM_STATE", state
, state_gtt_offset
,
486 (p
[5] & ~0x1fu
) - state_gtt_offset
, color
);
487 decode_struct(brw
, spec
, "COLOR_CALC_STATE", state
, state_gtt_offset
,
488 (p
[6] & ~0x3fu
) - state_gtt_offset
, color
);
490 case _3DSTATE_BINDING_TABLE_POINTERS_VS
:
491 case _3DSTATE_BINDING_TABLE_POINTERS_HS
:
492 case _3DSTATE_BINDING_TABLE_POINTERS_DS
:
493 case _3DSTATE_BINDING_TABLE_POINTERS_GS
:
494 case _3DSTATE_BINDING_TABLE_POINTERS_PS
: {
495 struct gen_group
*group
=
496 gen_spec_find_struct(spec
, "RENDER_SURFACE_STATE");
500 uint32_t bt_offset
= p
[1] & ~0x1fu
;
501 int bt_entries
= brw_state_batch_size(brw
, bt_offset
) / 4;
502 uint32_t *bt_pointers
= &state
[bt_offset
/ 4];
503 for (int i
= 0; i
< bt_entries
; i
++) {
504 fprintf(stderr
, "SURFACE_STATE - BTI = %d\n", i
);
505 gen_print_group(stderr
, group
, state_gtt_offset
+ bt_pointers
[i
],
506 &state
[bt_pointers
[i
] / 4], color
);
510 case _3DSTATE_SAMPLER_STATE_POINTERS_VS
:
511 case _3DSTATE_SAMPLER_STATE_POINTERS_HS
:
512 case _3DSTATE_SAMPLER_STATE_POINTERS_DS
:
513 case _3DSTATE_SAMPLER_STATE_POINTERS_GS
:
514 case _3DSTATE_SAMPLER_STATE_POINTERS_PS
:
515 decode_structs(brw
, spec
, "SAMPLER_STATE", state
,
516 state_gtt_offset
, p
[1] & ~0x1fu
, 4 * 4, color
);
518 case _3DSTATE_VIEWPORT_STATE_POINTERS
:
519 decode_structs(brw
, spec
, "CLIP_VIEWPORT", state
,
520 state_gtt_offset
, p
[1] & ~0x3fu
, 4 * 4, color
);
521 decode_structs(brw
, spec
, "SF_VIEWPORT", state
,
522 state_gtt_offset
, p
[1] & ~0x3fu
, 8 * 4, color
);
523 decode_structs(brw
, spec
, "CC_VIEWPORT", state
,
524 state_gtt_offset
, p
[3] & ~0x3fu
, 2 * 4, color
);
526 case _3DSTATE_VIEWPORT_STATE_POINTERS_CC
:
527 decode_structs(brw
, spec
, "CC_VIEWPORT", state
,
528 state_gtt_offset
, p
[1] & ~0x3fu
, 2 * 4, color
);
530 case _3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL
:
531 decode_structs(brw
, spec
, "SF_CLIP_VIEWPORT", state
,
532 state_gtt_offset
, p
[1] & ~0x3fu
, 16 * 4, color
);
534 case _3DSTATE_SCISSOR_STATE_POINTERS
:
535 decode_structs(brw
, spec
, "SCISSOR_RECT", state
,
536 state_gtt_offset
, p
[1] & ~0x1fu
, 2 * 4, color
);
538 case _3DSTATE_BLEND_STATE_POINTERS
:
539 /* TODO: handle Gen8+ extra dword at the beginning */
540 decode_structs(brw
, spec
, "BLEND_STATE", state
,
541 state_gtt_offset
, p
[1] & ~0x3fu
, 8 * 4, color
);
543 case _3DSTATE_CC_STATE_POINTERS
:
544 if (devinfo
->gen
>= 7) {
545 decode_struct(brw
, spec
, "COLOR_CALC_STATE", state
,
546 state_gtt_offset
, p
[1] & ~0x3fu
, color
);
547 } else if (devinfo
->gen
== 6) {
548 decode_structs(brw
, spec
, "BLEND_STATE", state
,
549 state_gtt_offset
, p
[1] & ~0x3fu
, 2 * 4, color
);
550 decode_struct(brw
, spec
, "DEPTH_STENCIL_STATE", state
,
551 state_gtt_offset
, p
[2] & ~0x3fu
, color
);
552 decode_struct(brw
, spec
, "COLOR_CALC_STATE", state
,
553 state_gtt_offset
, p
[3] & ~0x3fu
, color
);
556 case _3DSTATE_DEPTH_STENCIL_STATE_POINTERS
:
557 decode_struct(brw
, spec
, "DEPTH_STENCIL_STATE", state
,
558 state_gtt_offset
, p
[1] & ~0x3fu
, color
);
560 case MEDIA_INTERFACE_DESCRIPTOR_LOAD
: {
561 struct gen_group
*group
=
562 gen_spec_find_struct(spec
, "RENDER_SURFACE_STATE");
566 uint32_t idd_offset
= p
[3] & ~0x1fu
;
567 decode_struct(brw
, spec
, "INTERFACE_DESCRIPTOR_DATA", state
,
568 state_gtt_offset
, idd_offset
, color
);
570 uint32_t ss_offset
= state
[idd_offset
/ 4 + 3] & ~0x1fu
;
571 decode_structs(brw
, spec
, "SAMPLER_STATE", state
,
572 state_gtt_offset
, ss_offset
, 4 * 4, color
);
574 uint32_t bt_offset
= state
[idd_offset
/ 4 + 4] & ~0x1fu
;
575 int bt_entries
= brw_state_batch_size(brw
, bt_offset
) / 4;
576 uint32_t *bt_pointers
= &state
[bt_offset
/ 4];
577 for (int i
= 0; i
< bt_entries
; i
++) {
578 fprintf(stderr
, "SURFACE_STATE - BTI = %d\n", i
);
579 gen_print_group(stderr
, group
, state_gtt_offset
+ bt_pointers
[i
],
580 &state
[bt_pointers
[i
] / 4], color
);
587 brw_bo_unmap(batch
->bo
);
588 brw_bo_unmap(batch
->state_bo
);
591 static void do_batch_dump(struct brw_context
*brw
) { }
595 * Called when starting a new batch buffer.
598 brw_new_batch(struct brw_context
*brw
)
600 /* Unreference any BOs held by the previous batch, and reset counts. */
601 for (int i
= 0; i
< brw
->batch
.exec_count
; i
++) {
602 brw_bo_unreference(brw
->batch
.exec_bos
[i
]);
603 brw
->batch
.exec_bos
[i
] = NULL
;
605 brw
->batch
.batch_relocs
.reloc_count
= 0;
606 brw
->batch
.state_relocs
.reloc_count
= 0;
607 brw
->batch
.exec_count
= 0;
608 brw
->batch
.aperture_space
= 0;
610 brw_bo_unreference(brw
->batch
.state_bo
);
612 /* Create a new batchbuffer and reset the associated state: */
613 intel_batchbuffer_reset_and_clear_render_cache(brw
);
615 /* If the kernel supports hardware contexts, then most hardware state is
616 * preserved between batches; we only need to re-emit state that is required
617 * to be in every batch. Otherwise we need to re-emit all the state that
618 * would otherwise be stored in the context (which for all intents and
619 * purposes means everything).
621 if (brw
->hw_ctx
== 0) {
622 brw
->ctx
.NewDriverState
|= BRW_NEW_CONTEXT
;
623 brw_upload_invariant_state(brw
);
626 brw
->ctx
.NewDriverState
|= BRW_NEW_BATCH
;
628 brw
->ib
.index_size
= -1;
630 /* We need to periodically reap the shader time results, because rollover
631 * happens every few seconds. We also want to see results every once in a
632 * while, because many programs won't cleanly destroy our context, so the
633 * end-of-run printout may not happen.
635 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
636 brw_collect_and_report_shader_time(brw
);
640 * Called from intel_batchbuffer_flush before emitting MI_BATCHBUFFER_END and
643 * This function can emit state (say, to preserve registers that aren't saved
647 brw_finish_batch(struct brw_context
*brw
)
649 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
651 brw
->batch
.no_wrap
= true;
653 /* Capture the closing pipeline statistics register values necessary to
654 * support query objects (in the non-hardware context world).
656 brw_emit_query_end(brw
);
658 if (brw
->batch
.ring
== RENDER_RING
) {
659 /* Work around L3 state leaks into contexts set MI_RESTORE_INHIBIT which
660 * assume that the L3 cache is configured according to the hardware
663 if (devinfo
->gen
>= 7)
664 gen7_restore_default_l3_config(brw
);
666 if (devinfo
->is_haswell
) {
667 /* From the Haswell PRM, Volume 2b, Command Reference: Instructions,
668 * 3DSTATE_CC_STATE_POINTERS > "Note":
670 * "SW must program 3DSTATE_CC_STATE_POINTERS command at the end of every
671 * 3D batch buffer followed by a PIPE_CONTROL with RC flush and CS stall."
673 * From the example in the docs, it seems to expect a regular pipe control
674 * flush here as well. We may have done it already, but meh.
676 * See also WaAvoidRCZCounterRollover.
678 brw_emit_mi_flush(brw
);
680 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (2 - 2));
681 OUT_BATCH(brw
->cc
.state_offset
| 1);
683 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
|
684 PIPE_CONTROL_CS_STALL
);
688 /* Mark the end of the buffer. */
689 intel_batchbuffer_emit_dword(&brw
->batch
, MI_BATCH_BUFFER_END
);
690 if (USED_BATCH(brw
->batch
) & 1) {
691 /* Round batchbuffer usage to 2 DWORDs. */
692 intel_batchbuffer_emit_dword(&brw
->batch
, MI_NOOP
);
695 brw
->batch
.no_wrap
= false;
699 throttle(struct brw_context
*brw
)
701 /* Wait for the swapbuffers before the one we just emitted, so we
702 * don't get too many swaps outstanding for apps that are GPU-heavy
705 * We're using intelDRI2Flush (called from the loader before
706 * swapbuffer) and glFlush (for front buffer rendering) as the
707 * indicator that a frame is done and then throttle when we get
708 * here as we prepare to render the next frame. At this point for
709 * round trips for swap/copy and getting new buffers are done and
710 * we'll spend less time waiting on the GPU.
712 * Unfortunately, we don't have a handle to the batch containing
713 * the swap, and getting our hands on that doesn't seem worth it,
714 * so we just use the first batch we emitted after the last swap.
716 if (brw
->need_swap_throttle
&& brw
->throttle_batch
[0]) {
717 if (brw
->throttle_batch
[1]) {
718 if (!brw
->disable_throttling
) {
719 /* Pass NULL rather than brw so we avoid perf_debug warnings;
720 * stalling is common and expected here...
722 brw_bo_wait_rendering(brw
->throttle_batch
[1]);
724 brw_bo_unreference(brw
->throttle_batch
[1]);
726 brw
->throttle_batch
[1] = brw
->throttle_batch
[0];
727 brw
->throttle_batch
[0] = NULL
;
728 brw
->need_swap_throttle
= false;
729 /* Throttling here is more precise than the throttle ioctl, so skip it */
730 brw
->need_flush_throttle
= false;
733 if (brw
->need_flush_throttle
) {
734 __DRIscreen
*dri_screen
= brw
->screen
->driScrnPriv
;
735 drmCommandNone(dri_screen
->fd
, DRM_I915_GEM_THROTTLE
);
736 brw
->need_flush_throttle
= false;
742 struct intel_batchbuffer
*batch
,
749 struct drm_i915_gem_execbuffer2 execbuf
= {
750 .buffers_ptr
= (uintptr_t) batch
->validation_list
,
751 .buffer_count
= batch
->exec_count
,
752 .batch_start_offset
= 0,
755 .rsvd1
= ctx_id
, /* rsvd1 is actually the context ID */
758 unsigned long cmd
= DRM_IOCTL_I915_GEM_EXECBUFFER2
;
760 if (in_fence
!= -1) {
761 execbuf
.rsvd2
= in_fence
;
762 execbuf
.flags
|= I915_EXEC_FENCE_IN
;
765 if (out_fence
!= NULL
) {
766 cmd
= DRM_IOCTL_I915_GEM_EXECBUFFER2_WR
;
768 execbuf
.flags
|= I915_EXEC_FENCE_OUT
;
771 int ret
= drmIoctl(fd
, cmd
, &execbuf
);
775 for (int i
= 0; i
< batch
->exec_count
; i
++) {
776 struct brw_bo
*bo
= batch
->exec_bos
[i
];
781 /* Update brw_bo::gtt_offset */
782 if (batch
->validation_list
[i
].offset
!= bo
->gtt_offset
) {
783 DBG("BO %d migrated: 0x%" PRIx64
" -> 0x%llx\n",
784 bo
->gem_handle
, bo
->gtt_offset
,
785 batch
->validation_list
[i
].offset
);
786 bo
->gtt_offset
= batch
->validation_list
[i
].offset
;
790 if (ret
== 0 && out_fence
!= NULL
)
791 *out_fence
= execbuf
.rsvd2
>> 32;
797 submit_batch(struct brw_context
*brw
, int in_fence_fd
, int *out_fence_fd
)
799 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
800 __DRIscreen
*dri_screen
= brw
->screen
->driScrnPriv
;
801 struct intel_batchbuffer
*batch
= &brw
->batch
;
804 if (batch
->batch_cpu_map
) {
805 void *bo_map
= brw_bo_map(brw
, batch
->bo
, MAP_WRITE
);
806 memcpy(bo_map
, batch
->batch_cpu_map
, 4 * USED_BATCH(*batch
));
809 if (batch
->state_cpu_map
) {
810 void *bo_map
= brw_bo_map(brw
, batch
->state_bo
, MAP_WRITE
);
811 memcpy(bo_map
, batch
->state_cpu_map
, batch
->state_used
);
814 brw_bo_unmap(batch
->bo
);
815 brw_bo_unmap(batch
->state_bo
);
817 if (!brw
->screen
->no_hw
) {
818 /* The requirement for using I915_EXEC_NO_RELOC are:
820 * The addresses written in the objects must match the corresponding
821 * reloc.gtt_offset which in turn must match the corresponding
824 * Any render targets written to in the batch must be flagged with
827 * To avoid stalling, execobject.offset should match the current
828 * address of that object within the active context.
830 int flags
= I915_EXEC_NO_RELOC
;
832 if (devinfo
->gen
>= 6 && batch
->ring
== BLT_RING
) {
833 flags
|= I915_EXEC_BLT
;
835 flags
|= I915_EXEC_RENDER
;
837 if (batch
->needs_sol_reset
)
838 flags
|= I915_EXEC_GEN7_SOL_RESET
;
840 uint32_t hw_ctx
= batch
->ring
== RENDER_RING
? brw
->hw_ctx
: 0;
842 /* Set statebuffer relocations */
843 const unsigned state_index
= batch
->state_bo
->index
;
844 if (state_index
< batch
->exec_count
&&
845 batch
->exec_bos
[state_index
] == batch
->state_bo
) {
846 struct drm_i915_gem_exec_object2
*entry
=
847 &batch
->validation_list
[state_index
];
848 assert(entry
->handle
== batch
->state_bo
->gem_handle
);
849 entry
->relocation_count
= batch
->state_relocs
.reloc_count
;
850 entry
->relocs_ptr
= (uintptr_t) batch
->state_relocs
.relocs
;
853 /* Set batchbuffer relocations */
854 struct drm_i915_gem_exec_object2
*entry
= &batch
->validation_list
[0];
855 assert(entry
->handle
== batch
->bo
->gem_handle
);
856 entry
->relocation_count
= batch
->batch_relocs
.reloc_count
;
857 entry
->relocs_ptr
= (uintptr_t) batch
->batch_relocs
.relocs
;
859 if (batch
->use_batch_first
) {
860 flags
|= I915_EXEC_BATCH_FIRST
| I915_EXEC_HANDLE_LUT
;
862 /* Move the batch to the end of the validation list */
863 struct drm_i915_gem_exec_object2 tmp
;
864 const unsigned index
= batch
->exec_count
- 1;
867 *entry
= batch
->validation_list
[index
];
868 batch
->validation_list
[index
] = tmp
;
871 ret
= execbuffer(dri_screen
->fd
, batch
, hw_ctx
,
872 4 * USED_BATCH(*batch
),
873 in_fence_fd
, out_fence_fd
, flags
);
878 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
))
881 if (brw
->ctx
.Const
.ResetStrategy
== GL_LOSE_CONTEXT_ON_RESET_ARB
)
882 brw_check_for_reset(brw
);
885 fprintf(stderr
, "i965: Failed to submit batchbuffer: %s\n",
894 * The in_fence_fd is ignored if -1. Otherwise this function takes ownership
897 * The out_fence_fd is ignored if NULL. Otherwise, the caller takes ownership
898 * of the returned fd.
901 _intel_batchbuffer_flush_fence(struct brw_context
*brw
,
902 int in_fence_fd
, int *out_fence_fd
,
903 const char *file
, int line
)
907 if (USED_BATCH(brw
->batch
) == 0)
910 /* Check that we didn't just wrap our batchbuffer at a bad time. */
911 assert(!brw
->batch
.no_wrap
);
913 brw_finish_batch(brw
);
914 intel_upload_finish(brw
);
916 if (brw
->throttle_batch
[0] == NULL
) {
917 brw
->throttle_batch
[0] = brw
->batch
.bo
;
918 brw_bo_reference(brw
->throttle_batch
[0]);
921 if (unlikely(INTEL_DEBUG
& (DEBUG_BATCH
| DEBUG_SUBMIT
))) {
922 int bytes_for_commands
= 4 * USED_BATCH(brw
->batch
);
923 int bytes_for_state
= brw
->batch
.state_used
;
924 fprintf(stderr
, "%19s:%-3d: Batchbuffer flush with %5db (%0.1f%%) (pkt),"
925 " %5db (%0.1f%%) (state), %4d BOs (%0.1fMb aperture),"
926 " %4d batch relocs, %4d state relocs\n", file
, line
,
927 bytes_for_commands
, 100.0f
* bytes_for_commands
/ BATCH_SZ
,
928 bytes_for_state
, 100.0f
* bytes_for_state
/ STATE_SZ
,
929 brw
->batch
.exec_count
,
930 (float) brw
->batch
.aperture_space
/ (1024 * 1024),
931 brw
->batch
.batch_relocs
.reloc_count
,
932 brw
->batch
.state_relocs
.reloc_count
);
935 ret
= submit_batch(brw
, in_fence_fd
, out_fence_fd
);
937 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
938 fprintf(stderr
, "waiting for idle\n");
939 brw_bo_wait_rendering(brw
->batch
.bo
);
942 /* Start a new batch buffer. */
949 brw_batch_has_aperture_space(struct brw_context
*brw
, unsigned extra_space
)
951 return brw
->batch
.aperture_space
+ extra_space
<=
952 brw
->screen
->aperture_threshold
;
956 brw_batch_references(struct intel_batchbuffer
*batch
, struct brw_bo
*bo
)
958 unsigned index
= READ_ONCE(bo
->index
);
959 if (index
< batch
->exec_count
&& batch
->exec_bos
[index
] == bo
)
962 for (int i
= 0; i
< batch
->exec_count
; i
++) {
963 if (batch
->exec_bos
[i
] == bo
)
969 /* This is the only way buffers get added to the validate list.
972 emit_reloc(struct intel_batchbuffer
*batch
,
973 struct brw_reloc_list
*rlist
, uint32_t offset
,
974 struct brw_bo
*target
, uint32_t target_offset
,
975 unsigned int reloc_flags
)
977 assert(target
!= NULL
);
979 if (rlist
->reloc_count
== rlist
->reloc_array_size
) {
980 rlist
->reloc_array_size
*= 2;
981 rlist
->relocs
= realloc(rlist
->relocs
,
982 rlist
->reloc_array_size
*
983 sizeof(struct drm_i915_gem_relocation_entry
));
986 unsigned int index
= add_exec_bo(batch
, target
);
987 struct drm_i915_gem_exec_object2
*entry
= &batch
->validation_list
[index
];
990 entry
->flags
|= reloc_flags
& batch
->valid_reloc_flags
;
992 rlist
->relocs
[rlist
->reloc_count
++] =
993 (struct drm_i915_gem_relocation_entry
) {
995 .delta
= target_offset
,
996 .target_handle
= batch
->use_batch_first
? index
: target
->gem_handle
,
997 .presumed_offset
= entry
->offset
,
1000 /* Using the old buffer offset, write in what the right data would be, in
1001 * case the buffer doesn't move and we can short-circuit the relocation
1002 * processing in the kernel
1004 return entry
->offset
+ target_offset
;
1008 brw_batch_reloc(struct intel_batchbuffer
*batch
, uint32_t batch_offset
,
1009 struct brw_bo
*target
, uint32_t target_offset
,
1010 unsigned int reloc_flags
)
1012 assert(batch_offset
<= batch
->bo
->size
- sizeof(uint32_t));
1014 return emit_reloc(batch
, &batch
->batch_relocs
, batch_offset
,
1015 target
, target_offset
, reloc_flags
);
1019 brw_state_reloc(struct intel_batchbuffer
*batch
, uint32_t state_offset
,
1020 struct brw_bo
*target
, uint32_t target_offset
,
1021 unsigned int reloc_flags
)
1023 assert(state_offset
<= batch
->state_bo
->size
- sizeof(uint32_t));
1025 return emit_reloc(batch
, &batch
->state_relocs
, state_offset
,
1026 target
, target_offset
, reloc_flags
);
1031 brw_state_batch_size(struct brw_context
*brw
, uint32_t offset
)
1033 struct hash_entry
*entry
=
1034 _mesa_hash_table_search(brw
->batch
.state_batch_sizes
,
1035 (void *) (uintptr_t) offset
);
1036 return entry
? (uintptr_t) entry
->data
: 0;
1040 * Reserve some space in the statebuffer, or flush.
1042 * This is used to estimate when we're near the end of the batch,
1043 * so we can flush early.
1046 brw_require_statebuffer_space(struct brw_context
*brw
, int size
)
1048 if (brw
->batch
.state_used
+ size
>= STATE_SZ
)
1049 intel_batchbuffer_flush(brw
);
1053 * Allocates a block of space in the batchbuffer for indirect state.
1056 brw_state_batch(struct brw_context
*brw
,
1059 uint32_t *out_offset
)
1061 struct intel_batchbuffer
*batch
= &brw
->batch
;
1063 assert(size
< batch
->bo
->size
);
1065 uint32_t offset
= ALIGN(batch
->state_used
, alignment
);
1067 if (offset
+ size
>= STATE_SZ
&& !batch
->no_wrap
) {
1068 intel_batchbuffer_flush(brw
);
1069 offset
= ALIGN(batch
->state_used
, alignment
);
1070 } else if (offset
+ size
>= batch
->state_bo
->size
) {
1071 const unsigned new_size
=
1072 MIN2(batch
->state_bo
->size
+ batch
->state_bo
->size
/ 2,
1074 grow_buffer(brw
, &batch
->state_bo
, &batch
->state_map
,
1075 &batch
->state_cpu_map
, batch
->state_used
, new_size
);
1076 assert(offset
+ size
< batch
->state_bo
->size
);
1079 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
1080 _mesa_hash_table_insert(batch
->state_batch_sizes
,
1081 (void *) (uintptr_t) offset
,
1082 (void *) (uintptr_t) size
);
1085 batch
->state_used
= offset
+ size
;
1087 *out_offset
= offset
;
1088 return batch
->state_map
+ (offset
>> 2);
1092 intel_batchbuffer_data(struct brw_context
*brw
,
1093 const void *data
, GLuint bytes
, enum brw_gpu_ring ring
)
1095 assert((bytes
& 3) == 0);
1096 intel_batchbuffer_require_space(brw
, bytes
, ring
);
1097 memcpy(brw
->batch
.map_next
, data
, bytes
);
1098 brw
->batch
.map_next
+= bytes
>> 2;
1102 load_sized_register_mem(struct brw_context
*brw
,
1108 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1111 /* MI_LOAD_REGISTER_MEM only exists on Gen7+. */
1112 assert(devinfo
->gen
>= 7);
1114 if (devinfo
->gen
>= 8) {
1115 BEGIN_BATCH(4 * size
);
1116 for (i
= 0; i
< size
; i
++) {
1117 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (4 - 2));
1118 OUT_BATCH(reg
+ i
* 4);
1119 OUT_RELOC64(bo
, 0, offset
+ i
* 4);
1123 BEGIN_BATCH(3 * size
);
1124 for (i
= 0; i
< size
; i
++) {
1125 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (3 - 2));
1126 OUT_BATCH(reg
+ i
* 4);
1127 OUT_RELOC(bo
, 0, offset
+ i
* 4);
1134 brw_load_register_mem(struct brw_context
*brw
,
1139 load_sized_register_mem(brw
, reg
, bo
, offset
, 1);
1143 brw_load_register_mem64(struct brw_context
*brw
,
1148 load_sized_register_mem(brw
, reg
, bo
, offset
, 2);
1152 * Write an arbitrary 32-bit register to a buffer via MI_STORE_REGISTER_MEM.
1155 brw_store_register_mem32(struct brw_context
*brw
,
1156 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
)
1158 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1160 assert(devinfo
->gen
>= 6);
1162 if (devinfo
->gen
>= 8) {
1164 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
1166 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
1170 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
1172 OUT_RELOC(bo
, RELOC_WRITE
| RELOC_NEEDS_GGTT
, offset
);
1178 * Write an arbitrary 64-bit register to a buffer via MI_STORE_REGISTER_MEM.
1181 brw_store_register_mem64(struct brw_context
*brw
,
1182 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
)
1184 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1186 assert(devinfo
->gen
>= 6);
1188 /* MI_STORE_REGISTER_MEM only stores a single 32-bit value, so to
1189 * read a full 64-bit register, we need to do two of them.
1191 if (devinfo
->gen
>= 8) {
1193 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
1195 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
1196 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
1197 OUT_BATCH(reg
+ sizeof(uint32_t));
1198 OUT_RELOC64(bo
, RELOC_WRITE
, offset
+ sizeof(uint32_t));
1202 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
1204 OUT_RELOC(bo
, RELOC_WRITE
| RELOC_NEEDS_GGTT
, offset
);
1205 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
1206 OUT_BATCH(reg
+ sizeof(uint32_t));
1207 OUT_RELOC(bo
, RELOC_WRITE
| RELOC_NEEDS_GGTT
, offset
+ sizeof(uint32_t));
1213 * Write a 32-bit register using immediate data.
1216 brw_load_register_imm32(struct brw_context
*brw
, uint32_t reg
, uint32_t imm
)
1218 assert(brw
->screen
->devinfo
.gen
>= 6);
1221 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
1228 * Write a 64-bit register using immediate data.
1231 brw_load_register_imm64(struct brw_context
*brw
, uint32_t reg
, uint64_t imm
)
1233 assert(brw
->screen
->devinfo
.gen
>= 6);
1236 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (5 - 2));
1238 OUT_BATCH(imm
& 0xffffffff);
1240 OUT_BATCH(imm
>> 32);
1245 * Copies a 32-bit register.
1248 brw_load_register_reg(struct brw_context
*brw
, uint32_t src
, uint32_t dest
)
1250 assert(brw
->screen
->devinfo
.gen
>= 8 || brw
->screen
->devinfo
.is_haswell
);
1253 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1260 * Copies a 64-bit register.
1263 brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
, uint32_t dest
)
1265 assert(brw
->screen
->devinfo
.gen
>= 8 || brw
->screen
->devinfo
.is_haswell
);
1268 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1271 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1272 OUT_BATCH(src
+ sizeof(uint32_t));
1273 OUT_BATCH(dest
+ sizeof(uint32_t));
1278 * Write 32-bits of immediate data to a GPU memory buffer.
1281 brw_store_data_imm32(struct brw_context
*brw
, struct brw_bo
*bo
,
1282 uint32_t offset
, uint32_t imm
)
1284 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1286 assert(devinfo
->gen
>= 6);
1289 OUT_BATCH(MI_STORE_DATA_IMM
| (4 - 2));
1290 if (devinfo
->gen
>= 8)
1291 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
1293 OUT_BATCH(0); /* MBZ */
1294 OUT_RELOC(bo
, RELOC_WRITE
, offset
);
1301 * Write 64-bits of immediate data to a GPU memory buffer.
1304 brw_store_data_imm64(struct brw_context
*brw
, struct brw_bo
*bo
,
1305 uint32_t offset
, uint64_t imm
)
1307 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1309 assert(devinfo
->gen
>= 6);
1312 OUT_BATCH(MI_STORE_DATA_IMM
| (5 - 2));
1313 if (devinfo
->gen
>= 8)
1314 OUT_RELOC64(bo
, 0, offset
);
1316 OUT_BATCH(0); /* MBZ */
1317 OUT_RELOC(bo
, RELOC_WRITE
, offset
);
1319 OUT_BATCH(imm
& 0xffffffffu
);
1320 OUT_BATCH(imm
>> 32);