2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "intel_batchbuffer.h"
27 #include "intel_buffer_objects.h"
28 #include "brw_bufmgr.h"
29 #include "intel_buffers.h"
30 #include "intel_fbo.h"
31 #include "brw_context.h"
32 #include "brw_defines.h"
33 #include "brw_state.h"
34 #include "common/gen_decoder.h"
36 #include "util/hash_table.h"
41 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
44 intel_batchbuffer_reset(struct intel_batchbuffer
*batch
,
45 struct brw_bufmgr
*bufmgr
,
49 uint_key_compare(const void *a
, const void *b
)
55 uint_key_hash(const void *key
)
57 return (uintptr_t) key
;
61 intel_batchbuffer_init(struct intel_batchbuffer
*batch
,
62 struct brw_bufmgr
*bufmgr
,
65 intel_batchbuffer_reset(batch
, bufmgr
, has_llc
);
68 batch
->cpu_map
= malloc(BATCH_SZ
);
69 batch
->map
= batch
->cpu_map
;
70 batch
->map_next
= batch
->cpu_map
;
73 batch
->reloc_count
= 0;
74 batch
->reloc_array_size
= 250;
75 batch
->relocs
= malloc(batch
->reloc_array_size
*
76 sizeof(struct drm_i915_gem_relocation_entry
));
77 batch
->exec_count
= 0;
78 batch
->exec_array_size
= 100;
80 malloc(batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
81 batch
->validation_list
=
82 malloc(batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
84 if (INTEL_DEBUG
& DEBUG_BATCH
) {
85 batch
->state_batch_sizes
=
86 _mesa_hash_table_create(NULL
, uint_key_hash
, uint_key_compare
);
90 #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
93 add_exec_bo(struct intel_batchbuffer
*batch
, struct brw_bo
*bo
)
95 if (bo
!= batch
->bo
) {
96 unsigned index
= READ_ONCE(bo
->index
);
98 if (index
< batch
->exec_count
&& batch
->exec_bos
[index
] == bo
)
101 /* May have been shared between multiple active batches */
102 for (index
= 0; index
< batch
->exec_count
; index
++) {
103 if (batch
->exec_bos
[index
] == bo
)
107 brw_bo_reference(bo
);
110 if (batch
->exec_count
== batch
->exec_array_size
) {
111 batch
->exec_array_size
*= 2;
113 realloc(batch
->exec_bos
,
114 batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
115 batch
->validation_list
=
116 realloc(batch
->validation_list
,
117 batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
120 struct drm_i915_gem_exec_object2
*validation_entry
=
121 &batch
->validation_list
[batch
->exec_count
];
122 validation_entry
->handle
= bo
->gem_handle
;
123 if (bo
== batch
->bo
) {
124 validation_entry
->relocation_count
= batch
->reloc_count
;
125 validation_entry
->relocs_ptr
= (uintptr_t) batch
->relocs
;
127 validation_entry
->relocation_count
= 0;
128 validation_entry
->relocs_ptr
= 0;
130 validation_entry
->alignment
= bo
->align
;
131 validation_entry
->offset
= bo
->offset64
;
132 validation_entry
->flags
= bo
->kflags
;
133 validation_entry
->rsvd1
= 0;
134 validation_entry
->rsvd2
= 0;
136 bo
->index
= batch
->exec_count
;
137 batch
->exec_bos
[batch
->exec_count
] = bo
;
138 batch
->aperture_space
+= bo
->size
;
140 return batch
->exec_count
++;
144 intel_batchbuffer_reset(struct intel_batchbuffer
*batch
,
145 struct brw_bufmgr
*bufmgr
,
148 if (batch
->last_bo
!= NULL
) {
149 brw_bo_unreference(batch
->last_bo
);
150 batch
->last_bo
= NULL
;
152 batch
->last_bo
= batch
->bo
;
154 batch
->bo
= brw_bo_alloc(bufmgr
, "batchbuffer", BATCH_SZ
, 4096);
156 batch
->map
= brw_bo_map(NULL
, batch
->bo
, MAP_READ
| MAP_WRITE
);
158 batch
->map_next
= batch
->map
;
160 batch
->reserved_space
= BATCH_RESERVED
;
161 batch
->state_batch_offset
= batch
->bo
->size
;
162 batch
->needs_sol_reset
= false;
163 batch
->state_base_address_emitted
= false;
165 /* We don't know what ring the new batch will be sent to until we see the
166 * first BEGIN_BATCH or BEGIN_BATCH_BLT. Mark it as unknown.
168 batch
->ring
= UNKNOWN_RING
;
170 if (batch
->state_batch_sizes
)
171 _mesa_hash_table_clear(batch
->state_batch_sizes
, NULL
);
175 intel_batchbuffer_reset_and_clear_render_cache(struct brw_context
*brw
)
177 intel_batchbuffer_reset(&brw
->batch
, brw
->bufmgr
, brw
->has_llc
);
178 brw_render_cache_set_clear(brw
);
182 intel_batchbuffer_save_state(struct brw_context
*brw
)
184 brw
->batch
.saved
.map_next
= brw
->batch
.map_next
;
185 brw
->batch
.saved
.reloc_count
= brw
->batch
.reloc_count
;
186 brw
->batch
.saved
.exec_count
= brw
->batch
.exec_count
;
190 intel_batchbuffer_reset_to_saved(struct brw_context
*brw
)
192 for (int i
= brw
->batch
.saved
.exec_count
;
193 i
< brw
->batch
.exec_count
; i
++) {
194 if (brw
->batch
.exec_bos
[i
] != brw
->batch
.bo
) {
195 brw_bo_unreference(brw
->batch
.exec_bos
[i
]);
198 brw
->batch
.reloc_count
= brw
->batch
.saved
.reloc_count
;
199 brw
->batch
.exec_count
= brw
->batch
.saved
.exec_count
;
201 brw
->batch
.map_next
= brw
->batch
.saved
.map_next
;
202 if (USED_BATCH(brw
->batch
) == 0)
203 brw
->batch
.ring
= UNKNOWN_RING
;
207 intel_batchbuffer_free(struct intel_batchbuffer
*batch
)
209 free(batch
->cpu_map
);
211 for (int i
= 0; i
< batch
->exec_count
; i
++) {
212 if (batch
->exec_bos
[i
] != batch
->bo
) {
213 brw_bo_unreference(batch
->exec_bos
[i
]);
217 free(batch
->exec_bos
);
218 free(batch
->validation_list
);
220 brw_bo_unreference(batch
->last_bo
);
221 brw_bo_unreference(batch
->bo
);
222 if (batch
->state_batch_sizes
)
223 _mesa_hash_table_destroy(batch
->state_batch_sizes
, NULL
);
227 intel_batchbuffer_require_space(struct brw_context
*brw
, GLuint sz
,
228 enum brw_gpu_ring ring
)
230 /* If we're switching rings, implicitly flush the batch. */
231 if (unlikely(ring
!= brw
->batch
.ring
) && brw
->batch
.ring
!= UNKNOWN_RING
&&
233 intel_batchbuffer_flush(brw
);
237 assert(sz
< BATCH_SZ
- BATCH_RESERVED
);
239 if (intel_batchbuffer_space(&brw
->batch
) < sz
)
240 intel_batchbuffer_flush(brw
);
242 /* The intel_batchbuffer_flush() calls above might have changed
243 * brw->batch.ring to UNKNOWN_RING, so we need to set it here at the end.
245 brw
->batch
.ring
= ring
;
250 #define BLUE_HEADER CSI "0;44m"
251 #define NORMAL CSI "0m"
255 decode_struct(struct brw_context
*brw
, struct gen_spec
*spec
,
256 const char *struct_name
, uint32_t *data
,
257 uint32_t gtt_offset
, uint32_t offset
, bool color
)
259 struct gen_group
*group
= gen_spec_find_struct(spec
, struct_name
);
263 fprintf(stderr
, "%s\n", struct_name
);
264 gen_print_group(stderr
, group
, gtt_offset
+ offset
,
265 &data
[offset
/ 4], color
);
269 decode_structs(struct brw_context
*brw
, struct gen_spec
*spec
,
270 const char *struct_name
,
271 uint32_t *data
, uint32_t gtt_offset
, uint32_t offset
,
272 int struct_size
, bool color
)
274 struct gen_group
*group
= gen_spec_find_struct(spec
, struct_name
);
278 int entries
= brw_state_batch_size(brw
, offset
) / struct_size
;
279 for (int i
= 0; i
< entries
; i
++) {
280 fprintf(stderr
, "%s %d\n", struct_name
, i
);
281 gen_print_group(stderr
, group
, gtt_offset
+ offset
,
282 &data
[(offset
+ i
* struct_size
) / 4], color
);
287 do_batch_dump(struct brw_context
*brw
)
289 struct intel_batchbuffer
*batch
= &brw
->batch
;
290 struct gen_spec
*spec
= gen_spec_load(&brw
->screen
->devinfo
);
292 if (batch
->ring
!= RENDER_RING
)
295 void *map
= brw_bo_map(brw
, batch
->bo
, MAP_READ
);
298 "WARNING: failed to map batchbuffer, "
299 "dumping uploaded data instead.\n");
302 uint32_t *data
= map
? map
: batch
->map
;
303 uint32_t *end
= data
+ USED_BATCH(*batch
);
304 uint32_t gtt_offset
= map
? batch
->bo
->offset64
: 0;
307 bool color
= INTEL_DEBUG
& DEBUG_COLOR
;
308 const char *header_color
= color
? BLUE_HEADER
: "";
309 const char *reset_color
= color
? NORMAL
: "";
311 for (uint32_t *p
= data
; p
< end
; p
+= length
) {
312 struct gen_group
*inst
= gen_spec_find_instruction(spec
, p
);
313 length
= gen_group_get_length(inst
, p
);
314 assert(inst
== NULL
|| length
> 0);
315 length
= MAX2(1, length
);
317 fprintf(stderr
, "unknown instruction %08x\n", p
[0]);
321 uint64_t offset
= gtt_offset
+ 4 * (p
- data
);
323 fprintf(stderr
, "%s0x%08"PRIx64
": 0x%08x: %-80s%s\n", header_color
,
324 offset
, p
[0], gen_group_get_name(inst
), reset_color
);
326 gen_print_group(stderr
, inst
, offset
, p
, color
);
328 switch (gen_group_get_opcode(inst
) >> 16) {
329 case _3DSTATE_PIPELINED_POINTERS
:
330 /* Note: these Gen4-5 pointers are full relocations rather than
331 * offsets from the start of the batch. So we need to subtract
332 * gtt_offset (the start of the batch) to obtain an offset we
333 * can add to the map and get at the data.
335 decode_struct(brw
, spec
, "VS_STATE", data
, gtt_offset
,
336 (p
[1] & ~0x1fu
) - gtt_offset
, color
);
338 decode_struct(brw
, spec
, "GS_STATE", data
, gtt_offset
,
339 (p
[2] & ~0x1fu
) - gtt_offset
, color
);
342 decode_struct(brw
, spec
, "CLIP_STATE", data
, gtt_offset
,
343 (p
[3] & ~0x1fu
) - gtt_offset
, color
);
345 decode_struct(brw
, spec
, "SF_STATE", data
, gtt_offset
,
346 (p
[4] & ~0x1fu
) - gtt_offset
, color
);
347 decode_struct(brw
, spec
, "WM_STATE", data
, gtt_offset
,
348 (p
[5] & ~0x1fu
) - gtt_offset
, color
);
349 decode_struct(brw
, spec
, "COLOR_CALC_STATE", data
, gtt_offset
,
350 (p
[6] & ~0x3fu
) - gtt_offset
, color
);
352 case _3DSTATE_BINDING_TABLE_POINTERS_VS
:
353 case _3DSTATE_BINDING_TABLE_POINTERS_HS
:
354 case _3DSTATE_BINDING_TABLE_POINTERS_DS
:
355 case _3DSTATE_BINDING_TABLE_POINTERS_GS
:
356 case _3DSTATE_BINDING_TABLE_POINTERS_PS
: {
357 struct gen_group
*group
=
358 gen_spec_find_struct(spec
, "RENDER_SURFACE_STATE");
362 uint32_t bt_offset
= p
[1] & ~0x1fu
;
363 int bt_entries
= brw_state_batch_size(brw
, bt_offset
) / 4;
364 uint32_t *bt_pointers
= &data
[bt_offset
/ 4];
365 for (int i
= 0; i
< bt_entries
; i
++) {
366 fprintf(stderr
, "SURFACE_STATE - BTI = %d\n", i
);
367 gen_print_group(stderr
, group
, gtt_offset
+ bt_pointers
[i
],
368 &data
[bt_pointers
[i
] / 4], color
);
372 case _3DSTATE_SAMPLER_STATE_POINTERS_VS
:
373 case _3DSTATE_SAMPLER_STATE_POINTERS_HS
:
374 case _3DSTATE_SAMPLER_STATE_POINTERS_DS
:
375 case _3DSTATE_SAMPLER_STATE_POINTERS_GS
:
376 case _3DSTATE_SAMPLER_STATE_POINTERS_PS
:
377 decode_structs(brw
, spec
, "SAMPLER_STATE", data
,
378 gtt_offset
, p
[1] & ~0x1fu
, 4 * 4, color
);
380 case _3DSTATE_VIEWPORT_STATE_POINTERS
:
381 decode_structs(brw
, spec
, "CLIP_VIEWPORT", data
,
382 gtt_offset
, p
[1] & ~0x3fu
, 4 * 4, color
);
383 decode_structs(brw
, spec
, "SF_VIEWPORT", data
,
384 gtt_offset
, p
[1] & ~0x3fu
, 8 * 4, color
);
385 decode_structs(brw
, spec
, "CC_VIEWPORT", data
,
386 gtt_offset
, p
[3] & ~0x3fu
, 2 * 4, color
);
388 case _3DSTATE_VIEWPORT_STATE_POINTERS_CC
:
389 decode_structs(brw
, spec
, "CC_VIEWPORT", data
,
390 gtt_offset
, p
[1] & ~0x3fu
, 2 * 4, color
);
392 case _3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL
:
393 decode_structs(brw
, spec
, "SF_CLIP_VIEWPORT", data
,
394 gtt_offset
, p
[1] & ~0x3fu
, 16 * 4, color
);
396 case _3DSTATE_SCISSOR_STATE_POINTERS
:
397 decode_structs(brw
, spec
, "SCISSOR_RECT", data
,
398 gtt_offset
, p
[1] & ~0x1fu
, 2 * 4, color
);
400 case _3DSTATE_BLEND_STATE_POINTERS
:
401 /* TODO: handle Gen8+ extra dword at the beginning */
402 decode_structs(brw
, spec
, "BLEND_STATE", data
,
403 gtt_offset
, p
[1] & ~0x3fu
, 8 * 4, color
);
405 case _3DSTATE_CC_STATE_POINTERS
:
407 decode_struct(brw
, spec
, "COLOR_CALC_STATE", data
,
408 gtt_offset
, p
[1] & ~0x3fu
, color
);
409 } else if (brw
->gen
== 6) {
410 decode_structs(brw
, spec
, "BLEND_STATE", data
,
411 gtt_offset
, p
[1] & ~0x3fu
, 2 * 4, color
);
412 decode_struct(brw
, spec
, "DEPTH_STENCIL_STATE", data
,
413 gtt_offset
, p
[2] & ~0x3fu
, color
);
414 decode_struct(brw
, spec
, "COLOR_CALC_STATE", data
,
415 gtt_offset
, p
[3] & ~0x3fu
, color
);
418 case _3DSTATE_DEPTH_STENCIL_STATE_POINTERS
:
419 decode_struct(brw
, spec
, "DEPTH_STENCIL_STATE", data
,
420 gtt_offset
, p
[1] & ~0x3fu
, color
);
426 brw_bo_unmap(batch
->bo
);
430 static void do_batch_dump(struct brw_context
*brw
) { }
434 * Called when starting a new batch buffer.
437 brw_new_batch(struct brw_context
*brw
)
439 /* Unreference any BOs held by the previous batch, and reset counts. */
440 for (int i
= 0; i
< brw
->batch
.exec_count
; i
++) {
441 if (brw
->batch
.exec_bos
[i
] != brw
->batch
.bo
) {
442 brw_bo_unreference(brw
->batch
.exec_bos
[i
]);
444 brw
->batch
.exec_bos
[i
] = NULL
;
446 brw
->batch
.reloc_count
= 0;
447 brw
->batch
.exec_count
= 0;
448 brw
->batch
.aperture_space
= BATCH_SZ
;
450 /* Create a new batchbuffer and reset the associated state: */
451 intel_batchbuffer_reset_and_clear_render_cache(brw
);
453 /* If the kernel supports hardware contexts, then most hardware state is
454 * preserved between batches; we only need to re-emit state that is required
455 * to be in every batch. Otherwise we need to re-emit all the state that
456 * would otherwise be stored in the context (which for all intents and
457 * purposes means everything).
459 if (brw
->hw_ctx
== 0)
460 brw
->ctx
.NewDriverState
|= BRW_NEW_CONTEXT
;
462 brw
->ctx
.NewDriverState
|= BRW_NEW_BATCH
;
464 brw
->ib
.index_size
= -1;
466 /* We need to periodically reap the shader time results, because rollover
467 * happens every few seconds. We also want to see results every once in a
468 * while, because many programs won't cleanly destroy our context, so the
469 * end-of-run printout may not happen.
471 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
472 brw_collect_and_report_shader_time(brw
);
476 * Called from intel_batchbuffer_flush before emitting MI_BATCHBUFFER_END and
479 * This function can emit state (say, to preserve registers that aren't saved
480 * between batches). All of this state MUST fit in the reserved space at the
481 * end of the batchbuffer. If you add more GPU state, increase the reserved
482 * space by updating the BATCH_RESERVED macro.
485 brw_finish_batch(struct brw_context
*brw
)
487 /* Capture the closing pipeline statistics register values necessary to
488 * support query objects (in the non-hardware context world).
490 brw_emit_query_end(brw
);
492 if (brw
->batch
.ring
== RENDER_RING
) {
493 /* Work around L3 state leaks into contexts set MI_RESTORE_INHIBIT which
494 * assume that the L3 cache is configured according to the hardware
498 gen7_restore_default_l3_config(brw
);
500 if (brw
->is_haswell
) {
501 /* From the Haswell PRM, Volume 2b, Command Reference: Instructions,
502 * 3DSTATE_CC_STATE_POINTERS > "Note":
504 * "SW must program 3DSTATE_CC_STATE_POINTERS command at the end of every
505 * 3D batch buffer followed by a PIPE_CONTROL with RC flush and CS stall."
507 * From the example in the docs, it seems to expect a regular pipe control
508 * flush here as well. We may have done it already, but meh.
510 * See also WaAvoidRCZCounterRollover.
512 brw_emit_mi_flush(brw
);
514 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (2 - 2));
515 OUT_BATCH(brw
->cc
.state_offset
| 1);
517 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
|
518 PIPE_CONTROL_CS_STALL
);
524 throttle(struct brw_context
*brw
)
526 /* Wait for the swapbuffers before the one we just emitted, so we
527 * don't get too many swaps outstanding for apps that are GPU-heavy
530 * We're using intelDRI2Flush (called from the loader before
531 * swapbuffer) and glFlush (for front buffer rendering) as the
532 * indicator that a frame is done and then throttle when we get
533 * here as we prepare to render the next frame. At this point for
534 * round trips for swap/copy and getting new buffers are done and
535 * we'll spend less time waiting on the GPU.
537 * Unfortunately, we don't have a handle to the batch containing
538 * the swap, and getting our hands on that doesn't seem worth it,
539 * so we just use the first batch we emitted after the last swap.
541 if (brw
->need_swap_throttle
&& brw
->throttle_batch
[0]) {
542 if (brw
->throttle_batch
[1]) {
543 if (!brw
->disable_throttling
) {
544 /* Pass NULL rather than brw so we avoid perf_debug warnings;
545 * stalling is common and expected here...
547 brw_bo_wait_rendering(brw
->throttle_batch
[1]);
549 brw_bo_unreference(brw
->throttle_batch
[1]);
551 brw
->throttle_batch
[1] = brw
->throttle_batch
[0];
552 brw
->throttle_batch
[0] = NULL
;
553 brw
->need_swap_throttle
= false;
554 /* Throttling here is more precise than the throttle ioctl, so skip it */
555 brw
->need_flush_throttle
= false;
558 if (brw
->need_flush_throttle
) {
559 __DRIscreen
*dri_screen
= brw
->screen
->driScrnPriv
;
560 drmCommandNone(dri_screen
->fd
, DRM_I915_GEM_THROTTLE
);
561 brw
->need_flush_throttle
= false;
567 struct intel_batchbuffer
*batch
,
574 struct drm_i915_gem_execbuffer2 execbuf
= {
575 .buffers_ptr
= (uintptr_t) batch
->validation_list
,
576 .buffer_count
= batch
->exec_count
,
577 .batch_start_offset
= 0,
580 .rsvd1
= ctx_id
, /* rsvd1 is actually the context ID */
583 unsigned long cmd
= DRM_IOCTL_I915_GEM_EXECBUFFER2
;
585 if (in_fence
!= -1) {
586 execbuf
.rsvd2
= in_fence
;
587 execbuf
.flags
|= I915_EXEC_FENCE_IN
;
590 if (out_fence
!= NULL
) {
591 cmd
= DRM_IOCTL_I915_GEM_EXECBUFFER2_WR
;
593 execbuf
.flags
|= I915_EXEC_FENCE_OUT
;
596 int ret
= drmIoctl(fd
, cmd
, &execbuf
);
600 for (int i
= 0; i
< batch
->exec_count
; i
++) {
601 struct brw_bo
*bo
= batch
->exec_bos
[i
];
606 /* Update brw_bo::offset64 */
607 if (batch
->validation_list
[i
].offset
!= bo
->offset64
) {
608 DBG("BO %d migrated: 0x%" PRIx64
" -> 0x%llx\n",
609 bo
->gem_handle
, bo
->offset64
, batch
->validation_list
[i
].offset
);
610 bo
->offset64
= batch
->validation_list
[i
].offset
;
614 if (ret
== 0 && out_fence
!= NULL
)
615 *out_fence
= execbuf
.rsvd2
>> 32;
621 do_flush_locked(struct brw_context
*brw
, int in_fence_fd
, int *out_fence_fd
)
623 __DRIscreen
*dri_screen
= brw
->screen
->driScrnPriv
;
624 struct intel_batchbuffer
*batch
= &brw
->batch
;
628 brw_bo_unmap(batch
->bo
);
630 ret
= brw_bo_subdata(batch
->bo
, 0, 4 * USED_BATCH(*batch
), batch
->map
);
631 if (ret
== 0 && batch
->state_batch_offset
!= batch
->bo
->size
) {
632 ret
= brw_bo_subdata(batch
->bo
,
633 batch
->state_batch_offset
,
634 batch
->bo
->size
- batch
->state_batch_offset
,
635 (char *)batch
->map
+ batch
->state_batch_offset
);
639 if (!brw
->screen
->no_hw
) {
640 /* The requirement for using I915_EXEC_NO_RELOC are:
642 * The addresses written in the objects must match the corresponding
643 * reloc.presumed_offset which in turn must match the corresponding
646 * Any render targets written to in the batch must be flagged with
649 * To avoid stalling, execobject.offset should match the current
650 * address of that object within the active context.
652 int flags
= I915_EXEC_NO_RELOC
;
654 if (brw
->gen
>= 6 && batch
->ring
== BLT_RING
) {
655 flags
|= I915_EXEC_BLT
;
657 flags
|= I915_EXEC_RENDER
;
659 if (batch
->needs_sol_reset
)
660 flags
|= I915_EXEC_GEN7_SOL_RESET
;
663 uint32_t hw_ctx
= batch
->ring
== RENDER_RING
? brw
->hw_ctx
: 0;
665 /* Add the batch itself to the end of the validation list */
666 add_exec_bo(batch
, batch
->bo
);
668 ret
= execbuffer(dri_screen
->fd
, batch
, hw_ctx
,
669 4 * USED_BATCH(*batch
),
670 in_fence_fd
, out_fence_fd
, flags
);
676 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
))
679 if (brw
->ctx
.Const
.ResetStrategy
== GL_LOSE_CONTEXT_ON_RESET_ARB
)
680 brw_check_for_reset(brw
);
683 fprintf(stderr
, "intel_do_flush_locked failed: %s\n", strerror(-ret
));
691 * The in_fence_fd is ignored if -1. Otherwise this function takes ownership
694 * The out_fence_fd is ignored if NULL. Otherwise, the caller takes ownership
695 * of the returned fd.
698 _intel_batchbuffer_flush_fence(struct brw_context
*brw
,
699 int in_fence_fd
, int *out_fence_fd
,
700 const char *file
, int line
)
704 if (USED_BATCH(brw
->batch
) == 0)
707 if (brw
->throttle_batch
[0] == NULL
) {
708 brw
->throttle_batch
[0] = brw
->batch
.bo
;
709 brw_bo_reference(brw
->throttle_batch
[0]);
712 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
713 int bytes_for_commands
= 4 * USED_BATCH(brw
->batch
);
714 int bytes_for_state
= brw
->batch
.bo
->size
- brw
->batch
.state_batch_offset
;
715 int total_bytes
= bytes_for_commands
+ bytes_for_state
;
716 fprintf(stderr
, "%s:%d: Batchbuffer flush with %4db (pkt) + "
717 "%4db (state) = %4db (%0.1f%%)\n", file
, line
,
718 bytes_for_commands
, bytes_for_state
,
720 100.0f
* total_bytes
/ BATCH_SZ
);
723 brw
->batch
.reserved_space
= 0;
725 brw_finish_batch(brw
);
727 /* Mark the end of the buffer. */
728 intel_batchbuffer_emit_dword(&brw
->batch
, MI_BATCH_BUFFER_END
);
729 if (USED_BATCH(brw
->batch
) & 1) {
730 /* Round batchbuffer usage to 2 DWORDs. */
731 intel_batchbuffer_emit_dword(&brw
->batch
, MI_NOOP
);
734 intel_upload_finish(brw
);
736 /* Check that we didn't just wrap our batchbuffer at a bad time. */
737 assert(!brw
->no_batch_wrap
);
739 ret
= do_flush_locked(brw
, in_fence_fd
, out_fence_fd
);
741 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
742 fprintf(stderr
, "waiting for idle\n");
743 brw_bo_wait_rendering(brw
->batch
.bo
);
746 /* Start a new batch buffer. */
753 brw_batch_has_aperture_space(struct brw_context
*brw
, unsigned extra_space
)
755 return brw
->batch
.aperture_space
+ extra_space
<=
756 brw
->screen
->aperture_threshold
;
760 brw_batch_references(struct intel_batchbuffer
*batch
, struct brw_bo
*bo
)
762 unsigned index
= READ_ONCE(bo
->index
);
763 if (index
< batch
->exec_count
&& batch
->exec_bos
[index
] == bo
)
766 for (int i
= 0; i
< batch
->exec_count
; i
++) {
767 if (batch
->exec_bos
[i
] == bo
)
773 /* This is the only way buffers get added to the validate list.
776 brw_emit_reloc(struct intel_batchbuffer
*batch
, uint32_t batch_offset
,
777 struct brw_bo
*target
, uint32_t target_offset
,
778 uint32_t read_domains
, uint32_t write_domain
)
780 assert(target
!= NULL
);
782 if (batch
->reloc_count
== batch
->reloc_array_size
) {
783 batch
->reloc_array_size
*= 2;
784 batch
->relocs
= realloc(batch
->relocs
,
785 batch
->reloc_array_size
*
786 sizeof(struct drm_i915_gem_relocation_entry
));
790 assert(batch_offset
<= BATCH_SZ
- sizeof(uint32_t));
791 assert(_mesa_bitcount(write_domain
) <= 1);
794 if (target
!= batch
->bo
) {
795 unsigned int index
= add_exec_bo(batch
, target
);
796 struct drm_i915_gem_exec_object2
*entry
= &batch
->validation_list
[index
];
799 entry
->flags
|= EXEC_OBJECT_WRITE
;
801 /* PIPECONTROL needs a w/a on gen6 */
802 if (write_domain
== I915_GEM_DOMAIN_INSTRUCTION
) {
803 struct brw_context
*brw
= container_of(batch
, brw
, batch
);
805 entry
->flags
|= EXEC_OBJECT_NEEDS_GTT
;
809 offset64
= entry
->offset
;
811 offset64
= target
->offset64
;
814 batch
->relocs
[batch
->reloc_count
++] =
815 (struct drm_i915_gem_relocation_entry
) {
816 .offset
= batch_offset
,
817 .delta
= target_offset
,
818 .target_handle
= target
->gem_handle
,
819 .presumed_offset
= offset64
,
822 /* Using the old buffer offset, write in what the right data would be, in
823 * case the buffer doesn't move and we can short-circuit the relocation
824 * processing in the kernel
826 return offset64
+ target_offset
;
830 intel_batchbuffer_data(struct brw_context
*brw
,
831 const void *data
, GLuint bytes
, enum brw_gpu_ring ring
)
833 assert((bytes
& 3) == 0);
834 intel_batchbuffer_require_space(brw
, bytes
, ring
);
835 memcpy(brw
->batch
.map_next
, data
, bytes
);
836 brw
->batch
.map_next
+= bytes
>> 2;
840 load_sized_register_mem(struct brw_context
*brw
,
843 uint32_t read_domains
, uint32_t write_domain
,
849 /* MI_LOAD_REGISTER_MEM only exists on Gen7+. */
850 assert(brw
->gen
>= 7);
853 BEGIN_BATCH(4 * size
);
854 for (i
= 0; i
< size
; i
++) {
855 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (4 - 2));
856 OUT_BATCH(reg
+ i
* 4);
857 OUT_RELOC64(bo
, read_domains
, write_domain
, offset
+ i
* 4);
861 BEGIN_BATCH(3 * size
);
862 for (i
= 0; i
< size
; i
++) {
863 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (3 - 2));
864 OUT_BATCH(reg
+ i
* 4);
865 OUT_RELOC(bo
, read_domains
, write_domain
, offset
+ i
* 4);
872 brw_load_register_mem(struct brw_context
*brw
,
875 uint32_t read_domains
, uint32_t write_domain
,
878 load_sized_register_mem(brw
, reg
, bo
, read_domains
, write_domain
, offset
, 1);
882 brw_load_register_mem64(struct brw_context
*brw
,
885 uint32_t read_domains
, uint32_t write_domain
,
888 load_sized_register_mem(brw
, reg
, bo
, read_domains
, write_domain
, offset
, 2);
892 * Write an arbitrary 32-bit register to a buffer via MI_STORE_REGISTER_MEM.
895 brw_store_register_mem32(struct brw_context
*brw
,
896 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
)
898 assert(brw
->gen
>= 6);
902 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
904 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
909 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
911 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
918 * Write an arbitrary 64-bit register to a buffer via MI_STORE_REGISTER_MEM.
921 brw_store_register_mem64(struct brw_context
*brw
,
922 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
)
924 assert(brw
->gen
>= 6);
926 /* MI_STORE_REGISTER_MEM only stores a single 32-bit value, so to
927 * read a full 64-bit register, we need to do two of them.
931 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
933 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
935 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
936 OUT_BATCH(reg
+ sizeof(uint32_t));
937 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
938 offset
+ sizeof(uint32_t));
942 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
944 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
946 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
947 OUT_BATCH(reg
+ sizeof(uint32_t));
948 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
949 offset
+ sizeof(uint32_t));
955 * Write a 32-bit register using immediate data.
958 brw_load_register_imm32(struct brw_context
*brw
, uint32_t reg
, uint32_t imm
)
960 assert(brw
->gen
>= 6);
963 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
970 * Write a 64-bit register using immediate data.
973 brw_load_register_imm64(struct brw_context
*brw
, uint32_t reg
, uint64_t imm
)
975 assert(brw
->gen
>= 6);
978 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (5 - 2));
980 OUT_BATCH(imm
& 0xffffffff);
982 OUT_BATCH(imm
>> 32);
987 * Copies a 32-bit register.
990 brw_load_register_reg(struct brw_context
*brw
, uint32_t src
, uint32_t dest
)
992 assert(brw
->gen
>= 8 || brw
->is_haswell
);
995 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1002 * Copies a 64-bit register.
1005 brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
, uint32_t dest
)
1007 assert(brw
->gen
>= 8 || brw
->is_haswell
);
1010 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1013 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1014 OUT_BATCH(src
+ sizeof(uint32_t));
1015 OUT_BATCH(dest
+ sizeof(uint32_t));
1020 * Write 32-bits of immediate data to a GPU memory buffer.
1023 brw_store_data_imm32(struct brw_context
*brw
, struct brw_bo
*bo
,
1024 uint32_t offset
, uint32_t imm
)
1026 assert(brw
->gen
>= 6);
1029 OUT_BATCH(MI_STORE_DATA_IMM
| (4 - 2));
1031 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
1034 OUT_BATCH(0); /* MBZ */
1035 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
1043 * Write 64-bits of immediate data to a GPU memory buffer.
1046 brw_store_data_imm64(struct brw_context
*brw
, struct brw_bo
*bo
,
1047 uint32_t offset
, uint64_t imm
)
1049 assert(brw
->gen
>= 6);
1052 OUT_BATCH(MI_STORE_DATA_IMM
| (5 - 2));
1054 OUT_RELOC64(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
1057 OUT_BATCH(0); /* MBZ */
1058 OUT_RELOC(bo
, I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
,
1061 OUT_BATCH(imm
& 0xffffffffu
);
1062 OUT_BATCH(imm
>> 32);