2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "intel_batchbuffer.h"
27 #include "intel_buffer_objects.h"
28 #include "brw_bufmgr.h"
29 #include "intel_buffers.h"
30 #include "intel_fbo.h"
31 #include "brw_context.h"
32 #include "brw_defines.h"
33 #include "brw_state.h"
34 #include "common/gen_decoder.h"
36 #include "util/hash_table.h"
41 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
44 * Target sizes of the batch and state buffers. We create the initial
45 * buffers at these sizes, and flush when they're nearly full. If we
46 * underestimate how close we are to the end, and suddenly need more space
47 * in the middle of a draw, we can grow the buffers, and finish the draw.
48 * At that point, we'll be over our target size, so the next operation
49 * should flush. Each time we flush the batch, we recreate both buffers
50 * at the original target size, so it doesn't grow without bound.
52 #define BATCH_SZ (20 * 1024)
53 #define STATE_SZ (16 * 1024)
56 intel_batchbuffer_reset(struct brw_context
*brw
);
59 dump_validation_list(struct intel_batchbuffer
*batch
)
61 fprintf(stderr
, "Validation list (length %d):\n", batch
->exec_count
);
63 for (int i
= 0; i
< batch
->exec_count
; i
++) {
64 uint64_t flags
= batch
->validation_list
[i
].flags
;
65 assert(batch
->validation_list
[i
].handle
==
66 batch
->exec_bos
[i
]->gem_handle
);
67 fprintf(stderr
, "[%2d]: %2d %-14s %p %s%-7s @ 0x%016llx%s (%"PRIu64
"B)\n",
69 batch
->validation_list
[i
].handle
,
70 batch
->exec_bos
[i
]->name
,
72 (flags
& EXEC_OBJECT_SUPPORTS_48B_ADDRESS
) ? "(48b" : "(32b",
73 (flags
& EXEC_OBJECT_WRITE
) ? " write)" : ")",
74 batch
->validation_list
[i
].offset
,
75 (flags
& EXEC_OBJECT_PINNED
) ? " (pinned)" : "",
76 batch
->exec_bos
[i
]->size
);
80 static struct gen_batch_decode_bo
81 decode_get_bo(void *v_brw
, uint64_t address
)
83 struct brw_context
*brw
= v_brw
;
84 struct intel_batchbuffer
*batch
= &brw
->batch
;
86 for (int i
= 0; i
< batch
->exec_count
; i
++) {
87 struct brw_bo
*bo
= batch
->exec_bos
[i
];
88 /* The decoder zeroes out the top 16 bits, so we need to as well */
89 uint64_t bo_address
= bo
->gtt_offset
& (~0ull >> 16);
91 if (address
>= bo_address
&& address
< bo_address
+ bo
->size
) {
92 return (struct gen_batch_decode_bo
) {
95 .map
= brw_bo_map(brw
, bo
, MAP_READ
) + (address
- bo_address
),
100 return (struct gen_batch_decode_bo
) { };
104 decode_get_state_size(void *v_brw
, uint32_t offset_from_dsba
)
106 struct brw_context
*brw
= v_brw
;
107 struct intel_batchbuffer
*batch
= &brw
->batch
;
108 struct hash_entry
*entry
=
109 _mesa_hash_table_search(batch
->state_batch_sizes
,
110 (void *) (uintptr_t) offset_from_dsba
);
111 return entry
? (uintptr_t) entry
->data
: 0;
115 uint_key_compare(const void *a
, const void *b
)
121 uint_key_hash(const void *key
)
123 return (uintptr_t) key
;
127 init_reloc_list(struct brw_reloc_list
*rlist
, int count
)
129 rlist
->reloc_count
= 0;
130 rlist
->reloc_array_size
= count
;
131 rlist
->relocs
= malloc(rlist
->reloc_array_size
*
132 sizeof(struct drm_i915_gem_relocation_entry
));
136 intel_batchbuffer_init(struct brw_context
*brw
)
138 struct intel_screen
*screen
= brw
->screen
;
139 struct intel_batchbuffer
*batch
= &brw
->batch
;
140 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
142 batch
->use_shadow_copy
= !devinfo
->has_llc
;
144 init_reloc_list(&batch
->batch_relocs
, 250);
145 init_reloc_list(&batch
->state_relocs
, 250);
147 batch
->batch
.map
= NULL
;
148 batch
->state
.map
= NULL
;
149 batch
->exec_count
= 0;
150 batch
->exec_array_size
= 100;
152 malloc(batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
153 batch
->validation_list
=
154 malloc(batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
156 if (INTEL_DEBUG
& DEBUG_BATCH
) {
157 batch
->state_batch_sizes
=
158 _mesa_hash_table_create(NULL
, uint_key_hash
, uint_key_compare
);
160 const unsigned decode_flags
=
161 GEN_BATCH_DECODE_FULL
|
162 ((INTEL_DEBUG
& DEBUG_COLOR
) ? GEN_BATCH_DECODE_IN_COLOR
: 0) |
163 GEN_BATCH_DECODE_OFFSETS
|
164 GEN_BATCH_DECODE_FLOATS
;
166 gen_batch_decode_ctx_init(&batch
->decoder
, devinfo
, stderr
,
167 decode_flags
, NULL
, decode_get_bo
,
168 decode_get_state_size
, brw
);
169 batch
->decoder
.max_vbo_decoded_lines
= 100;
172 batch
->use_batch_first
=
173 screen
->kernel_features
& KERNEL_ALLOWS_EXEC_BATCH_FIRST
;
175 /* PIPE_CONTROL needs a w/a but only on gen6 */
176 batch
->valid_reloc_flags
= EXEC_OBJECT_WRITE
;
177 if (devinfo
->gen
== 6)
178 batch
->valid_reloc_flags
|= EXEC_OBJECT_NEEDS_GTT
;
180 intel_batchbuffer_reset(brw
);
183 #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
186 add_exec_bo(struct intel_batchbuffer
*batch
, struct brw_bo
*bo
)
188 unsigned index
= READ_ONCE(bo
->index
);
190 if (index
< batch
->exec_count
&& batch
->exec_bos
[index
] == bo
)
193 /* May have been shared between multiple active batches */
194 for (index
= 0; index
< batch
->exec_count
; index
++) {
195 if (batch
->exec_bos
[index
] == bo
)
199 brw_bo_reference(bo
);
201 if (batch
->exec_count
== batch
->exec_array_size
) {
202 batch
->exec_array_size
*= 2;
204 realloc(batch
->exec_bos
,
205 batch
->exec_array_size
* sizeof(batch
->exec_bos
[0]));
206 batch
->validation_list
=
207 realloc(batch
->validation_list
,
208 batch
->exec_array_size
* sizeof(batch
->validation_list
[0]));
211 batch
->validation_list
[batch
->exec_count
] =
212 (struct drm_i915_gem_exec_object2
) {
213 .handle
= bo
->gem_handle
,
214 .offset
= bo
->gtt_offset
,
218 bo
->index
= batch
->exec_count
;
219 batch
->exec_bos
[batch
->exec_count
] = bo
;
220 batch
->aperture_space
+= bo
->size
;
222 return batch
->exec_count
++;
226 recreate_growing_buffer(struct brw_context
*brw
,
227 struct brw_growing_bo
*grow
,
228 const char *name
, unsigned size
,
229 enum brw_memory_zone memzone
)
231 struct intel_screen
*screen
= brw
->screen
;
232 struct intel_batchbuffer
*batch
= &brw
->batch
;
233 struct brw_bufmgr
*bufmgr
= screen
->bufmgr
;
235 grow
->bo
= brw_bo_alloc(bufmgr
, name
, size
, memzone
);
236 grow
->bo
->kflags
|= can_do_exec_capture(screen
) ? EXEC_OBJECT_CAPTURE
: 0;
237 grow
->partial_bo
= NULL
;
238 grow
->partial_bo_map
= NULL
;
239 grow
->partial_bytes
= 0;
240 grow
->memzone
= memzone
;
242 if (batch
->use_shadow_copy
)
243 grow
->map
= realloc(grow
->map
, grow
->bo
->size
);
245 grow
->map
= brw_bo_map(brw
, grow
->bo
, MAP_READ
| MAP_WRITE
);
249 intel_batchbuffer_reset(struct brw_context
*brw
)
251 struct intel_batchbuffer
*batch
= &brw
->batch
;
253 if (batch
->last_bo
!= NULL
) {
254 brw_bo_unreference(batch
->last_bo
);
255 batch
->last_bo
= NULL
;
257 batch
->last_bo
= batch
->batch
.bo
;
259 recreate_growing_buffer(brw
, &batch
->batch
, "batchbuffer", BATCH_SZ
,
261 batch
->map_next
= batch
->batch
.map
;
263 recreate_growing_buffer(brw
, &batch
->state
, "statebuffer", STATE_SZ
,
264 BRW_MEMZONE_DYNAMIC
);
266 /* Avoid making 0 a valid state offset - otherwise the decoder will try
267 * and decode data when we use offset 0 as a null pointer.
269 batch
->state_used
= 1;
271 add_exec_bo(batch
, batch
->batch
.bo
);
272 assert(batch
->batch
.bo
->index
== 0);
274 batch
->needs_sol_reset
= false;
275 batch
->state_base_address_emitted
= false;
277 /* We don't know what ring the new batch will be sent to until we see the
278 * first BEGIN_BATCH or BEGIN_BATCH_BLT. Mark it as unknown.
280 batch
->ring
= UNKNOWN_RING
;
282 if (batch
->state_batch_sizes
)
283 _mesa_hash_table_clear(batch
->state_batch_sizes
, NULL
);
287 intel_batchbuffer_reset_and_clear_render_cache(struct brw_context
*brw
)
289 intel_batchbuffer_reset(brw
);
290 brw_cache_sets_clear(brw
);
294 intel_batchbuffer_save_state(struct brw_context
*brw
)
296 brw
->batch
.saved
.map_next
= brw
->batch
.map_next
;
297 brw
->batch
.saved
.batch_reloc_count
= brw
->batch
.batch_relocs
.reloc_count
;
298 brw
->batch
.saved
.state_reloc_count
= brw
->batch
.state_relocs
.reloc_count
;
299 brw
->batch
.saved
.exec_count
= brw
->batch
.exec_count
;
303 intel_batchbuffer_reset_to_saved(struct brw_context
*brw
)
305 for (int i
= brw
->batch
.saved
.exec_count
;
306 i
< brw
->batch
.exec_count
; i
++) {
307 brw_bo_unreference(brw
->batch
.exec_bos
[i
]);
309 brw
->batch
.batch_relocs
.reloc_count
= brw
->batch
.saved
.batch_reloc_count
;
310 brw
->batch
.state_relocs
.reloc_count
= brw
->batch
.saved
.state_reloc_count
;
311 brw
->batch
.exec_count
= brw
->batch
.saved
.exec_count
;
313 brw
->batch
.map_next
= brw
->batch
.saved
.map_next
;
314 if (USED_BATCH(brw
->batch
) == 0)
315 brw
->batch
.ring
= UNKNOWN_RING
;
319 intel_batchbuffer_free(struct intel_batchbuffer
*batch
)
321 if (batch
->use_shadow_copy
) {
322 free(batch
->batch
.map
);
323 free(batch
->state
.map
);
326 for (int i
= 0; i
< batch
->exec_count
; i
++) {
327 brw_bo_unreference(batch
->exec_bos
[i
]);
329 free(batch
->batch_relocs
.relocs
);
330 free(batch
->state_relocs
.relocs
);
331 free(batch
->exec_bos
);
332 free(batch
->validation_list
);
334 brw_bo_unreference(batch
->last_bo
);
335 brw_bo_unreference(batch
->batch
.bo
);
336 brw_bo_unreference(batch
->state
.bo
);
337 if (batch
->state_batch_sizes
) {
338 _mesa_hash_table_destroy(batch
->state_batch_sizes
, NULL
);
339 gen_batch_decode_ctx_finish(&batch
->decoder
);
344 * Finish copying the old batch/state buffer's contents to the new one
345 * after we tried to "grow" the buffer in an earlier operation.
348 finish_growing_bos(struct brw_growing_bo
*grow
)
350 struct brw_bo
*old_bo
= grow
->partial_bo
;
354 memcpy(grow
->map
, grow
->partial_bo_map
, grow
->partial_bytes
);
356 grow
->partial_bo
= NULL
;
357 grow
->partial_bo_map
= NULL
;
358 grow
->partial_bytes
= 0;
360 brw_bo_unreference(old_bo
);
364 replace_bo_in_reloc_list(struct brw_reloc_list
*rlist
,
365 uint32_t old_handle
, uint32_t new_handle
)
367 for (int i
= 0; i
< rlist
->reloc_count
; i
++) {
368 if (rlist
->relocs
[i
].target_handle
== old_handle
)
369 rlist
->relocs
[i
].target_handle
= new_handle
;
374 * Grow either the batch or state buffer to a new larger size.
376 * We can't actually grow buffers, so we allocate a new one, copy over
377 * the existing contents, and update our lists to refer to the new one.
379 * Note that this is only temporary - each new batch recreates the buffers
380 * at their original target size (BATCH_SZ or STATE_SZ).
383 grow_buffer(struct brw_context
*brw
,
384 struct brw_growing_bo
*grow
,
385 unsigned existing_bytes
,
388 struct intel_batchbuffer
*batch
= &brw
->batch
;
389 struct brw_bufmgr
*bufmgr
= brw
->bufmgr
;
390 struct brw_bo
*bo
= grow
->bo
;
392 perf_debug("Growing %s - ran out of space\n", bo
->name
);
394 if (grow
->partial_bo
) {
395 /* We've already grown once, and now we need to do it again.
396 * Finish our last grow operation so we can start a new one.
397 * This should basically never happen.
399 perf_debug("Had to grow multiple times");
400 finish_growing_bos(grow
);
403 struct brw_bo
*new_bo
=
404 brw_bo_alloc(bufmgr
, bo
->name
, new_size
, grow
->memzone
);
406 /* Copy existing data to the new larger buffer */
407 grow
->partial_bo_map
= grow
->map
;
409 if (batch
->use_shadow_copy
) {
410 /* We can't safely use realloc, as it may move the existing buffer,
411 * breaking existing pointers the caller may still be using. Just
412 * malloc a new copy and memcpy it like the normal BO path.
414 * Use bo->size rather than new_size because the bufmgr may have
415 * rounded up the size, and we want the shadow size to match.
417 grow
->map
= malloc(new_bo
->size
);
419 grow
->map
= brw_bo_map(brw
, new_bo
, MAP_READ
| MAP_WRITE
);
422 /* Try to put the new BO at the same GTT offset as the old BO (which
423 * we're throwing away, so it doesn't need to be there).
425 * This guarantees that our relocations continue to work: values we've
426 * already written into the buffer, values we're going to write into the
427 * buffer, and the validation/relocation lists all will match.
429 * Also preserve kflags for EXEC_OBJECT_CAPTURE.
431 new_bo
->gtt_offset
= bo
->gtt_offset
;
432 new_bo
->index
= bo
->index
;
433 new_bo
->kflags
= bo
->kflags
;
435 /* Batch/state buffers are per-context, and if we've run out of space,
436 * we must have actually used them before, so...they will be in the list.
438 assert(bo
->index
< batch
->exec_count
);
439 assert(batch
->exec_bos
[bo
->index
] == bo
);
441 /* Update the validation list to use the new BO. */
442 batch
->validation_list
[bo
->index
].handle
= new_bo
->gem_handle
;
444 if (!batch
->use_batch_first
) {
445 /* We're not using I915_EXEC_HANDLE_LUT, which means we need to go
446 * update the relocation list entries to point at the new BO as well.
447 * (With newer kernels, the "handle" is an offset into the validation
448 * list, which remains unchanged, so we can skip this.)
450 replace_bo_in_reloc_list(&batch
->batch_relocs
,
451 bo
->gem_handle
, new_bo
->gem_handle
);
452 replace_bo_in_reloc_list(&batch
->state_relocs
,
453 bo
->gem_handle
, new_bo
->gem_handle
);
456 /* Exchange the two BOs...without breaking pointers to the old BO.
458 * Consider this scenario:
460 * 1. Somebody calls brw_state_batch() to get a region of memory, and
461 * and then creates a brw_address pointing to brw->batch.state.bo.
462 * 2. They then call brw_state_batch() a second time, which happens to
463 * grow and replace the state buffer. They then try to emit a
464 * relocation to their first section of memory.
466 * If we replace the brw->batch.state.bo pointer at step 2, we would
467 * break the address created in step 1. They'd have a pointer to the
468 * old destroyed BO. Emitting a relocation would add this dead BO to
469 * the validation list...causing /both/ statebuffers to be in the list,
470 * and all kinds of disasters.
472 * This is not a contrived case - BLORP vertex data upload hits this.
474 * There are worse scenarios too. Fences for GL sync objects reference
475 * brw->batch.batch.bo. If we replaced the batch pointer when growing,
476 * we'd need to chase down every fence and update it to point to the
477 * new BO. Otherwise, it would refer to a "batch" that never actually
478 * gets submitted, and would fail to trigger.
480 * To work around both of these issues, we transmutate the buffers in
481 * place, making the existing struct brw_bo represent the new buffer,
482 * and "new_bo" represent the old BO. This is highly unusual, but it
483 * seems like a necessary evil.
485 * We also defer the memcpy of the existing batch's contents. Callers
486 * may make multiple brw_state_batch calls, and retain pointers to the
487 * old BO's map. We'll perform the memcpy in finish_growing_bo() when
488 * we finally submit the batch, at which point we've finished uploading
489 * state, and nobody should have any old references anymore.
491 * To do that, we keep a reference to the old BO in grow->partial_bo,
492 * and store the number of bytes to copy in grow->partial_bytes. We
493 * can monkey with the refcounts directly without atomics because these
494 * are per-context BOs and they can only be touched by this thread.
496 assert(new_bo
->refcount
== 1);
497 new_bo
->refcount
= bo
->refcount
;
501 memcpy(&tmp
, bo
, sizeof(struct brw_bo
));
502 memcpy(bo
, new_bo
, sizeof(struct brw_bo
));
503 memcpy(new_bo
, &tmp
, sizeof(struct brw_bo
));
505 grow
->partial_bo
= new_bo
; /* the one reference of the OLD bo */
506 grow
->partial_bytes
= existing_bytes
;
510 intel_batchbuffer_require_space(struct brw_context
*brw
, GLuint sz
,
511 enum brw_gpu_ring ring
)
513 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
514 struct intel_batchbuffer
*batch
= &brw
->batch
;
516 /* If we're switching rings, implicitly flush the batch. */
517 if (unlikely(ring
!= brw
->batch
.ring
) && brw
->batch
.ring
!= UNKNOWN_RING
&&
519 intel_batchbuffer_flush(brw
);
522 const unsigned batch_used
= USED_BATCH(*batch
) * 4;
523 if (batch_used
+ sz
>= BATCH_SZ
&& !batch
->no_wrap
) {
524 intel_batchbuffer_flush(brw
);
525 } else if (batch_used
+ sz
>= batch
->batch
.bo
->size
) {
526 const unsigned new_size
=
527 MIN2(batch
->batch
.bo
->size
+ batch
->batch
.bo
->size
/ 2,
529 grow_buffer(brw
, &batch
->batch
, batch_used
, new_size
);
530 batch
->map_next
= (void *) batch
->batch
.map
+ batch_used
;
531 assert(batch_used
+ sz
< batch
->batch
.bo
->size
);
534 /* The intel_batchbuffer_flush() calls above might have changed
535 * brw->batch.ring to UNKNOWN_RING, so we need to set it here at the end.
537 brw
->batch
.ring
= ring
;
541 * Called when starting a new batch buffer.
544 brw_new_batch(struct brw_context
*brw
)
546 /* Unreference any BOs held by the previous batch, and reset counts. */
547 for (int i
= 0; i
< brw
->batch
.exec_count
; i
++) {
548 brw_bo_unreference(brw
->batch
.exec_bos
[i
]);
549 brw
->batch
.exec_bos
[i
] = NULL
;
551 brw
->batch
.batch_relocs
.reloc_count
= 0;
552 brw
->batch
.state_relocs
.reloc_count
= 0;
553 brw
->batch
.exec_count
= 0;
554 brw
->batch
.aperture_space
= 0;
556 brw_bo_unreference(brw
->batch
.state
.bo
);
558 /* Create a new batchbuffer and reset the associated state: */
559 intel_batchbuffer_reset_and_clear_render_cache(brw
);
561 /* If the kernel supports hardware contexts, then most hardware state is
562 * preserved between batches; we only need to re-emit state that is required
563 * to be in every batch. Otherwise we need to re-emit all the state that
564 * would otherwise be stored in the context (which for all intents and
565 * purposes means everything).
567 if (brw
->hw_ctx
== 0) {
568 brw
->ctx
.NewDriverState
|= BRW_NEW_CONTEXT
;
569 brw_upload_invariant_state(brw
);
572 brw
->ctx
.NewDriverState
|= BRW_NEW_BATCH
;
574 brw
->ib
.index_size
= -1;
576 /* We need to periodically reap the shader time results, because rollover
577 * happens every few seconds. We also want to see results every once in a
578 * while, because many programs won't cleanly destroy our context, so the
579 * end-of-run printout may not happen.
581 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
582 brw_collect_and_report_shader_time(brw
);
586 * Called from intel_batchbuffer_flush before emitting MI_BATCHBUFFER_END and
589 * This function can emit state (say, to preserve registers that aren't saved
593 brw_finish_batch(struct brw_context
*brw
)
595 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
597 brw
->batch
.no_wrap
= true;
599 /* Capture the closing pipeline statistics register values necessary to
600 * support query objects (in the non-hardware context world).
602 brw_emit_query_end(brw
);
604 if (brw
->batch
.ring
== RENDER_RING
) {
605 /* Work around L3 state leaks into contexts set MI_RESTORE_INHIBIT which
606 * assume that the L3 cache is configured according to the hardware
607 * defaults. On Kernel 4.16+, we no longer need to do this.
609 if (devinfo
->gen
>= 7 &&
610 !(brw
->screen
->kernel_features
& KERNEL_ALLOWS_CONTEXT_ISOLATION
))
611 gen7_restore_default_l3_config(brw
);
613 if (devinfo
->is_haswell
) {
614 /* From the Haswell PRM, Volume 2b, Command Reference: Instructions,
615 * 3DSTATE_CC_STATE_POINTERS > "Note":
617 * "SW must program 3DSTATE_CC_STATE_POINTERS command at the end of every
618 * 3D batch buffer followed by a PIPE_CONTROL with RC flush and CS stall."
620 * From the example in the docs, it seems to expect a regular pipe control
621 * flush here as well. We may have done it already, but meh.
623 * See also WaAvoidRCZCounterRollover.
625 brw_emit_mi_flush(brw
);
627 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS
<< 16 | (2 - 2));
628 OUT_BATCH(brw
->cc
.state_offset
| 1);
630 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_RENDER_TARGET_FLUSH
|
631 PIPE_CONTROL_CS_STALL
);
634 /* Do not restore push constant packets during context restore. */
635 if (devinfo
->gen
>= 7)
636 gen10_emit_isp_disable(brw
);
639 /* Emit MI_BATCH_BUFFER_END to finish our batch. Note that execbuf2
640 * requires our batch size to be QWord aligned, so we pad it out if
641 * necessary by emitting an extra MI_NOOP after the end.
643 intel_batchbuffer_require_space(brw
, 8, brw
->batch
.ring
);
644 *brw
->batch
.map_next
++ = MI_BATCH_BUFFER_END
;
645 if (USED_BATCH(brw
->batch
) & 1) {
646 *brw
->batch
.map_next
++ = MI_NOOP
;
649 brw
->batch
.no_wrap
= false;
653 throttle(struct brw_context
*brw
)
655 /* Wait for the swapbuffers before the one we just emitted, so we
656 * don't get too many swaps outstanding for apps that are GPU-heavy
659 * We're using intelDRI2Flush (called from the loader before
660 * swapbuffer) and glFlush (for front buffer rendering) as the
661 * indicator that a frame is done and then throttle when we get
662 * here as we prepare to render the next frame. At this point for
663 * round trips for swap/copy and getting new buffers are done and
664 * we'll spend less time waiting on the GPU.
666 * Unfortunately, we don't have a handle to the batch containing
667 * the swap, and getting our hands on that doesn't seem worth it,
668 * so we just use the first batch we emitted after the last swap.
670 if (brw
->need_swap_throttle
&& brw
->throttle_batch
[0]) {
671 if (brw
->throttle_batch
[1]) {
672 if (!brw
->disable_throttling
) {
673 brw_bo_wait_rendering(brw
->throttle_batch
[1]);
675 brw_bo_unreference(brw
->throttle_batch
[1]);
677 brw
->throttle_batch
[1] = brw
->throttle_batch
[0];
678 brw
->throttle_batch
[0] = NULL
;
679 brw
->need_swap_throttle
= false;
680 /* Throttling here is more precise than the throttle ioctl, so skip it */
681 brw
->need_flush_throttle
= false;
684 if (brw
->need_flush_throttle
) {
685 __DRIscreen
*dri_screen
= brw
->screen
->driScrnPriv
;
686 drmCommandNone(dri_screen
->fd
, DRM_I915_GEM_THROTTLE
);
687 brw
->need_flush_throttle
= false;
693 struct intel_batchbuffer
*batch
,
700 struct drm_i915_gem_execbuffer2 execbuf
= {
701 .buffers_ptr
= (uintptr_t) batch
->validation_list
,
702 .buffer_count
= batch
->exec_count
,
703 .batch_start_offset
= 0,
706 .rsvd1
= ctx_id
, /* rsvd1 is actually the context ID */
709 unsigned long cmd
= DRM_IOCTL_I915_GEM_EXECBUFFER2
;
711 if (in_fence
!= -1) {
712 execbuf
.rsvd2
= in_fence
;
713 execbuf
.flags
|= I915_EXEC_FENCE_IN
;
716 if (out_fence
!= NULL
) {
717 cmd
= DRM_IOCTL_I915_GEM_EXECBUFFER2_WR
;
719 execbuf
.flags
|= I915_EXEC_FENCE_OUT
;
722 int ret
= drmIoctl(fd
, cmd
, &execbuf
);
726 for (int i
= 0; i
< batch
->exec_count
; i
++) {
727 struct brw_bo
*bo
= batch
->exec_bos
[i
];
732 /* Update brw_bo::gtt_offset */
733 if (batch
->validation_list
[i
].offset
!= bo
->gtt_offset
) {
734 DBG("BO %d migrated: 0x%" PRIx64
" -> 0x%llx\n",
735 bo
->gem_handle
, bo
->gtt_offset
,
736 batch
->validation_list
[i
].offset
);
737 bo
->gtt_offset
= batch
->validation_list
[i
].offset
;
741 if (ret
== 0 && out_fence
!= NULL
)
742 *out_fence
= execbuf
.rsvd2
>> 32;
748 submit_batch(struct brw_context
*brw
, int in_fence_fd
, int *out_fence_fd
)
750 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
751 __DRIscreen
*dri_screen
= brw
->screen
->driScrnPriv
;
752 struct intel_batchbuffer
*batch
= &brw
->batch
;
755 if (batch
->use_shadow_copy
) {
756 void *bo_map
= brw_bo_map(brw
, batch
->batch
.bo
, MAP_WRITE
);
757 memcpy(bo_map
, batch
->batch
.map
, 4 * USED_BATCH(*batch
));
759 bo_map
= brw_bo_map(brw
, batch
->state
.bo
, MAP_WRITE
);
760 memcpy(bo_map
, batch
->state
.map
, batch
->state_used
);
763 brw_bo_unmap(batch
->batch
.bo
);
764 brw_bo_unmap(batch
->state
.bo
);
766 if (!brw
->screen
->no_hw
) {
767 /* The requirement for using I915_EXEC_NO_RELOC are:
769 * The addresses written in the objects must match the corresponding
770 * reloc.gtt_offset which in turn must match the corresponding
773 * Any render targets written to in the batch must be flagged with
776 * To avoid stalling, execobject.offset should match the current
777 * address of that object within the active context.
779 assert(devinfo
->gen
< 6 || batch
->ring
== RENDER_RING
);
780 int flags
= I915_EXEC_NO_RELOC
| I915_EXEC_RENDER
;
782 if (batch
->needs_sol_reset
)
783 flags
|= I915_EXEC_GEN7_SOL_RESET
;
785 /* Set statebuffer relocations */
786 const unsigned state_index
= batch
->state
.bo
->index
;
787 if (state_index
< batch
->exec_count
&&
788 batch
->exec_bos
[state_index
] == batch
->state
.bo
) {
789 struct drm_i915_gem_exec_object2
*entry
=
790 &batch
->validation_list
[state_index
];
791 assert(entry
->handle
== batch
->state
.bo
->gem_handle
);
792 entry
->relocation_count
= batch
->state_relocs
.reloc_count
;
793 entry
->relocs_ptr
= (uintptr_t) batch
->state_relocs
.relocs
;
796 /* Set batchbuffer relocations */
797 struct drm_i915_gem_exec_object2
*entry
= &batch
->validation_list
[0];
798 assert(entry
->handle
== batch
->batch
.bo
->gem_handle
);
799 entry
->relocation_count
= batch
->batch_relocs
.reloc_count
;
800 entry
->relocs_ptr
= (uintptr_t) batch
->batch_relocs
.relocs
;
802 if (batch
->use_batch_first
) {
803 flags
|= I915_EXEC_BATCH_FIRST
| I915_EXEC_HANDLE_LUT
;
805 /* Move the batch to the end of the validation list */
806 struct drm_i915_gem_exec_object2 tmp
;
807 const unsigned index
= batch
->exec_count
- 1;
810 *entry
= batch
->validation_list
[index
];
811 batch
->validation_list
[index
] = tmp
;
814 ret
= execbuffer(dri_screen
->fd
, batch
, brw
->hw_ctx
,
815 4 * USED_BATCH(*batch
),
816 in_fence_fd
, out_fence_fd
, flags
);
821 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
822 gen_print_batch(&batch
->decoder
, batch
->batch
.map
,
823 4 * USED_BATCH(*batch
),
824 batch
->batch
.bo
->gtt_offset
);
827 if (brw
->ctx
.Const
.ResetStrategy
== GL_LOSE_CONTEXT_ON_RESET_ARB
)
828 brw_check_for_reset(brw
);
831 fprintf(stderr
, "i965: Failed to submit batchbuffer: %s\n",
840 * The in_fence_fd is ignored if -1. Otherwise this function takes ownership
843 * The out_fence_fd is ignored if NULL. Otherwise, the caller takes ownership
844 * of the returned fd.
847 _intel_batchbuffer_flush_fence(struct brw_context
*brw
,
848 int in_fence_fd
, int *out_fence_fd
,
849 const char *file
, int line
)
853 if (USED_BATCH(brw
->batch
) == 0)
856 /* Check that we didn't just wrap our batchbuffer at a bad time. */
857 assert(!brw
->batch
.no_wrap
);
859 brw_finish_batch(brw
);
860 brw_upload_finish(&brw
->upload
);
862 finish_growing_bos(&brw
->batch
.batch
);
863 finish_growing_bos(&brw
->batch
.state
);
865 if (brw
->throttle_batch
[0] == NULL
) {
866 brw
->throttle_batch
[0] = brw
->batch
.batch
.bo
;
867 brw_bo_reference(brw
->throttle_batch
[0]);
870 if (unlikely(INTEL_DEBUG
& (DEBUG_BATCH
| DEBUG_SUBMIT
))) {
871 int bytes_for_commands
= 4 * USED_BATCH(brw
->batch
);
872 int bytes_for_state
= brw
->batch
.state_used
;
873 fprintf(stderr
, "%19s:%-3d: Batchbuffer flush with %5db (%0.1f%%) (pkt),"
874 " %5db (%0.1f%%) (state), %4d BOs (%0.1fMb aperture),"
875 " %4d batch relocs, %4d state relocs\n", file
, line
,
876 bytes_for_commands
, 100.0f
* bytes_for_commands
/ BATCH_SZ
,
877 bytes_for_state
, 100.0f
* bytes_for_state
/ STATE_SZ
,
878 brw
->batch
.exec_count
,
879 (float) brw
->batch
.aperture_space
/ (1024 * 1024),
880 brw
->batch
.batch_relocs
.reloc_count
,
881 brw
->batch
.state_relocs
.reloc_count
);
883 dump_validation_list(&brw
->batch
);
886 ret
= submit_batch(brw
, in_fence_fd
, out_fence_fd
);
888 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
889 fprintf(stderr
, "waiting for idle\n");
890 brw_bo_wait_rendering(brw
->batch
.batch
.bo
);
893 /* Start a new batch buffer. */
900 brw_batch_has_aperture_space(struct brw_context
*brw
, unsigned extra_space
)
902 return brw
->batch
.aperture_space
+ extra_space
<=
903 brw
->screen
->aperture_threshold
;
907 brw_batch_references(struct intel_batchbuffer
*batch
, struct brw_bo
*bo
)
909 unsigned index
= READ_ONCE(bo
->index
);
910 if (index
< batch
->exec_count
&& batch
->exec_bos
[index
] == bo
)
913 for (int i
= 0; i
< batch
->exec_count
; i
++) {
914 if (batch
->exec_bos
[i
] == bo
)
920 /* This is the only way buffers get added to the validate list.
923 emit_reloc(struct intel_batchbuffer
*batch
,
924 struct brw_reloc_list
*rlist
, uint32_t offset
,
925 struct brw_bo
*target
, int32_t target_offset
,
926 unsigned int reloc_flags
)
928 assert(target
!= NULL
);
930 if (rlist
->reloc_count
== rlist
->reloc_array_size
) {
931 rlist
->reloc_array_size
*= 2;
932 rlist
->relocs
= realloc(rlist
->relocs
,
933 rlist
->reloc_array_size
*
934 sizeof(struct drm_i915_gem_relocation_entry
));
937 unsigned int index
= add_exec_bo(batch
, target
);
938 struct drm_i915_gem_exec_object2
*entry
= &batch
->validation_list
[index
];
940 if (reloc_flags
& RELOC_32BIT
) {
941 /* Restrict this buffer to the low 32 bits of the address space.
943 * Altering the validation list flags restricts it for this batch,
944 * but we also alter the BO's kflags to restrict it permanently
945 * (until the BO is destroyed and put back in the cache). Buffers
946 * may stay bound across batches, and we want keep it constrained.
948 target
->kflags
&= ~EXEC_OBJECT_SUPPORTS_48B_ADDRESS
;
949 entry
->flags
&= ~EXEC_OBJECT_SUPPORTS_48B_ADDRESS
;
951 /* RELOC_32BIT is not an EXEC_OBJECT_* flag, so get rid of it. */
952 reloc_flags
&= ~RELOC_32BIT
;
956 entry
->flags
|= reloc_flags
& batch
->valid_reloc_flags
;
958 rlist
->relocs
[rlist
->reloc_count
++] =
959 (struct drm_i915_gem_relocation_entry
) {
961 .delta
= target_offset
,
962 .target_handle
= batch
->use_batch_first
? index
: target
->gem_handle
,
963 .presumed_offset
= entry
->offset
,
966 /* Using the old buffer offset, write in what the right data would be, in
967 * case the buffer doesn't move and we can short-circuit the relocation
968 * processing in the kernel
970 return entry
->offset
+ target_offset
;
974 brw_batch_reloc(struct intel_batchbuffer
*batch
, uint32_t batch_offset
,
975 struct brw_bo
*target
, uint32_t target_offset
,
976 unsigned int reloc_flags
)
978 assert(batch_offset
<= batch
->batch
.bo
->size
- sizeof(uint32_t));
980 return emit_reloc(batch
, &batch
->batch_relocs
, batch_offset
,
981 target
, target_offset
, reloc_flags
);
985 brw_state_reloc(struct intel_batchbuffer
*batch
, uint32_t state_offset
,
986 struct brw_bo
*target
, uint32_t target_offset
,
987 unsigned int reloc_flags
)
989 assert(state_offset
<= batch
->state
.bo
->size
- sizeof(uint32_t));
991 return emit_reloc(batch
, &batch
->state_relocs
, state_offset
,
992 target
, target_offset
, reloc_flags
);
996 * Reserve some space in the statebuffer, or flush.
998 * This is used to estimate when we're near the end of the batch,
999 * so we can flush early.
1002 brw_require_statebuffer_space(struct brw_context
*brw
, int size
)
1004 if (brw
->batch
.state_used
+ size
>= STATE_SZ
)
1005 intel_batchbuffer_flush(brw
);
1009 * Allocates a block of space in the batchbuffer for indirect state.
1012 brw_state_batch(struct brw_context
*brw
,
1015 uint32_t *out_offset
)
1017 struct intel_batchbuffer
*batch
= &brw
->batch
;
1019 assert(size
< batch
->state
.bo
->size
);
1021 uint32_t offset
= ALIGN(batch
->state_used
, alignment
);
1023 if (offset
+ size
>= STATE_SZ
&& !batch
->no_wrap
) {
1024 intel_batchbuffer_flush(brw
);
1025 offset
= ALIGN(batch
->state_used
, alignment
);
1026 } else if (offset
+ size
>= batch
->state
.bo
->size
) {
1027 const unsigned new_size
=
1028 MIN2(batch
->state
.bo
->size
+ batch
->state
.bo
->size
/ 2,
1030 grow_buffer(brw
, &batch
->state
, batch
->state_used
, new_size
);
1031 assert(offset
+ size
< batch
->state
.bo
->size
);
1034 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
1035 _mesa_hash_table_insert(batch
->state_batch_sizes
,
1036 (void *) (uintptr_t) offset
,
1037 (void *) (uintptr_t) size
);
1040 batch
->state_used
= offset
+ size
;
1042 *out_offset
= offset
;
1043 return batch
->state
.map
+ (offset
>> 2);
1047 intel_batchbuffer_data(struct brw_context
*brw
,
1048 const void *data
, GLuint bytes
, enum brw_gpu_ring ring
)
1050 assert((bytes
& 3) == 0);
1051 intel_batchbuffer_require_space(brw
, bytes
, ring
);
1052 memcpy(brw
->batch
.map_next
, data
, bytes
);
1053 brw
->batch
.map_next
+= bytes
>> 2;
1057 load_sized_register_mem(struct brw_context
*brw
,
1063 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1066 /* MI_LOAD_REGISTER_MEM only exists on Gen7+. */
1067 assert(devinfo
->gen
>= 7);
1069 if (devinfo
->gen
>= 8) {
1070 BEGIN_BATCH(4 * size
);
1071 for (i
= 0; i
< size
; i
++) {
1072 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (4 - 2));
1073 OUT_BATCH(reg
+ i
* 4);
1074 OUT_RELOC64(bo
, 0, offset
+ i
* 4);
1078 BEGIN_BATCH(3 * size
);
1079 for (i
= 0; i
< size
; i
++) {
1080 OUT_BATCH(GEN7_MI_LOAD_REGISTER_MEM
| (3 - 2));
1081 OUT_BATCH(reg
+ i
* 4);
1082 OUT_RELOC(bo
, 0, offset
+ i
* 4);
1089 brw_load_register_mem(struct brw_context
*brw
,
1094 load_sized_register_mem(brw
, reg
, bo
, offset
, 1);
1098 brw_load_register_mem64(struct brw_context
*brw
,
1103 load_sized_register_mem(brw
, reg
, bo
, offset
, 2);
1107 * Write an arbitrary 32-bit register to a buffer via MI_STORE_REGISTER_MEM.
1110 brw_store_register_mem32(struct brw_context
*brw
,
1111 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
)
1113 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1115 assert(devinfo
->gen
>= 6);
1117 if (devinfo
->gen
>= 8) {
1119 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
1121 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
1125 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
1127 OUT_RELOC(bo
, RELOC_WRITE
| RELOC_NEEDS_GGTT
, offset
);
1133 * Write an arbitrary 64-bit register to a buffer via MI_STORE_REGISTER_MEM.
1136 brw_store_register_mem64(struct brw_context
*brw
,
1137 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
)
1139 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1141 assert(devinfo
->gen
>= 6);
1143 /* MI_STORE_REGISTER_MEM only stores a single 32-bit value, so to
1144 * read a full 64-bit register, we need to do two of them.
1146 if (devinfo
->gen
>= 8) {
1148 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
1150 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
1151 OUT_BATCH(MI_STORE_REGISTER_MEM
| (4 - 2));
1152 OUT_BATCH(reg
+ sizeof(uint32_t));
1153 OUT_RELOC64(bo
, RELOC_WRITE
, offset
+ sizeof(uint32_t));
1157 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
1159 OUT_RELOC(bo
, RELOC_WRITE
| RELOC_NEEDS_GGTT
, offset
);
1160 OUT_BATCH(MI_STORE_REGISTER_MEM
| (3 - 2));
1161 OUT_BATCH(reg
+ sizeof(uint32_t));
1162 OUT_RELOC(bo
, RELOC_WRITE
| RELOC_NEEDS_GGTT
, offset
+ sizeof(uint32_t));
1168 * Write a 32-bit register using immediate data.
1171 brw_load_register_imm32(struct brw_context
*brw
, uint32_t reg
, uint32_t imm
)
1173 assert(brw
->screen
->devinfo
.gen
>= 6);
1176 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
1183 * Write a 64-bit register using immediate data.
1186 brw_load_register_imm64(struct brw_context
*brw
, uint32_t reg
, uint64_t imm
)
1188 assert(brw
->screen
->devinfo
.gen
>= 6);
1191 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (5 - 2));
1193 OUT_BATCH(imm
& 0xffffffff);
1195 OUT_BATCH(imm
>> 32);
1200 * Copies a 32-bit register.
1203 brw_load_register_reg(struct brw_context
*brw
, uint32_t src
, uint32_t dest
)
1205 assert(brw
->screen
->devinfo
.gen
>= 8 || brw
->screen
->devinfo
.is_haswell
);
1208 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1215 * Copies a 64-bit register.
1218 brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
, uint32_t dest
)
1220 assert(brw
->screen
->devinfo
.gen
>= 8 || brw
->screen
->devinfo
.is_haswell
);
1223 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1226 OUT_BATCH(MI_LOAD_REGISTER_REG
| (3 - 2));
1227 OUT_BATCH(src
+ sizeof(uint32_t));
1228 OUT_BATCH(dest
+ sizeof(uint32_t));
1233 * Write 32-bits of immediate data to a GPU memory buffer.
1236 brw_store_data_imm32(struct brw_context
*brw
, struct brw_bo
*bo
,
1237 uint32_t offset
, uint32_t imm
)
1239 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1241 assert(devinfo
->gen
>= 6);
1244 OUT_BATCH(MI_STORE_DATA_IMM
| (4 - 2));
1245 if (devinfo
->gen
>= 8)
1246 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
1248 OUT_BATCH(0); /* MBZ */
1249 OUT_RELOC(bo
, RELOC_WRITE
, offset
);
1256 * Write 64-bits of immediate data to a GPU memory buffer.
1259 brw_store_data_imm64(struct brw_context
*brw
, struct brw_bo
*bo
,
1260 uint32_t offset
, uint64_t imm
)
1262 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1264 assert(devinfo
->gen
>= 6);
1267 OUT_BATCH(MI_STORE_DATA_IMM
| (5 - 2));
1268 if (devinfo
->gen
>= 8)
1269 OUT_RELOC64(bo
, RELOC_WRITE
, offset
);
1271 OUT_BATCH(0); /* MBZ */
1272 OUT_RELOC(bo
, RELOC_WRITE
, offset
);
1274 OUT_BATCH(imm
& 0xffffffffu
);
1275 OUT_BATCH(imm
>> 32);