src/mesa/drivers/dri/i965/intel_batchbuffer.h

   1 #ifndef INTEL_BATCHBUFFER_H
   2 #define INTEL_BATCHBUFFER_H
   3
   4 #include "main/mtypes.h"
   5
   6 #include "brw_context.h"
   7 #include "brw_bufmgr.h"
   8
   9 #ifdef __cplusplus
  10 extern "C" {
  11 #endif
  12
  13 /* The kernel assumes batchbuffers are smaller than 256kB. */
  14 #define MAX_BATCH_SIZE (256 * 1024)
  15
  16 /* 3DSTATE_BINDING_TABLE_POINTERS has a U16 offset from Surface State Base
  17  * Address, which means that we can't put binding tables beyond 64kB.  This
  18  * effectively limits the maximum statebuffer size to 64kB.
  19  */
  20 #define MAX_STATE_SIZE (64 * 1024)
  21
  22 struct intel_batchbuffer;
  23
  24 void intel_batchbuffer_init(struct brw_context *brw);
  25 void intel_batchbuffer_free(struct intel_batchbuffer *batch);
  26 void intel_batchbuffer_save_state(struct brw_context *brw);
  27 void intel_batchbuffer_reset_to_saved(struct brw_context *brw);
  28 void intel_batchbuffer_require_space(struct brw_context *brw, GLuint sz,
  29                                      enum brw_gpu_ring ring);
  30 int _intel_batchbuffer_flush_fence(struct brw_context *brw,
  31                                    int in_fence_fd, int *out_fence_fd,
  32                                    const char *file, int line);
  33
  34 #define intel_batchbuffer_flush(brw) \
  35    _intel_batchbuffer_flush_fence((brw), -1, NULL, __FILE__, __LINE__)
  36
  37 #define intel_batchbuffer_flush_fence(brw, in_fence_fd, out_fence_fd) \
  38    _intel_batchbuffer_flush_fence((brw), (in_fence_fd), (out_fence_fd), \
  39                                   __FILE__, __LINE__)
  40
  41 /* Unlike bmBufferData, this currently requires the buffer be mapped.
  42  * Consider it a convenience function wrapping multple
  43  * intel_buffer_dword() calls.
  44  */
  45 void intel_batchbuffer_data(struct brw_context *brw,
  46                             const void *data, GLuint bytes,
  47                             enum brw_gpu_ring ring);
  48
  49 bool brw_batch_has_aperture_space(struct brw_context *brw,
  50                                   unsigned extra_space_in_bytes);
  51
  52 bool brw_batch_references(struct intel_batchbuffer *batch, struct brw_bo *bo);
  53
  54 #define RELOC_WRITE EXEC_OBJECT_WRITE
  55 #define RELOC_NEEDS_GGTT EXEC_OBJECT_NEEDS_GTT
  56 /* Inverted meaning, but using the same bit...emit_reloc will flip it. */
  57 #define RELOC_32BIT EXEC_OBJECT_SUPPORTS_48B_ADDRESS
  58 uint64_t brw_batch_reloc(struct intel_batchbuffer *batch,
  59                          uint32_t batch_offset,
  60                          struct brw_bo *target,
  61                          uint32_t target_offset,
  62                          unsigned flags);
  63 uint64_t brw_state_reloc(struct intel_batchbuffer *batch,
  64                          uint32_t batch_offset,
  65                          struct brw_bo *target,
  66                          uint32_t target_offset,
  67                          unsigned flags);
  68
  69 #define USED_BATCH(_batch) \
  70    ((uintptr_t)((_batch).map_next - (_batch).batch.map))
  71
  72 static inline uint32_t float_as_int(float f)
  73 {
  74    union {
  75       float f;
  76       uint32_t d;
  77    } fi;
  78
  79    fi.f = f;
  80    return fi.d;
  81 }
  82
  83 static inline void
  84 intel_batchbuffer_begin(struct brw_context *brw, int n, enum brw_gpu_ring ring)
  85 {
  86    intel_batchbuffer_require_space(brw, n * 4, ring);
  87
  88 #ifdef DEBUG
  89    brw->batch.emit = USED_BATCH(brw->batch);
  90    brw->batch.total = n;
  91 #endif
  92 }
  93
  94 static inline void
  95 intel_batchbuffer_advance(struct brw_context *brw)
  96 {
  97 #ifdef DEBUG
  98    struct intel_batchbuffer *batch = &brw->batch;
  99    unsigned int _n = USED_BATCH(*batch) - batch->emit;
 100    assert(batch->total != 0);
 101    if (_n != batch->total) {
 102       fprintf(stderr, "ADVANCE_BATCH: %d of %d dwords emitted\n",
 103               _n, batch->total);
 104       abort();
 105    }
 106    batch->total = 0;
 107 #else
 108    (void) brw;
 109 #endif
 110 }
 111
 112 static inline bool
 113 brw_ptr_in_state_buffer(struct intel_batchbuffer *batch, void *p)
 114 {
 115    return (char *) p >= (char *) batch->state.map &&
 116           (char *) p < (char *) batch->state.map + batch->state.bo->size;
 117 }
 118
 119 #define BEGIN_BATCH(n) do {                            \
 120    intel_batchbuffer_begin(brw, (n), RENDER_RING);     \
 121    uint32_t *__map = brw->batch.map_next;              \
 122    brw->batch.map_next += (n)
 123
 124 #define BEGIN_BATCH_BLT(n) do {                        \
 125    intel_batchbuffer_begin(brw, (n), BLT_RING);        \
 126    uint32_t *__map = brw->batch.map_next;              \
 127    brw->batch.map_next += (n)
 128
 129 #define OUT_BATCH(d) *__map++ = (d)
 130 #define OUT_BATCH_F(f) OUT_BATCH(float_as_int((f)))
 131
 132 #define OUT_RELOC(buf, flags, delta) do {          \
 133    uint32_t __offset = (__map - brw->batch.batch.map) * 4;              \
 134    uint32_t reloc =                                                     \
 135       brw_batch_reloc(&brw->batch, __offset, (buf), (delta), (flags));  \
 136    OUT_BATCH(reloc);                                                    \
 137 } while (0)
 138
 139 /* Handle 48-bit address relocations for Gen8+ */
 140 #define OUT_RELOC64(buf, flags, delta) do {        \
 141    uint32_t __offset = (__map - brw->batch.batch.map) * 4;              \
 142    uint64_t reloc64 =                                                   \
 143       brw_batch_reloc(&brw->batch, __offset, (buf), (delta), (flags));  \
 144    OUT_BATCH(reloc64);                                                  \
 145    OUT_BATCH(reloc64 >> 32);                                            \
 146 } while (0)
 147
 148 #define ADVANCE_BATCH()                  \
 149    assert(__map == brw->batch.map_next); \
 150    intel_batchbuffer_advance(brw);       \
 151 } while (0)
 152
 153 #ifdef __cplusplus
 154 }
 155 #endif
 156
 157 #endif