1 #ifndef INTEL_BATCHBUFFER_H
2 #define INTEL_BATCHBUFFER_H
4 #include "main/mtypes.h"
6 #include "brw_context.h"
7 #include "intel_bufmgr.h"
15 * Number of bytes to reserve for commands necessary to complete a batch.
18 * - MI_BATCHBUFFER_END (4 bytes)
19 * - Optional MI_NOOP for ensuring the batch length is qword aligned (4 bytes)
20 * - Any state emitted by vtbl->finish_batch():
21 * - Gen4-5 record ending occlusion query values (4 * 4 = 16 bytes)
22 * - Disabling OA counters on Gen6+ (3 DWords = 12 bytes)
23 * - Ending MI_REPORT_PERF_COUNT on Gen5+, plus associated PIPE_CONTROLs:
24 * - Two sets of PIPE_CONTROLs, which become 3 PIPE_CONTROLs each on SNB,
25 * which are 5 DWords each ==> 2 * 3 * 5 * 4 = 120 bytes
26 * - 3 DWords for MI_REPORT_PERF_COUNT itself on Gen6+. ==> 12 bytes.
27 * On Ironlake, it's 6 DWords, but we have some slack due to the lack of
28 * Sandybridge PIPE_CONTROL madness.
29 * - CC_STATE workaround on HSW (12 * 4 = 48 bytes)
30 * - 5 dwords for initial mi_flush
31 * - 2 dwords for CC state setup
32 * - 5 dwords for the required pipe control at the end
34 #define BATCH_RESERVED 152
36 struct intel_batchbuffer
;
38 void intel_batchbuffer_emit_render_ring_prelude(struct brw_context
*brw
);
39 void intel_batchbuffer_init(struct brw_context
*brw
);
40 void intel_batchbuffer_free(struct brw_context
*brw
);
41 void intel_batchbuffer_save_state(struct brw_context
*brw
);
42 void intel_batchbuffer_reset_to_saved(struct brw_context
*brw
);
44 int _intel_batchbuffer_flush(struct brw_context
*brw
,
45 const char *file
, int line
);
47 #define intel_batchbuffer_flush(intel) \
48 _intel_batchbuffer_flush(intel, __FILE__, __LINE__)
52 /* Unlike bmBufferData, this currently requires the buffer be mapped.
53 * Consider it a convenience function wrapping multple
54 * intel_buffer_dword() calls.
56 void intel_batchbuffer_data(struct brw_context
*brw
,
57 const void *data
, GLuint bytes
,
58 enum brw_gpu_ring ring
);
60 uint32_t intel_batchbuffer_reloc(struct brw_context
*brw
,
63 uint32_t read_domains
,
64 uint32_t write_domain
,
66 uint64_t intel_batchbuffer_reloc64(struct brw_context
*brw
,
69 uint32_t read_domains
,
70 uint32_t write_domain
,
73 #define USED_BATCH(batch) ((uintptr_t)((batch).map_next - (batch).map))
75 static inline uint32_t float_as_int(float f
)
86 /* Inline functions - might actually be better off with these
87 * non-inlined. Certainly better off switching all command packets to
88 * be passed as structs rather than dwords, but that's a little bit of
91 static inline unsigned
92 intel_batchbuffer_space(struct brw_context
*brw
)
94 return (brw
->batch
.state_batch_offset
- brw
->batch
.reserved_space
)
95 - USED_BATCH(brw
->batch
) * 4;
100 intel_batchbuffer_emit_dword(struct brw_context
*brw
, GLuint dword
)
103 assert(intel_batchbuffer_space(brw
) >= 4);
105 *brw
->batch
.map_next
++ = dword
;
106 assert(brw
->batch
.ring
!= UNKNOWN_RING
);
110 intel_batchbuffer_emit_float(struct brw_context
*brw
, float f
)
112 intel_batchbuffer_emit_dword(brw
, float_as_int(f
));
116 intel_batchbuffer_require_space(struct brw_context
*brw
, GLuint sz
,
117 enum brw_gpu_ring ring
)
119 /* If we're switching rings, implicitly flush the batch. */
120 if (unlikely(ring
!= brw
->batch
.ring
) && brw
->batch
.ring
!= UNKNOWN_RING
&&
122 intel_batchbuffer_flush(brw
);
126 assert(sz
< BATCH_SZ
- BATCH_RESERVED
);
128 if (intel_batchbuffer_space(brw
) < sz
)
129 intel_batchbuffer_flush(brw
);
131 enum brw_gpu_ring prev_ring
= brw
->batch
.ring
;
132 /* The intel_batchbuffer_flush() calls above might have changed
133 * brw->batch.ring to UNKNOWN_RING, so we need to set it here at the end.
135 brw
->batch
.ring
= ring
;
137 if (unlikely(prev_ring
== UNKNOWN_RING
&& ring
== RENDER_RING
))
138 intel_batchbuffer_emit_render_ring_prelude(brw
);
142 intel_batchbuffer_begin(struct brw_context
*brw
, int n
, enum brw_gpu_ring ring
)
144 intel_batchbuffer_require_space(brw
, n
* 4, ring
);
147 brw
->batch
.emit
= USED_BATCH(brw
->batch
);
148 brw
->batch
.total
= n
;
153 intel_batchbuffer_advance(struct brw_context
*brw
)
156 struct intel_batchbuffer
*batch
= &brw
->batch
;
157 unsigned int _n
= USED_BATCH(*batch
) - batch
->emit
;
158 assert(batch
->total
!= 0);
159 if (_n
!= batch
->total
) {
160 fprintf(stderr
, "ADVANCE_BATCH: %d of %d dwords emitted\n",
168 #define BEGIN_BATCH(n) do { \
169 intel_batchbuffer_begin(brw, (n), RENDER_RING); \
170 uint32_t *__map = brw->batch.map_next; \
171 brw->batch.map_next += (n)
173 #define BEGIN_BATCH_BLT(n) do { \
174 intel_batchbuffer_begin(brw, (n), BLT_RING); \
175 uint32_t *__map = brw->batch.map_next; \
176 brw->batch.map_next += (n)
178 #define OUT_BATCH(d) *__map++ = (d)
179 #define OUT_BATCH_F(f) OUT_BATCH(float_as_int((f)))
181 #define OUT_RELOC(buf, read_domains, write_domain, delta) do { \
182 uint32_t __offset = (__map - brw->batch.map) * 4; \
183 OUT_BATCH(intel_batchbuffer_reloc(brw, (buf), __offset, \
189 /* Handle 48-bit address relocations for Gen8+ */
190 #define OUT_RELOC64(buf, read_domains, write_domain, delta) do { \
191 uint32_t __offset = (__map - brw->batch.map) * 4; \
192 uint64_t reloc64 = intel_batchbuffer_reloc64(brw, (buf), __offset, \
196 OUT_BATCH(reloc64); \
197 OUT_BATCH(reloc64 >> 32); \
200 #define ADVANCE_BATCH() \
201 assert(__map == brw->batch.map_next); \
202 intel_batchbuffer_advance(brw); \