src/mesa/drivers/dri/i965/intel_batchbuffer.h

   1 #ifndef INTEL_BATCHBUFFER_H
   2 #define INTEL_BATCHBUFFER_H
   3
   4 #include "main/mtypes.h"
   5
   6 #include "brw_context.h"
   7 #include "intel_bufmgr.h"
   8
   9 #ifdef __cplusplus
  10 extern "C" {
  11 #endif
  12
  13 /**
  14  * Number of bytes to reserve for commands necessary to complete a batch.
  15  *
  16  * This includes:
  17  * - MI_BATCHBUFFER_END (4 bytes)
  18  * - Optional MI_NOOP for ensuring the batch length is qword aligned (4 bytes)
  19  * - Any state emitted by vtbl->finish_batch():
  20  *   - Gen4-5 record ending occlusion query values (4 * 4 = 16 bytes)
  21  *   - Disabling OA counters on Gen6+ (3 DWords = 12 bytes)
  22  *   - Ending MI_REPORT_PERF_COUNT on Gen5+, plus associated PIPE_CONTROLs:
  23  *     - Two sets of PIPE_CONTROLs, which become 4 PIPE_CONTROLs each on SNB,
  24  *       which are 5 DWords each ==> 2 * 4 * 5 * 4 = 160 bytes
  25  *     - 3 DWords for MI_REPORT_PERF_COUNT itself on Gen6+.  ==> 12 bytes.
  26  *       On Ironlake, it's 6 DWords, but we have some slack due to the lack of
  27  *       Sandybridge PIPE_CONTROL madness.
  28  *   - CC_STATE workaround on HSW (17 * 4 = 68 bytes)
  29  *     - 10 dwords for initial mi_flush
  30  *     - 2 dwords for CC state setup
  31  *     - 5 dwords for the required pipe control at the end
  32  *   - Restoring L3 configuration: (24 dwords = 96 bytes)
  33  *     - 2*6 dwords for two PIPE_CONTROL flushes.
  34  *     - 7 dwords for L3 configuration set-up.
  35  *     - 5 dwords for L3 atomic set-up (on HSW).
  36  */
  37 #define BATCH_RESERVED 308
  38
  39 struct intel_batchbuffer;
  40
  41 void intel_batchbuffer_emit_render_ring_prelude(struct brw_context *brw);
  42 void intel_batchbuffer_init(struct intel_batchbuffer *batch, dri_bufmgr *bufmgr,
  43                             bool has_llc);
  44 void intel_batchbuffer_free(struct intel_batchbuffer *batch);
  45 void intel_batchbuffer_save_state(struct brw_context *brw);
  46 void intel_batchbuffer_reset_to_saved(struct brw_context *brw);
  47 void intel_batchbuffer_require_space(struct brw_context *brw, GLuint sz,
  48                                      enum brw_gpu_ring ring);
  49 int _intel_batchbuffer_flush_fence(struct brw_context *brw,
  50                                    int in_fence_fd, int *out_fence_fd,
  51                                    const char *file, int line);
  52
  53 #define intel_batchbuffer_flush(brw) \
  54    _intel_batchbuffer_flush_fence((brw), -1, NULL, __FILE__, __LINE__)
  55
  56 #define intel_batchbuffer_flush_fence(brw, in_fence_fd, out_fence_fd) \
  57    _intel_batchbuffer_flush_fence((brw), (in_fence_fd), (out_fence_fd), \
  58                                   __FILE__, __LINE__)
  59
  60 /* Unlike bmBufferData, this currently requires the buffer be mapped.
  61  * Consider it a convenience function wrapping multple
  62  * intel_buffer_dword() calls.
  63  */
  64 void intel_batchbuffer_data(struct brw_context *brw,
  65                             const void *data, GLuint bytes,
  66                             enum brw_gpu_ring ring);
  67
  68 uint32_t intel_batchbuffer_reloc(struct intel_batchbuffer *batch,
  69                                  drm_intel_bo *buffer,
  70                                  uint32_t offset,
  71                                  uint32_t read_domains,
  72                                  uint32_t write_domain,
  73                                  uint32_t delta);
  74 uint64_t intel_batchbuffer_reloc64(struct intel_batchbuffer *batch,
  75                                    drm_intel_bo *buffer,
  76                                    uint32_t offset,
  77                                    uint32_t read_domains,
  78                                    uint32_t write_domain,
  79                                    uint32_t delta);
  80
  81 #define USED_BATCH(batch) ((uintptr_t)((batch).map_next - (batch).map))
  82
  83 static inline uint32_t float_as_int(float f)
  84 {
  85    union {
  86       float f;
  87       uint32_t d;
  88    } fi;
  89
  90    fi.f = f;
  91    return fi.d;
  92 }
  93
  94 /* Inline functions - might actually be better off with these
  95  * non-inlined.  Certainly better off switching all command packets to
  96  * be passed as structs rather than dwords, but that's a little bit of
  97  * work...
  98  */
  99 static inline unsigned
 100 intel_batchbuffer_space(struct intel_batchbuffer *batch)
 101 {
 102    return (batch->state_batch_offset - batch->reserved_space)
 103       - USED_BATCH(*batch) * 4;
 104 }
 105
 106
 107 static inline void
 108 intel_batchbuffer_emit_dword(struct intel_batchbuffer *batch, GLuint dword)
 109 {
 110 #ifdef DEBUG
 111    assert(intel_batchbuffer_space(batch) >= 4);
 112 #endif
 113    *batch->map_next++ = dword;
 114    assert(batch->ring != UNKNOWN_RING);
 115 }
 116
 117 static inline void
 118 intel_batchbuffer_emit_float(struct intel_batchbuffer *batch, float f)
 119 {
 120    intel_batchbuffer_emit_dword(batch, float_as_int(f));
 121 }
 122
 123 static inline void
 124 intel_batchbuffer_begin(struct brw_context *brw, int n, enum brw_gpu_ring ring)
 125 {
 126    intel_batchbuffer_require_space(brw, n * 4, ring);
 127
 128 #ifdef DEBUG
 129    brw->batch.emit = USED_BATCH(brw->batch);
 130    brw->batch.total = n;
 131 #endif
 132 }
 133
 134 static inline void
 135 intel_batchbuffer_advance(struct brw_context *brw)
 136 {
 137 #ifdef DEBUG
 138    struct intel_batchbuffer *batch = &brw->batch;
 139    unsigned int _n = USED_BATCH(*batch) - batch->emit;
 140    assert(batch->total != 0);
 141    if (_n != batch->total) {
 142       fprintf(stderr, "ADVANCE_BATCH: %d of %d dwords emitted\n",
 143               _n, batch->total);
 144       abort();
 145    }
 146    batch->total = 0;
 147 #else
 148    (void) brw;
 149 #endif
 150 }
 151
 152 #define BEGIN_BATCH(n) do {                            \
 153    intel_batchbuffer_begin(brw, (n), RENDER_RING);     \
 154    uint32_t *__map = brw->batch.map_next;              \
 155    brw->batch.map_next += (n)
 156
 157 #define BEGIN_BATCH_BLT(n) do {                        \
 158    intel_batchbuffer_begin(brw, (n), BLT_RING);        \
 159    uint32_t *__map = brw->batch.map_next;              \
 160    brw->batch.map_next += (n)
 161
 162 #define OUT_BATCH(d) *__map++ = (d)
 163 #define OUT_BATCH_F(f) OUT_BATCH(float_as_int((f)))
 164
 165 #define OUT_RELOC(buf, read_domains, write_domain, delta) do {    \
 166    uint32_t __offset = (__map - brw->batch.map) * 4;              \
 167    OUT_BATCH(intel_batchbuffer_reloc(&brw->batch, (buf), __offset, \
 168                                      (read_domains),              \
 169                                      (write_domain),              \
 170                                      (delta)));                   \
 171 } while (0)
 172
 173 /* Handle 48-bit address relocations for Gen8+ */
 174 #define OUT_RELOC64(buf, read_domains, write_domain, delta) do {      \
 175    uint32_t __offset = (__map - brw->batch.map) * 4;                  \
 176    uint64_t reloc64 = intel_batchbuffer_reloc64(&brw->batch, (buf), __offset, \
 177                                                 (read_domains),       \
 178                                                 (write_domain),       \
 179                                                 (delta));             \
 180    OUT_BATCH(reloc64);                                                \
 181    OUT_BATCH(reloc64 >> 32);                                          \
 182 } while (0)
 183
 184 #define ADVANCE_BATCH()                  \
 185    assert(__map == brw->batch.map_next); \
 186    intel_batchbuffer_advance(brw);       \
 187 } while (0)
 188
 189 #ifdef __cplusplus
 190 }
 191 #endif
 192
 193 #endif