src/mesa/drivers/dri/i965/intel_batchbuffer.h

   1 #ifndef INTEL_BATCHBUFFER_H
   2 #define INTEL_BATCHBUFFER_H
   3
   4 #include "main/mtypes.h"
   5
   6 #include "brw_context.h"
   7 #include "intel_bufmgr.h"
   8 #include "intel_reg.h"
   9
  10 #ifdef __cplusplus
  11 extern "C" {
  12 #endif
  13
  14 /**
  15  * Number of bytes to reserve for commands necessary to complete a batch.
  16  *
  17  * This includes:
  18  * - MI_BATCHBUFFER_END (4 bytes)
  19  * - Optional MI_NOOP for ensuring the batch length is qword aligned (4 bytes)
  20  * - Any state emitted by vtbl->finish_batch():
  21  *   - Gen4-5 record ending occlusion query values (4 * 4 = 16 bytes)
  22  */
  23 #define BATCH_RESERVED 24
  24
  25 struct intel_batchbuffer;
  26
  27 void intel_batchbuffer_init(struct brw_context *brw);
  28 void intel_batchbuffer_free(struct brw_context *brw);
  29 void intel_batchbuffer_save_state(struct brw_context *brw);
  30 void intel_batchbuffer_reset_to_saved(struct brw_context *brw);
  31 void intel_batchbuffer_clear_cache(struct brw_context *brw);
  32
  33 int _intel_batchbuffer_flush(struct brw_context *brw,
  34                              const char *file, int line);
  35
  36 #define intel_batchbuffer_flush(intel) \
  37         _intel_batchbuffer_flush(intel, __FILE__, __LINE__)
  38
  39
  40
  41 /* Unlike bmBufferData, this currently requires the buffer be mapped.
  42  * Consider it a convenience function wrapping multple
  43  * intel_buffer_dword() calls.
  44  */
  45 void intel_batchbuffer_data(struct brw_context *brw,
  46                             const void *data, GLuint bytes, bool is_blit);
  47
  48 bool intel_batchbuffer_emit_reloc(struct brw_context *brw,
  49                                        drm_intel_bo *buffer,
  50                                        uint32_t read_domains,
  51                                        uint32_t write_domain,
  52                                        uint32_t offset);
  53 bool intel_batchbuffer_emit_reloc_fenced(struct brw_context *brw,
  54                                               drm_intel_bo *buffer,
  55                                               uint32_t read_domains,
  56                                               uint32_t write_domain,
  57                                               uint32_t offset);
  58 void intel_batchbuffer_emit_mi_flush(struct brw_context *brw);
  59 void intel_emit_post_sync_nonzero_flush(struct brw_context *brw);
  60 void intel_emit_depth_stall_flushes(struct brw_context *brw);
  61 void gen7_emit_vs_workaround_flush(struct brw_context *brw);
  62
  63 static INLINE uint32_t float_as_int(float f)
  64 {
  65    union {
  66       float f;
  67       uint32_t d;
  68    } fi;
  69
  70    fi.f = f;
  71    return fi.d;
  72 }
  73
  74 /* Inline functions - might actually be better off with these
  75  * non-inlined.  Certainly better off switching all command packets to
  76  * be passed as structs rather than dwords, but that's a little bit of
  77  * work...
  78  */
  79 static INLINE unsigned
  80 intel_batchbuffer_space(struct brw_context *brw)
  81 {
  82    return (brw->batch.state_batch_offset - brw->batch.reserved_space)
  83       - brw->batch.used*4;
  84 }
  85
  86
  87 static INLINE void
  88 intel_batchbuffer_emit_dword(struct brw_context *brw, GLuint dword)
  89 {
  90 #ifdef DEBUG
  91    assert(intel_batchbuffer_space(brw) >= 4);
  92 #endif
  93    brw->batch.map[brw->batch.used++] = dword;
  94 }
  95
  96 static INLINE void
  97 intel_batchbuffer_emit_float(struct brw_context *brw, float f)
  98 {
  99    intel_batchbuffer_emit_dword(brw, float_as_int(f));
 100 }
 101
 102 static INLINE void
 103 intel_batchbuffer_require_space(struct brw_context *brw, GLuint sz, int is_blit)
 104 {
 105    if (brw->gen >= 6 &&
 106        brw->batch.is_blit != is_blit && brw->batch.used) {
 107       intel_batchbuffer_flush(brw);
 108    }
 109
 110    brw->batch.is_blit = is_blit;
 111
 112 #ifdef DEBUG
 113    assert(sz < BATCH_SZ - BATCH_RESERVED);
 114 #endif
 115    if (intel_batchbuffer_space(brw) < sz)
 116       intel_batchbuffer_flush(brw);
 117 }
 118
 119 static INLINE void
 120 intel_batchbuffer_begin(struct brw_context *brw, int n, bool is_blit)
 121 {
 122    intel_batchbuffer_require_space(brw, n * 4, is_blit);
 123
 124    brw->batch.emit = brw->batch.used;
 125 #ifdef DEBUG
 126    brw->batch.total = n;
 127 #endif
 128 }
 129
 130 static INLINE void
 131 intel_batchbuffer_advance(struct brw_context *brw)
 132 {
 133 #ifdef DEBUG
 134    struct intel_batchbuffer *batch = &brw->batch;
 135    unsigned int _n = batch->used - batch->emit;
 136    assert(batch->total != 0);
 137    if (_n != batch->total) {
 138       fprintf(stderr, "ADVANCE_BATCH: %d of %d dwords emitted\n",
 139               _n, batch->total);
 140       abort();
 141    }
 142    batch->total = 0;
 143 #endif
 144 }
 145
 146 void intel_batchbuffer_cached_advance(struct brw_context *brw);
 147
 148 #define BEGIN_BATCH(n) intel_batchbuffer_begin(brw, n, false)
 149 #define BEGIN_BATCH_BLT(n) intel_batchbuffer_begin(brw, n, true)
 150 #define OUT_BATCH(d) intel_batchbuffer_emit_dword(brw, d)
 151 #define OUT_BATCH_F(f) intel_batchbuffer_emit_float(brw, f)
 152 #define OUT_RELOC(buf, read_domains, write_domain, delta) do {          \
 153    intel_batchbuffer_emit_reloc(brw, buf,                       \
 154                                 read_domains, write_domain, delta);     \
 155 } while (0)
 156 #define OUT_RELOC_FENCED(buf, read_domains, write_domain, delta) do {   \
 157    intel_batchbuffer_emit_reloc_fenced(brw, buf,                \
 158                                        read_domains, write_domain, delta); \
 159 } while (0)
 160
 161 #define ADVANCE_BATCH() intel_batchbuffer_advance(brw);
 162 #define CACHED_BATCH() intel_batchbuffer_cached_advance(brw);
 163
 164 #ifdef __cplusplus
 165 }
 166 #endif
 167
 168 #endif