src/mesa/drivers/dri/i965/intel_batchbuffer.h

   1 #ifndef INTEL_BATCHBUFFER_H
   2 #define INTEL_BATCHBUFFER_H
   3
   4 #include "main/mtypes.h"
   5
   6 #include "brw_context.h"
   7 #include "intel_bufmgr.h"
   8 #include "intel_reg.h"
   9
  10 #ifdef __cplusplus
  11 extern "C" {
  12 #endif
  13
  14 /**
  15  * Number of bytes to reserve for commands necessary to complete a batch.
  16  *
  17  * This includes:
  18  * - MI_BATCHBUFFER_END (4 bytes)
  19  * - Optional MI_NOOP for ensuring the batch length is qword aligned (4 bytes)
  20  * - Any state emitted by vtbl->finish_batch():
  21  *   - Gen4-5 record ending occlusion query values (4 * 4 = 16 bytes)
  22  *   - Disabling OA counters on Gen6+ (3 DWords = 12 bytes)
  23  *   - Ending MI_REPORT_PERF_COUNT on Gen5+, plus associated PIPE_CONTROLs:
  24  *     - Two sets of PIPE_CONTROLs, which become 3 PIPE_CONTROLs each on SNB,
  25  *       which are 5 DWords each ==> 2 * 3 * 5 * 4 = 120 bytes
  26  *     - 3 DWords for MI_REPORT_PERF_COUNT itself on Gen6+.  ==> 12 bytes.
  27  *       On Ironlake, it's 6 DWords, but we have some slack due to the lack of
  28  *       Sandybridge PIPE_CONTROL madness.
  29  *   - CC_STATE workaround on HSW (12 * 4 = 48 bytes)
  30  *     - 5 dwords for initial mi_flush
  31  *     - 2 dwords for CC state setup
  32  *     - 5 dwords for the required pipe control at the end
  33  *   - Restoring L3 configuration: (24 dwords = 96 bytes)
  34  *     - 2*6 dwords for two PIPE_CONTROL flushes.
  35  *     - 7 dwords for L3 configuration set-up.
  36  *     - 5 dwords for L3 atomic set-up (on HSW).
  37  */
  38 #define BATCH_RESERVED 248
  39
  40 struct intel_batchbuffer;
  41
  42 void intel_batchbuffer_emit_render_ring_prelude(struct brw_context *brw);
  43 void intel_batchbuffer_init(struct brw_context *brw);
  44 void intel_batchbuffer_free(struct brw_context *brw);
  45 void intel_batchbuffer_save_state(struct brw_context *brw);
  46 void intel_batchbuffer_reset_to_saved(struct brw_context *brw);
  47
  48 int _intel_batchbuffer_flush(struct brw_context *brw,
  49                              const char *file, int line);
  50
  51 #define intel_batchbuffer_flush(intel) \
  52         _intel_batchbuffer_flush(intel, __FILE__, __LINE__)
  53
  54
  55
  56 /* Unlike bmBufferData, this currently requires the buffer be mapped.
  57  * Consider it a convenience function wrapping multple
  58  * intel_buffer_dword() calls.
  59  */
  60 void intel_batchbuffer_data(struct brw_context *brw,
  61                             const void *data, GLuint bytes,
  62                             enum brw_gpu_ring ring);
  63
  64 uint32_t intel_batchbuffer_reloc(struct brw_context *brw,
  65                                  drm_intel_bo *buffer,
  66                                  uint32_t offset,
  67                                  uint32_t read_domains,
  68                                  uint32_t write_domain,
  69                                  uint32_t delta);
  70 uint64_t intel_batchbuffer_reloc64(struct brw_context *brw,
  71                                    drm_intel_bo *buffer,
  72                                    uint32_t offset,
  73                                    uint32_t read_domains,
  74                                    uint32_t write_domain,
  75                                    uint32_t delta);
  76
  77 #define USED_BATCH(batch) ((uintptr_t)((batch).map_next - (batch).map))
  78
  79 static inline uint32_t float_as_int(float f)
  80 {
  81    union {
  82       float f;
  83       uint32_t d;
  84    } fi;
  85
  86    fi.f = f;
  87    return fi.d;
  88 }
  89
  90 /* Inline functions - might actually be better off with these
  91  * non-inlined.  Certainly better off switching all command packets to
  92  * be passed as structs rather than dwords, but that's a little bit of
  93  * work...
  94  */
  95 static inline unsigned
  96 intel_batchbuffer_space(struct brw_context *brw)
  97 {
  98    return (brw->batch.state_batch_offset - brw->batch.reserved_space)
  99       - USED_BATCH(brw->batch) * 4;
 100 }
 101
 102
 103 static inline void
 104 intel_batchbuffer_emit_dword(struct brw_context *brw, GLuint dword)
 105 {
 106 #ifdef DEBUG
 107    assert(intel_batchbuffer_space(brw) >= 4);
 108 #endif
 109    *brw->batch.map_next++ = dword;
 110    assert(brw->batch.ring != UNKNOWN_RING);
 111 }
 112
 113 static inline void
 114 intel_batchbuffer_emit_float(struct brw_context *brw, float f)
 115 {
 116    intel_batchbuffer_emit_dword(brw, float_as_int(f));
 117 }
 118
 119 static inline void
 120 intel_batchbuffer_require_space(struct brw_context *brw, GLuint sz,
 121                                 enum brw_gpu_ring ring)
 122 {
 123    /* If we're switching rings, implicitly flush the batch. */
 124    if (unlikely(ring != brw->batch.ring) && brw->batch.ring != UNKNOWN_RING &&
 125        brw->gen >= 6) {
 126       intel_batchbuffer_flush(brw);
 127    }
 128
 129 #ifdef DEBUG
 130    assert(sz < BATCH_SZ - BATCH_RESERVED);
 131 #endif
 132    if (intel_batchbuffer_space(brw) < sz)
 133       intel_batchbuffer_flush(brw);
 134
 135    enum brw_gpu_ring prev_ring = brw->batch.ring;
 136    /* The intel_batchbuffer_flush() calls above might have changed
 137     * brw->batch.ring to UNKNOWN_RING, so we need to set it here at the end.
 138     */
 139    brw->batch.ring = ring;
 140
 141    if (unlikely(prev_ring == UNKNOWN_RING && ring == RENDER_RING))
 142       intel_batchbuffer_emit_render_ring_prelude(brw);
 143 }
 144
 145 static inline void
 146 intel_batchbuffer_begin(struct brw_context *brw, int n, enum brw_gpu_ring ring)
 147 {
 148    intel_batchbuffer_require_space(brw, n * 4, ring);
 149
 150 #ifdef DEBUG
 151    brw->batch.emit = USED_BATCH(brw->batch);
 152    brw->batch.total = n;
 153 #endif
 154 }
 155
 156 static inline void
 157 intel_batchbuffer_advance(struct brw_context *brw)
 158 {
 159 #ifdef DEBUG
 160    struct intel_batchbuffer *batch = &brw->batch;
 161    unsigned int _n = USED_BATCH(*batch) - batch->emit;
 162    assert(batch->total != 0);
 163    if (_n != batch->total) {
 164       fprintf(stderr, "ADVANCE_BATCH: %d of %d dwords emitted\n",
 165               _n, batch->total);
 166       abort();
 167    }
 168    batch->total = 0;
 169 #else
 170    (void) brw;
 171 #endif
 172 }
 173
 174 #define BEGIN_BATCH(n) do {                            \
 175    intel_batchbuffer_begin(brw, (n), RENDER_RING);     \
 176    uint32_t *__map = brw->batch.map_next;              \
 177    brw->batch.map_next += (n)
 178
 179 #define BEGIN_BATCH_BLT(n) do {                        \
 180    intel_batchbuffer_begin(brw, (n), BLT_RING);        \
 181    uint32_t *__map = brw->batch.map_next;              \
 182    brw->batch.map_next += (n)
 183
 184 #define OUT_BATCH(d) *__map++ = (d)
 185 #define OUT_BATCH_F(f) OUT_BATCH(float_as_int((f)))
 186
 187 #define OUT_RELOC(buf, read_domains, write_domain, delta) do { \
 188    uint32_t __offset = (__map - brw->batch.map) * 4;           \
 189    OUT_BATCH(intel_batchbuffer_reloc(brw, (buf), __offset,     \
 190                                      (read_domains),           \
 191                                      (write_domain),           \
 192                                      (delta)));                \
 193 } while (0)
 194
 195 /* Handle 48-bit address relocations for Gen8+ */
 196 #define OUT_RELOC64(buf, read_domains, write_domain, delta) do {      \
 197    uint32_t __offset = (__map - brw->batch.map) * 4;                  \
 198    uint64_t reloc64 = intel_batchbuffer_reloc64(brw, (buf), __offset, \
 199                                                 (read_domains),       \
 200                                                 (write_domain),       \
 201                                                 (delta));             \
 202    OUT_BATCH(reloc64);                                                \
 203    OUT_BATCH(reloc64 >> 32);                                          \
 204 } while (0)
 205
 206 #define ADVANCE_BATCH()                  \
 207    assert(__map == brw->batch.map_next); \
 208    intel_batchbuffer_advance(brw);       \
 209 } while (0)
 210
 211 #ifdef __cplusplus
 212 }
 213 #endif
 214
 215 #endif