src/mesa/drivers/dri/i965/intel_batchbuffer.h

   1 #ifndef INTEL_BATCHBUFFER_H
   2 #define INTEL_BATCHBUFFER_H
   3
   4 #include "main/mtypes.h"
   5
   6 #include "brw_context.h"
   7 #include "intel_bufmgr.h"
   8 #include "intel_reg.h"
   9
  10 #ifdef __cplusplus
  11 extern "C" {
  12 #endif
  13
  14 /**
  15  * Number of bytes to reserve for commands necessary to complete a batch.
  16  *
  17  * This includes:
  18  * - MI_BATCHBUFFER_END (4 bytes)
  19  * - Optional MI_NOOP for ensuring the batch length is qword aligned (4 bytes)
  20  * - Any state emitted by vtbl->finish_batch():
  21  *   - Gen4-5 record ending occlusion query values (4 * 4 = 16 bytes)
  22  */
  23 #define BATCH_RESERVED 24
  24
  25 struct intel_batchbuffer;
  26
  27 void intel_batchbuffer_init(struct brw_context *brw);
  28 void intel_batchbuffer_free(struct brw_context *brw);
  29 void intel_batchbuffer_save_state(struct brw_context *brw);
  30 void intel_batchbuffer_reset_to_saved(struct brw_context *brw);
  31 void intel_batchbuffer_clear_cache(struct brw_context *brw);
  32
  33 int _intel_batchbuffer_flush(struct brw_context *brw,
  34                              const char *file, int line);
  35
  36 #define intel_batchbuffer_flush(intel) \
  37         _intel_batchbuffer_flush(intel, __FILE__, __LINE__)
  38
  39
  40
  41 /* Unlike bmBufferData, this currently requires the buffer be mapped.
  42  * Consider it a convenience function wrapping multple
  43  * intel_buffer_dword() calls.
  44  */
  45 void intel_batchbuffer_data(struct brw_context *brw,
  46                             const void *data, GLuint bytes,
  47                             enum brw_gpu_ring ring);
  48
  49 bool intel_batchbuffer_emit_reloc(struct brw_context *brw,
  50                                        drm_intel_bo *buffer,
  51                                        uint32_t read_domains,
  52                                        uint32_t write_domain,
  53                                        uint32_t offset);
  54 bool intel_batchbuffer_emit_reloc_fenced(struct brw_context *brw,
  55                                               drm_intel_bo *buffer,
  56                                               uint32_t read_domains,
  57                                               uint32_t write_domain,
  58                                               uint32_t offset);
  59 void intel_batchbuffer_emit_mi_flush(struct brw_context *brw);
  60 void intel_emit_post_sync_nonzero_flush(struct brw_context *brw);
  61 void intel_emit_depth_stall_flushes(struct brw_context *brw);
  62 void gen7_emit_vs_workaround_flush(struct brw_context *brw);
  63 void gen7_emit_cs_stall_flush(struct brw_context *brw);
  64
  65 static INLINE uint32_t float_as_int(float f)
  66 {
  67    union {
  68       float f;
  69       uint32_t d;
  70    } fi;
  71
  72    fi.f = f;
  73    return fi.d;
  74 }
  75
  76 /* Inline functions - might actually be better off with these
  77  * non-inlined.  Certainly better off switching all command packets to
  78  * be passed as structs rather than dwords, but that's a little bit of
  79  * work...
  80  */
  81 static INLINE unsigned
  82 intel_batchbuffer_space(struct brw_context *brw)
  83 {
  84    return (brw->batch.state_batch_offset - brw->batch.reserved_space)
  85       - brw->batch.used*4;
  86 }
  87
  88
  89 static INLINE void
  90 intel_batchbuffer_emit_dword(struct brw_context *brw, GLuint dword)
  91 {
  92 #ifdef DEBUG
  93    assert(intel_batchbuffer_space(brw) >= 4);
  94 #endif
  95    brw->batch.map[brw->batch.used++] = dword;
  96    assert(brw->batch.ring != UNKNOWN_RING);
  97 }
  98
  99 static INLINE void
 100 intel_batchbuffer_emit_float(struct brw_context *brw, float f)
 101 {
 102    intel_batchbuffer_emit_dword(brw, float_as_int(f));
 103 }
 104
 105 static INLINE void
 106 intel_batchbuffer_require_space(struct brw_context *brw, GLuint sz,
 107                                 enum brw_gpu_ring ring)
 108 {
 109    /* If we're switching rings, implicitly flush the batch. */
 110    if (unlikely(ring != brw->batch.ring) && brw->batch.ring != UNKNOWN_RING &&
 111        brw->gen >= 6) {
 112       intel_batchbuffer_flush(brw);
 113    }
 114
 115 #ifdef DEBUG
 116    assert(sz < BATCH_SZ - BATCH_RESERVED);
 117 #endif
 118    if (intel_batchbuffer_space(brw) < sz)
 119       intel_batchbuffer_flush(brw);
 120
 121    /* The intel_batchbuffer_flush() calls above might have changed
 122     * brw->batch.ring to UNKNOWN_RING, so we need to set it here at the end.
 123     */
 124    brw->batch.ring = ring;
 125 }
 126
 127 static INLINE void
 128 intel_batchbuffer_begin(struct brw_context *brw, int n, enum brw_gpu_ring ring)
 129 {
 130    intel_batchbuffer_require_space(brw, n * 4, ring);
 131
 132    brw->batch.emit = brw->batch.used;
 133 #ifdef DEBUG
 134    brw->batch.total = n;
 135 #endif
 136 }
 137
 138 static INLINE void
 139 intel_batchbuffer_advance(struct brw_context *brw)
 140 {
 141 #ifdef DEBUG
 142    struct intel_batchbuffer *batch = &brw->batch;
 143    unsigned int _n = batch->used - batch->emit;
 144    assert(batch->total != 0);
 145    if (_n != batch->total) {
 146       fprintf(stderr, "ADVANCE_BATCH: %d of %d dwords emitted\n",
 147               _n, batch->total);
 148       abort();
 149    }
 150    batch->total = 0;
 151 #endif
 152 }
 153
 154 void intel_batchbuffer_cached_advance(struct brw_context *brw);
 155
 156 #define BEGIN_BATCH(n) intel_batchbuffer_begin(brw, n, RENDER_RING)
 157 #define BEGIN_BATCH_BLT(n) intel_batchbuffer_begin(brw, n, BLT_RING)
 158 #define OUT_BATCH(d) intel_batchbuffer_emit_dword(brw, d)
 159 #define OUT_BATCH_F(f) intel_batchbuffer_emit_float(brw, f)
 160 #define OUT_RELOC(buf, read_domains, write_domain, delta) do {          \
 161    intel_batchbuffer_emit_reloc(brw, buf,                       \
 162                                 read_domains, write_domain, delta);     \
 163 } while (0)
 164 #define OUT_RELOC_FENCED(buf, read_domains, write_domain, delta) do {   \
 165    intel_batchbuffer_emit_reloc_fenced(brw, buf,                \
 166                                        read_domains, write_domain, delta); \
 167 } while (0)
 168
 169 #define ADVANCE_BATCH() intel_batchbuffer_advance(brw);
 170 #define CACHED_BATCH() intel_batchbuffer_cached_advance(brw);
 171
 172 #ifdef __cplusplus
 173 }
 174 #endif
 175
 176 #endif