src/mesa/drivers/dri/i965/intel_batchbuffer.h

   1 #ifndef INTEL_BATCHBUFFER_H
   2 #define INTEL_BATCHBUFFER_H
   3
   4 #include "main/mtypes.h"
   5
   6 #include "brw_context.h"
   7 #include "intel_bufmgr.h"
   8
   9 #ifdef __cplusplus
  10 extern "C" {
  11 #endif
  12
  13 /**
  14  * Number of bytes to reserve for commands necessary to complete a batch.
  15  *
  16  * This includes:
  17  * - MI_BATCHBUFFER_END (4 bytes)
  18  * - Optional MI_NOOP for ensuring the batch length is qword aligned (4 bytes)
  19  * - Any state emitted by vtbl->finish_batch():
  20  *   - Gen4-5 record ending occlusion query values (4 * 4 = 16 bytes)
  21  *   - Disabling OA counters on Gen6+ (3 DWords = 12 bytes)
  22  *   - Ending MI_REPORT_PERF_COUNT on Gen5+, plus associated PIPE_CONTROLs:
  23  *     - Two sets of PIPE_CONTROLs, which become 4 PIPE_CONTROLs each on SNB,
  24  *       which are 5 DWords each ==> 2 * 4 * 5 * 4 = 160 bytes
  25  *     - 3 DWords for MI_REPORT_PERF_COUNT itself on Gen6+.  ==> 12 bytes.
  26  *       On Ironlake, it's 6 DWords, but we have some slack due to the lack of
  27  *       Sandybridge PIPE_CONTROL madness.
  28  *   - CC_STATE workaround on HSW (17 * 4 = 68 bytes)
  29  *     - 10 dwords for initial mi_flush
  30  *     - 2 dwords for CC state setup
  31  *     - 5 dwords for the required pipe control at the end
  32  *   - Restoring L3 configuration: (24 dwords = 96 bytes)
  33  *     - 2*6 dwords for two PIPE_CONTROL flushes.
  34  *     - 7 dwords for L3 configuration set-up.
  35  *     - 5 dwords for L3 atomic set-up (on HSW).
  36  */
  37 #define BATCH_RESERVED 308
  38
  39 struct intel_batchbuffer;
  40
  41 void intel_batchbuffer_emit_render_ring_prelude(struct brw_context *brw);
  42 void intel_batchbuffer_init(struct brw_context *brw);
  43 void intel_batchbuffer_free(struct brw_context *brw);
  44 void intel_batchbuffer_save_state(struct brw_context *brw);
  45 void intel_batchbuffer_reset_to_saved(struct brw_context *brw);
  46 void intel_batchbuffer_require_space(struct brw_context *brw, GLuint sz,
  47                                      enum brw_gpu_ring ring);
  48
  49 int _intel_batchbuffer_flush(struct brw_context *brw,
  50                              const char *file, int line);
  51
  52 #define intel_batchbuffer_flush(intel) \
  53         _intel_batchbuffer_flush(intel, __FILE__, __LINE__)
  54
  55
  56
  57 /* Unlike bmBufferData, this currently requires the buffer be mapped.
  58  * Consider it a convenience function wrapping multple
  59  * intel_buffer_dword() calls.
  60  */
  61 void intel_batchbuffer_data(struct brw_context *brw,
  62                             const void *data, GLuint bytes,
  63                             enum brw_gpu_ring ring);
  64
  65 uint32_t intel_batchbuffer_reloc(struct brw_context *brw,
  66                                  drm_intel_bo *buffer,
  67                                  uint32_t offset,
  68                                  uint32_t read_domains,
  69                                  uint32_t write_domain,
  70                                  uint32_t delta);
  71 uint64_t intel_batchbuffer_reloc64(struct brw_context *brw,
  72                                    drm_intel_bo *buffer,
  73                                    uint32_t offset,
  74                                    uint32_t read_domains,
  75                                    uint32_t write_domain,
  76                                    uint32_t delta);
  77
  78 #define USED_BATCH(batch) ((uintptr_t)((batch).map_next - (batch).map))
  79
  80 static inline uint32_t float_as_int(float f)
  81 {
  82    union {
  83       float f;
  84       uint32_t d;
  85    } fi;
  86
  87    fi.f = f;
  88    return fi.d;
  89 }
  90
  91 /* Inline functions - might actually be better off with these
  92  * non-inlined.  Certainly better off switching all command packets to
  93  * be passed as structs rather than dwords, but that's a little bit of
  94  * work...
  95  */
  96 static inline unsigned
  97 intel_batchbuffer_space(struct brw_context *brw)
  98 {
  99    return (brw->batch.state_batch_offset - brw->batch.reserved_space)
 100       - USED_BATCH(brw->batch) * 4;
 101 }
 102
 103
 104 static inline void
 105 intel_batchbuffer_emit_dword(struct brw_context *brw, GLuint dword)
 106 {
 107 #ifdef DEBUG
 108    assert(intel_batchbuffer_space(brw) >= 4);
 109 #endif
 110    *brw->batch.map_next++ = dword;
 111    assert(brw->batch.ring != UNKNOWN_RING);
 112 }
 113
 114 static inline void
 115 intel_batchbuffer_emit_float(struct brw_context *brw, float f)
 116 {
 117    intel_batchbuffer_emit_dword(brw, float_as_int(f));
 118 }
 119
 120 static inline void
 121 intel_batchbuffer_begin(struct brw_context *brw, int n, enum brw_gpu_ring ring)
 122 {
 123    intel_batchbuffer_require_space(brw, n * 4, ring);
 124
 125 #ifdef DEBUG
 126    brw->batch.emit = USED_BATCH(brw->batch);
 127    brw->batch.total = n;
 128 #endif
 129 }
 130
 131 static inline void
 132 intel_batchbuffer_advance(struct brw_context *brw)
 133 {
 134 #ifdef DEBUG
 135    struct intel_batchbuffer *batch = &brw->batch;
 136    unsigned int _n = USED_BATCH(*batch) - batch->emit;
 137    assert(batch->total != 0);
 138    if (_n != batch->total) {
 139       fprintf(stderr, "ADVANCE_BATCH: %d of %d dwords emitted\n",
 140               _n, batch->total);
 141       abort();
 142    }
 143    batch->total = 0;
 144 #else
 145    (void) brw;
 146 #endif
 147 }
 148
 149 #define BEGIN_BATCH(n) do {                            \
 150    intel_batchbuffer_begin(brw, (n), RENDER_RING);     \
 151    uint32_t *__map = brw->batch.map_next;              \
 152    brw->batch.map_next += (n)
 153
 154 #define BEGIN_BATCH_BLT(n) do {                        \
 155    intel_batchbuffer_begin(brw, (n), BLT_RING);        \
 156    uint32_t *__map = brw->batch.map_next;              \
 157    brw->batch.map_next += (n)
 158
 159 #define OUT_BATCH(d) *__map++ = (d)
 160 #define OUT_BATCH_F(f) OUT_BATCH(float_as_int((f)))
 161
 162 #define OUT_RELOC(buf, read_domains, write_domain, delta) do { \
 163    uint32_t __offset = (__map - brw->batch.map) * 4;           \
 164    OUT_BATCH(intel_batchbuffer_reloc(brw, (buf), __offset,     \
 165                                      (read_domains),           \
 166                                      (write_domain),           \
 167                                      (delta)));                \
 168 } while (0)
 169
 170 /* Handle 48-bit address relocations for Gen8+ */
 171 #define OUT_RELOC64(buf, read_domains, write_domain, delta) do {      \
 172    uint32_t __offset = (__map - brw->batch.map) * 4;                  \
 173    uint64_t reloc64 = intel_batchbuffer_reloc64(brw, (buf), __offset, \
 174                                                 (read_domains),       \
 175                                                 (write_domain),       \
 176                                                 (delta));             \
 177    OUT_BATCH(reloc64);                                                \
 178    OUT_BATCH(reloc64 >> 32);                                          \
 179 } while (0)
 180
 181 #define ADVANCE_BATCH()                  \
 182    assert(__map == brw->batch.map_next); \
 183    intel_batchbuffer_advance(brw);       \
 184 } while (0)
 185
 186 #ifdef __cplusplus
 187 }
 188 #endif
 189
 190 #endif