src/mesa/drivers/dri/i965/intel_batchbuffer.h

   1 #ifndef INTEL_BATCHBUFFER_H
   2 #define INTEL_BATCHBUFFER_H
   3
   4 #include "main/mtypes.h"
   5
   6 #include "brw_context.h"
   7 #include "intel_bufmgr.h"
   8 #include "intel_reg.h"
   9
  10 #ifdef __cplusplus
  11 extern "C" {
  12 #endif
  13
  14 /**
  15  * Number of bytes to reserve for commands necessary to complete a batch.
  16  *
  17  * This includes:
  18  * - MI_BATCHBUFFER_END (4 bytes)
  19  * - Optional MI_NOOP for ensuring the batch length is qword aligned (4 bytes)
  20  * - Any state emitted by vtbl->finish_batch():
  21  *   - Gen4-5 record ending occlusion query values (4 * 4 = 16 bytes)
  22  *   - Disabling OA counters on Gen6+ (3 DWords = 12 bytes)
  23  *   - Ending MI_REPORT_PERF_COUNT on Gen5+, plus associated PIPE_CONTROLs:
  24  *     - Two sets of PIPE_CONTROLs, which become 3 PIPE_CONTROLs each on SNB,
  25  *       which are 5 DWords each ==> 2 * 3 * 5 * 4 = 120 bytes
  26  *     - 3 DWords for MI_REPORT_PERF_COUNT itself on Gen6+.  ==> 12 bytes.
  27  *       On Ironlake, it's 6 DWords, but we have some slack due to the lack of
  28  *       Sandybridge PIPE_CONTROL madness.
  29  */
  30 #define BATCH_RESERVED 152
  31
  32 struct intel_batchbuffer;
  33
  34 void intel_batchbuffer_emit_render_ring_prelude(struct brw_context *brw);
  35 void intel_batchbuffer_init(struct brw_context *brw);
  36 void intel_batchbuffer_free(struct brw_context *brw);
  37 void intel_batchbuffer_save_state(struct brw_context *brw);
  38 void intel_batchbuffer_reset_to_saved(struct brw_context *brw);
  39
  40 int _intel_batchbuffer_flush(struct brw_context *brw,
  41                              const char *file, int line);
  42
  43 #define intel_batchbuffer_flush(intel) \
  44         _intel_batchbuffer_flush(intel, __FILE__, __LINE__)
  45
  46
  47
  48 /* Unlike bmBufferData, this currently requires the buffer be mapped.
  49  * Consider it a convenience function wrapping multple
  50  * intel_buffer_dword() calls.
  51  */
  52 void intel_batchbuffer_data(struct brw_context *brw,
  53                             const void *data, GLuint bytes,
  54                             enum brw_gpu_ring ring);
  55
  56 bool intel_batchbuffer_emit_reloc(struct brw_context *brw,
  57                                        drm_intel_bo *buffer,
  58                                        uint32_t read_domains,
  59                                        uint32_t write_domain,
  60                                        uint32_t offset);
  61 bool intel_batchbuffer_emit_reloc64(struct brw_context *brw,
  62                                     drm_intel_bo *buffer,
  63                                     uint32_t read_domains,
  64                                     uint32_t write_domain,
  65                                     uint32_t offset);
  66 static inline uint32_t float_as_int(float f)
  67 {
  68    union {
  69       float f;
  70       uint32_t d;
  71    } fi;
  72
  73    fi.f = f;
  74    return fi.d;
  75 }
  76
  77 /* Inline functions - might actually be better off with these
  78  * non-inlined.  Certainly better off switching all command packets to
  79  * be passed as structs rather than dwords, but that's a little bit of
  80  * work...
  81  */
  82 static inline unsigned
  83 intel_batchbuffer_space(struct brw_context *brw)
  84 {
  85    return (brw->batch.state_batch_offset - brw->batch.reserved_space)
  86       - brw->batch.used*4;
  87 }
  88
  89
  90 static inline void
  91 intel_batchbuffer_emit_dword(struct brw_context *brw, GLuint dword)
  92 {
  93 #ifdef DEBUG
  94    assert(intel_batchbuffer_space(brw) >= 4);
  95 #endif
  96    brw->batch.map[brw->batch.used++] = dword;
  97    assert(brw->batch.ring != UNKNOWN_RING);
  98 }
  99
 100 static inline void
 101 intel_batchbuffer_emit_float(struct brw_context *brw, float f)
 102 {
 103    intel_batchbuffer_emit_dword(brw, float_as_int(f));
 104 }
 105
 106 static inline void
 107 intel_batchbuffer_require_space(struct brw_context *brw, GLuint sz,
 108                                 enum brw_gpu_ring ring)
 109 {
 110    /* If we're switching rings, implicitly flush the batch. */
 111    if (unlikely(ring != brw->batch.ring) && brw->batch.ring != UNKNOWN_RING &&
 112        brw->gen >= 6) {
 113       intel_batchbuffer_flush(brw);
 114    }
 115
 116 #ifdef DEBUG
 117    assert(sz < BATCH_SZ - BATCH_RESERVED);
 118 #endif
 119    if (intel_batchbuffer_space(brw) < sz)
 120       intel_batchbuffer_flush(brw);
 121
 122    enum brw_gpu_ring prev_ring = brw->batch.ring;
 123    /* The intel_batchbuffer_flush() calls above might have changed
 124     * brw->batch.ring to UNKNOWN_RING, so we need to set it here at the end.
 125     */
 126    brw->batch.ring = ring;
 127
 128    if (unlikely(prev_ring == UNKNOWN_RING && ring == RENDER_RING))
 129       intel_batchbuffer_emit_render_ring_prelude(brw);
 130 }
 131
 132 static inline void
 133 intel_batchbuffer_begin(struct brw_context *brw, int n, enum brw_gpu_ring ring)
 134 {
 135    intel_batchbuffer_require_space(brw, n * 4, ring);
 136
 137    brw->batch.emit = brw->batch.used;
 138 #ifdef DEBUG
 139    brw->batch.total = n;
 140 #endif
 141 }
 142
 143 static inline void
 144 intel_batchbuffer_advance(struct brw_context *brw)
 145 {
 146 #ifdef DEBUG
 147    struct intel_batchbuffer *batch = &brw->batch;
 148    unsigned int _n = batch->used - batch->emit;
 149    assert(batch->total != 0);
 150    if (_n != batch->total) {
 151       fprintf(stderr, "ADVANCE_BATCH: %d of %d dwords emitted\n",
 152               _n, batch->total);
 153       abort();
 154    }
 155    batch->total = 0;
 156 #endif
 157 }
 158
 159 #define BEGIN_BATCH(n) intel_batchbuffer_begin(brw, n, RENDER_RING)
 160 #define BEGIN_BATCH_BLT(n) intel_batchbuffer_begin(brw, n, BLT_RING)
 161 #define OUT_BATCH(d) intel_batchbuffer_emit_dword(brw, d)
 162 #define OUT_BATCH_F(f) intel_batchbuffer_emit_float(brw, f)
 163 #define OUT_RELOC(buf, read_domains, write_domain, delta) do {          \
 164    intel_batchbuffer_emit_reloc(brw, buf,                       \
 165                                 read_domains, write_domain, delta);     \
 166 } while (0)
 167
 168 /* Handle 48-bit address relocations for Gen8+ */
 169 #define OUT_RELOC64(buf, read_domains, write_domain, delta) do { \
 170    intel_batchbuffer_emit_reloc64(brw, buf, read_domains, write_domain, delta); \
 171 } while (0)
 172
 173 #define ADVANCE_BATCH() intel_batchbuffer_advance(brw);
 174
 175 #ifdef __cplusplus
 176 }
 177 #endif
 178
 179 #endif