src/mesa/drivers/dri/i965/intel_batchbuffer.h

   1 #ifndef INTEL_BATCHBUFFER_H
   2 #define INTEL_BATCHBUFFER_H
   3
   4 #include "main/mtypes.h"
   5
   6 #include "brw_context.h"
   7 #include "intel_bufmgr.h"
   8 #include "intel_reg.h"
   9
  10 #ifdef __cplusplus
  11 extern "C" {
  12 #endif
  13
  14 /**
  15  * Number of bytes to reserve for commands necessary to complete a batch.
  16  *
  17  * This includes:
  18  * - MI_BATCHBUFFER_END (4 bytes)
  19  * - Optional MI_NOOP for ensuring the batch length is qword aligned (4 bytes)
  20  * - Any state emitted by vtbl->finish_batch():
  21  *   - Gen4-5 record ending occlusion query values (4 * 4 = 16 bytes)
  22  *   - Disabling OA counters on Gen6+ (3 DWords = 12 bytes)
  23  *   - Ending MI_REPORT_PERF_COUNT on Gen5+, plus associated PIPE_CONTROLs:
  24  *     - Two sets of PIPE_CONTROLs, which become 3 PIPE_CONTROLs each on SNB,
  25  *       which are 4 DWords each ==> 2 * 3 * 4 * 4 = 96 bytes
  26  *     - 3 DWords for MI_REPORT_PERF_COUNT itself on Gen6+.  ==> 12 bytes.
  27  *       On Ironlake, it's 6 DWords, but we have some slack due to the lack of
  28  *       Sandybridge PIPE_CONTROL madness.
  29  */
  30 #define BATCH_RESERVED 146
  31
  32 struct intel_batchbuffer;
  33
  34 void intel_batchbuffer_emit_render_ring_prelude(struct brw_context *brw);
  35 void intel_batchbuffer_init(struct brw_context *brw);
  36 void intel_batchbuffer_free(struct brw_context *brw);
  37 void intel_batchbuffer_save_state(struct brw_context *brw);
  38 void intel_batchbuffer_reset_to_saved(struct brw_context *brw);
  39 void intel_batchbuffer_clear_cache(struct brw_context *brw);
  40
  41 int _intel_batchbuffer_flush(struct brw_context *brw,
  42                              const char *file, int line);
  43
  44 #define intel_batchbuffer_flush(intel) \
  45         _intel_batchbuffer_flush(intel, __FILE__, __LINE__)
  46
  47
  48
  49 /* Unlike bmBufferData, this currently requires the buffer be mapped.
  50  * Consider it a convenience function wrapping multple
  51  * intel_buffer_dword() calls.
  52  */
  53 void intel_batchbuffer_data(struct brw_context *brw,
  54                             const void *data, GLuint bytes,
  55                             enum brw_gpu_ring ring);
  56
  57 bool intel_batchbuffer_emit_reloc(struct brw_context *brw,
  58                                        drm_intel_bo *buffer,
  59                                        uint32_t read_domains,
  60                                        uint32_t write_domain,
  61                                        uint32_t offset);
  62 void intel_batchbuffer_emit_mi_flush(struct brw_context *brw);
  63 void intel_emit_post_sync_nonzero_flush(struct brw_context *brw);
  64 void intel_emit_depth_stall_flushes(struct brw_context *brw);
  65 void gen7_emit_vs_workaround_flush(struct brw_context *brw);
  66 void gen7_emit_cs_stall_flush(struct brw_context *brw);
  67
  68 static inline uint32_t float_as_int(float f)
  69 {
  70    union {
  71       float f;
  72       uint32_t d;
  73    } fi;
  74
  75    fi.f = f;
  76    return fi.d;
  77 }
  78
  79 /* Inline functions - might actually be better off with these
  80  * non-inlined.  Certainly better off switching all command packets to
  81  * be passed as structs rather than dwords, but that's a little bit of
  82  * work...
  83  */
  84 static inline unsigned
  85 intel_batchbuffer_space(struct brw_context *brw)
  86 {
  87    return (brw->batch.state_batch_offset - brw->batch.reserved_space)
  88       - brw->batch.used*4;
  89 }
  90
  91
  92 static inline void
  93 intel_batchbuffer_emit_dword(struct brw_context *brw, GLuint dword)
  94 {
  95 #ifdef DEBUG
  96    assert(intel_batchbuffer_space(brw) >= 4);
  97 #endif
  98    brw->batch.map[brw->batch.used++] = dword;
  99    assert(brw->batch.ring != UNKNOWN_RING);
 100 }
 101
 102 static inline void
 103 intel_batchbuffer_emit_float(struct brw_context *brw, float f)
 104 {
 105    intel_batchbuffer_emit_dword(brw, float_as_int(f));
 106 }
 107
 108 static inline void
 109 intel_batchbuffer_require_space(struct brw_context *brw, GLuint sz,
 110                                 enum brw_gpu_ring ring)
 111 {
 112    /* If we're switching rings, implicitly flush the batch. */
 113    if (unlikely(ring != brw->batch.ring) && brw->batch.ring != UNKNOWN_RING &&
 114        brw->gen >= 6) {
 115       intel_batchbuffer_flush(brw);
 116    }
 117
 118 #ifdef DEBUG
 119    assert(sz < BATCH_SZ - BATCH_RESERVED);
 120 #endif
 121    if (intel_batchbuffer_space(brw) < sz)
 122       intel_batchbuffer_flush(brw);
 123
 124    enum brw_gpu_ring prev_ring = brw->batch.ring;
 125    /* The intel_batchbuffer_flush() calls above might have changed
 126     * brw->batch.ring to UNKNOWN_RING, so we need to set it here at the end.
 127     */
 128    brw->batch.ring = ring;
 129
 130    if (unlikely(prev_ring == UNKNOWN_RING && ring == RENDER_RING))
 131       intel_batchbuffer_emit_render_ring_prelude(brw);
 132 }
 133
 134 static inline void
 135 intel_batchbuffer_begin(struct brw_context *brw, int n, enum brw_gpu_ring ring)
 136 {
 137    intel_batchbuffer_require_space(brw, n * 4, ring);
 138
 139    brw->batch.emit = brw->batch.used;
 140 #ifdef DEBUG
 141    brw->batch.total = n;
 142 #endif
 143 }
 144
 145 static inline void
 146 intel_batchbuffer_advance(struct brw_context *brw)
 147 {
 148 #ifdef DEBUG
 149    struct intel_batchbuffer *batch = &brw->batch;
 150    unsigned int _n = batch->used - batch->emit;
 151    assert(batch->total != 0);
 152    if (_n != batch->total) {
 153       fprintf(stderr, "ADVANCE_BATCH: %d of %d dwords emitted\n",
 154               _n, batch->total);
 155       abort();
 156    }
 157    batch->total = 0;
 158 #endif
 159 }
 160
 161 #define BEGIN_BATCH(n) intel_batchbuffer_begin(brw, n, RENDER_RING)
 162 #define BEGIN_BATCH_BLT(n) intel_batchbuffer_begin(brw, n, BLT_RING)
 163 #define OUT_BATCH(d) intel_batchbuffer_emit_dword(brw, d)
 164 #define OUT_BATCH_F(f) intel_batchbuffer_emit_float(brw, f)
 165 #define OUT_RELOC(buf, read_domains, write_domain, delta) do {          \
 166    intel_batchbuffer_emit_reloc(brw, buf,                       \
 167                                 read_domains, write_domain, delta);     \
 168 } while (0)
 169
 170 #define ADVANCE_BATCH() intel_batchbuffer_advance(brw);
 171
 172 #ifdef __cplusplus
 173 }
 174 #endif
 175
 176 #endif