1 #ifndef INTEL_BATCHBUFFER_H
2 #define INTEL_BATCHBUFFER_H
4 #include "main/mtypes.h"
6 #include "brw_context.h"
7 #include "brw_bufmgr.h"
14 * Number of bytes to reserve for commands necessary to complete a batch.
17 * - MI_BATCHBUFFER_END (4 bytes)
18 * - Optional MI_NOOP for ensuring the batch length is qword aligned (4 bytes)
19 * - Any state emitted by vtbl->finish_batch():
20 * - Gen4-5 record ending occlusion query values (4 * 4 = 16 bytes)
21 * - Disabling OA counters on Gen6+ (3 DWords = 12 bytes)
22 * - Ending MI_REPORT_PERF_COUNT on Gen5+, plus associated PIPE_CONTROLs:
23 * - Two sets of PIPE_CONTROLs, which become 4 PIPE_CONTROLs each on SNB,
24 * which are 5 DWords each ==> 2 * 4 * 5 * 4 = 160 bytes
25 * - 3 DWords for MI_REPORT_PERF_COUNT itself on Gen6+. ==> 12 bytes.
26 * On Ironlake, it's 6 DWords, but we have some slack due to the lack of
27 * Sandybridge PIPE_CONTROL madness.
28 * - CC_STATE workaround on HSW (17 * 4 = 68 bytes)
29 * - 10 dwords for initial mi_flush
30 * - 2 dwords for CC state setup
31 * - 5 dwords for the required pipe control at the end
32 * - Restoring L3 configuration: (24 dwords = 96 bytes)
33 * - 2*6 dwords for two PIPE_CONTROL flushes.
34 * - 7 dwords for L3 configuration set-up.
35 * - 5 dwords for L3 atomic set-up (on HSW).
37 #define BATCH_RESERVED 308
39 struct intel_batchbuffer
;
41 void intel_batchbuffer_init(struct intel_batchbuffer
*batch
,
42 drm_bacon_bufmgr
*bufmgr
,
44 void intel_batchbuffer_free(struct intel_batchbuffer
*batch
);
45 void intel_batchbuffer_save_state(struct brw_context
*brw
);
46 void intel_batchbuffer_reset_to_saved(struct brw_context
*brw
);
47 void intel_batchbuffer_require_space(struct brw_context
*brw
, GLuint sz
,
48 enum brw_gpu_ring ring
);
49 int _intel_batchbuffer_flush_fence(struct brw_context
*brw
,
50 int in_fence_fd
, int *out_fence_fd
,
51 const char *file
, int line
);
53 #define intel_batchbuffer_flush(brw) \
54 _intel_batchbuffer_flush_fence((brw), -1, NULL, __FILE__, __LINE__)
56 #define intel_batchbuffer_flush_fence(brw, in_fence_fd, out_fence_fd) \
57 _intel_batchbuffer_flush_fence((brw), (in_fence_fd), (out_fence_fd), \
60 /* Unlike bmBufferData, this currently requires the buffer be mapped.
61 * Consider it a convenience function wrapping multple
62 * intel_buffer_dword() calls.
64 void intel_batchbuffer_data(struct brw_context
*brw
,
65 const void *data
, GLuint bytes
,
66 enum brw_gpu_ring ring
);
68 bool brw_batch_references(struct intel_batchbuffer
*batch
, drm_bacon_bo
*bo
);
70 uint64_t brw_emit_reloc(struct intel_batchbuffer
*batch
, uint32_t batch_offset
,
71 drm_bacon_bo
*target
, uint32_t target_offset
,
72 uint32_t read_domains
, uint32_t write_domain
);
74 static inline uint32_t
75 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
79 /* Using state base address. */
83 brw_emit_reloc(&brw
->batch
, state_offset
, brw
->cache
.bo
, prog_offset
,
84 I915_GEM_DOMAIN_INSTRUCTION
, 0);
86 return brw
->cache
.bo
->offset64
+ prog_offset
;
89 #define USED_BATCH(batch) ((uintptr_t)((batch).map_next - (batch).map))
91 static inline uint32_t float_as_int(float f
)
102 /* Inline functions - might actually be better off with these
103 * non-inlined. Certainly better off switching all command packets to
104 * be passed as structs rather than dwords, but that's a little bit of
107 static inline unsigned
108 intel_batchbuffer_space(struct intel_batchbuffer
*batch
)
110 return (batch
->state_batch_offset
- batch
->reserved_space
)
111 - USED_BATCH(*batch
) * 4;
116 intel_batchbuffer_emit_dword(struct intel_batchbuffer
*batch
, GLuint dword
)
119 assert(intel_batchbuffer_space(batch
) >= 4);
121 *batch
->map_next
++ = dword
;
122 assert(batch
->ring
!= UNKNOWN_RING
);
126 intel_batchbuffer_emit_float(struct intel_batchbuffer
*batch
, float f
)
128 intel_batchbuffer_emit_dword(batch
, float_as_int(f
));
132 intel_batchbuffer_begin(struct brw_context
*brw
, int n
, enum brw_gpu_ring ring
)
134 intel_batchbuffer_require_space(brw
, n
* 4, ring
);
137 brw
->batch
.emit
= USED_BATCH(brw
->batch
);
138 brw
->batch
.total
= n
;
143 intel_batchbuffer_advance(struct brw_context
*brw
)
146 struct intel_batchbuffer
*batch
= &brw
->batch
;
147 unsigned int _n
= USED_BATCH(*batch
) - batch
->emit
;
148 assert(batch
->total
!= 0);
149 if (_n
!= batch
->total
) {
150 fprintf(stderr
, "ADVANCE_BATCH: %d of %d dwords emitted\n",
160 #define BEGIN_BATCH(n) do { \
161 intel_batchbuffer_begin(brw, (n), RENDER_RING); \
162 uint32_t *__map = brw->batch.map_next; \
163 brw->batch.map_next += (n)
165 #define BEGIN_BATCH_BLT(n) do { \
166 intel_batchbuffer_begin(brw, (n), BLT_RING); \
167 uint32_t *__map = brw->batch.map_next; \
168 brw->batch.map_next += (n)
170 #define OUT_BATCH(d) *__map++ = (d)
171 #define OUT_BATCH_F(f) OUT_BATCH(float_as_int((f)))
173 #define OUT_RELOC(buf, read_domains, write_domain, delta) do { \
174 uint32_t __offset = (__map - brw->batch.map) * 4; \
176 brw_emit_reloc(&brw->batch, __offset, (buf), (delta), \
177 (read_domains), (write_domain)); \
181 /* Handle 48-bit address relocations for Gen8+ */
182 #define OUT_RELOC64(buf, read_domains, write_domain, delta) do { \
183 uint32_t __offset = (__map - brw->batch.map) * 4; \
185 brw_emit_reloc(&brw->batch, __offset, (buf), (delta), \
186 (read_domains), (write_domain)); \
187 OUT_BATCH(reloc64); \
188 OUT_BATCH(reloc64 >> 32); \
191 #define ADVANCE_BATCH() \
192 assert(__map == brw->batch.map_next); \
193 intel_batchbuffer_advance(brw); \