i965: Start and stop OA counters as necessary.
[mesa.git] / src / mesa / drivers / dri / i965 / intel_batchbuffer.h
1 #ifndef INTEL_BATCHBUFFER_H
2 #define INTEL_BATCHBUFFER_H
3
4 #include "main/mtypes.h"
5
6 #include "brw_context.h"
7 #include "intel_bufmgr.h"
8 #include "intel_reg.h"
9
10 #ifdef __cplusplus
11 extern "C" {
12 #endif
13
14 /**
15 * Number of bytes to reserve for commands necessary to complete a batch.
16 *
17 * This includes:
18 * - MI_BATCHBUFFER_END (4 bytes)
19 * - Optional MI_NOOP for ensuring the batch length is qword aligned (4 bytes)
20 * - Any state emitted by vtbl->finish_batch():
21 * - Gen4-5 record ending occlusion query values (4 * 4 = 16 bytes)
22 * - Disabling OA counters on Gen6+ (3 DWords = 12 bytes)
23 */
24 #define BATCH_RESERVED 36
25
26 struct intel_batchbuffer;
27
28 void intel_batchbuffer_emit_render_ring_prelude(struct brw_context *brw);
29 void intel_batchbuffer_init(struct brw_context *brw);
30 void intel_batchbuffer_free(struct brw_context *brw);
31 void intel_batchbuffer_save_state(struct brw_context *brw);
32 void intel_batchbuffer_reset_to_saved(struct brw_context *brw);
33 void intel_batchbuffer_clear_cache(struct brw_context *brw);
34
35 int _intel_batchbuffer_flush(struct brw_context *brw,
36 const char *file, int line);
37
38 #define intel_batchbuffer_flush(intel) \
39 _intel_batchbuffer_flush(intel, __FILE__, __LINE__)
40
41
42
43 /* Unlike bmBufferData, this currently requires the buffer be mapped.
44 * Consider it a convenience function wrapping multple
45 * intel_buffer_dword() calls.
46 */
47 void intel_batchbuffer_data(struct brw_context *brw,
48 const void *data, GLuint bytes,
49 enum brw_gpu_ring ring);
50
51 bool intel_batchbuffer_emit_reloc(struct brw_context *brw,
52 drm_intel_bo *buffer,
53 uint32_t read_domains,
54 uint32_t write_domain,
55 uint32_t offset);
56 bool intel_batchbuffer_emit_reloc_fenced(struct brw_context *brw,
57 drm_intel_bo *buffer,
58 uint32_t read_domains,
59 uint32_t write_domain,
60 uint32_t offset);
61 void intel_batchbuffer_emit_mi_flush(struct brw_context *brw);
62 void intel_emit_post_sync_nonzero_flush(struct brw_context *brw);
63 void intel_emit_depth_stall_flushes(struct brw_context *brw);
64 void gen7_emit_vs_workaround_flush(struct brw_context *brw);
65 void gen7_emit_cs_stall_flush(struct brw_context *brw);
66
67 static INLINE uint32_t float_as_int(float f)
68 {
69 union {
70 float f;
71 uint32_t d;
72 } fi;
73
74 fi.f = f;
75 return fi.d;
76 }
77
78 /* Inline functions - might actually be better off with these
79 * non-inlined. Certainly better off switching all command packets to
80 * be passed as structs rather than dwords, but that's a little bit of
81 * work...
82 */
83 static INLINE unsigned
84 intel_batchbuffer_space(struct brw_context *brw)
85 {
86 return (brw->batch.state_batch_offset - brw->batch.reserved_space)
87 - brw->batch.used*4;
88 }
89
90
91 static INLINE void
92 intel_batchbuffer_emit_dword(struct brw_context *brw, GLuint dword)
93 {
94 #ifdef DEBUG
95 assert(intel_batchbuffer_space(brw) >= 4);
96 #endif
97 brw->batch.map[brw->batch.used++] = dword;
98 assert(brw->batch.ring != UNKNOWN_RING);
99 }
100
101 static INLINE void
102 intel_batchbuffer_emit_float(struct brw_context *brw, float f)
103 {
104 intel_batchbuffer_emit_dword(brw, float_as_int(f));
105 }
106
107 static INLINE void
108 intel_batchbuffer_require_space(struct brw_context *brw, GLuint sz,
109 enum brw_gpu_ring ring)
110 {
111 /* If we're switching rings, implicitly flush the batch. */
112 if (unlikely(ring != brw->batch.ring) && brw->batch.ring != UNKNOWN_RING &&
113 brw->gen >= 6) {
114 intel_batchbuffer_flush(brw);
115 }
116
117 #ifdef DEBUG
118 assert(sz < BATCH_SZ - BATCH_RESERVED);
119 #endif
120 if (intel_batchbuffer_space(brw) < sz)
121 intel_batchbuffer_flush(brw);
122
123 enum brw_gpu_ring prev_ring = brw->batch.ring;
124 /* The intel_batchbuffer_flush() calls above might have changed
125 * brw->batch.ring to UNKNOWN_RING, so we need to set it here at the end.
126 */
127 brw->batch.ring = ring;
128
129 if (unlikely(prev_ring == UNKNOWN_RING && ring == RENDER_RING))
130 intel_batchbuffer_emit_render_ring_prelude(brw);
131 }
132
133 static INLINE void
134 intel_batchbuffer_begin(struct brw_context *brw, int n, enum brw_gpu_ring ring)
135 {
136 intel_batchbuffer_require_space(brw, n * 4, ring);
137
138 brw->batch.emit = brw->batch.used;
139 #ifdef DEBUG
140 brw->batch.total = n;
141 #endif
142 }
143
144 static INLINE void
145 intel_batchbuffer_advance(struct brw_context *brw)
146 {
147 #ifdef DEBUG
148 struct intel_batchbuffer *batch = &brw->batch;
149 unsigned int _n = batch->used - batch->emit;
150 assert(batch->total != 0);
151 if (_n != batch->total) {
152 fprintf(stderr, "ADVANCE_BATCH: %d of %d dwords emitted\n",
153 _n, batch->total);
154 abort();
155 }
156 batch->total = 0;
157 #endif
158 }
159
160 void intel_batchbuffer_cached_advance(struct brw_context *brw);
161
162 #define BEGIN_BATCH(n) intel_batchbuffer_begin(brw, n, RENDER_RING)
163 #define BEGIN_BATCH_BLT(n) intel_batchbuffer_begin(brw, n, BLT_RING)
164 #define OUT_BATCH(d) intel_batchbuffer_emit_dword(brw, d)
165 #define OUT_BATCH_F(f) intel_batchbuffer_emit_float(brw, f)
166 #define OUT_RELOC(buf, read_domains, write_domain, delta) do { \
167 intel_batchbuffer_emit_reloc(brw, buf, \
168 read_domains, write_domain, delta); \
169 } while (0)
170 #define OUT_RELOC_FENCED(buf, read_domains, write_domain, delta) do { \
171 intel_batchbuffer_emit_reloc_fenced(brw, buf, \
172 read_domains, write_domain, delta); \
173 } while (0)
174
175 #define ADVANCE_BATCH() intel_batchbuffer_advance(brw);
176 #define CACHED_BATCH() intel_batchbuffer_cached_advance(brw);
177
178 #ifdef __cplusplus
179 }
180 #endif
181
182 #endif