1 /**************************************************************************
3 * Copyright 2003 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include "main/mtypes.h"
30 #include "main/blit.h"
31 #include "main/context.h"
32 #include "main/enums.h"
33 #include "main/colormac.h"
34 #include "main/fbobject.h"
36 #include "brw_context.h"
37 #include "brw_defines.h"
38 #include "intel_blit.h"
39 #include "intel_buffers.h"
40 #include "intel_fbo.h"
41 #include "intel_reg.h"
42 #include "intel_batchbuffer.h"
43 #include "intel_mipmap_tree.h"
45 #define FILE_DEBUG_FLAG DEBUG_BLIT
47 #define SET_TILING_XY_FAST_COPY_BLT(tiling, tr_mode, type) \
51 CMD |= type ## _TILED_X; \
54 if (tr_mode == INTEL_MIPTREE_TRMODE_YS) \
55 CMD |= type ## _TILED_64K; \
57 CMD |= type ## _TILED_Y; \
60 unreachable("not reached"); \
65 intel_miptree_set_alpha_to_one(struct brw_context
*brw
,
66 struct intel_mipmap_tree
*mt
,
67 int x
, int y
, int width
, int height
);
69 static GLuint
translate_raster_op(GLenum logicop
)
72 case GL_CLEAR
: return 0x00;
73 case GL_AND
: return 0x88;
74 case GL_AND_REVERSE
: return 0x44;
75 case GL_COPY
: return 0xCC;
76 case GL_AND_INVERTED
: return 0x22;
77 case GL_NOOP
: return 0xAA;
78 case GL_XOR
: return 0x66;
79 case GL_OR
: return 0xEE;
80 case GL_NOR
: return 0x11;
81 case GL_EQUIV
: return 0x99;
82 case GL_INVERT
: return 0x55;
83 case GL_OR_REVERSE
: return 0xDD;
84 case GL_COPY_INVERTED
: return 0x33;
85 case GL_OR_INVERTED
: return 0xBB;
86 case GL_NAND
: return 0x77;
87 case GL_SET
: return 0xFF;
107 unreachable("not reached");
112 get_tr_horizontal_align(uint32_t tr_mode
, uint32_t cpp
, bool is_src
) {
113 /* Alignment tables for YF/YS tiled surfaces. */
114 const uint32_t align_2d_yf
[] = {64, 64, 32, 32, 16};
115 const uint32_t bpp
= cpp
* 8;
116 const uint32_t shift
= is_src
? 17 : 10;
120 if (tr_mode
== INTEL_MIPTREE_TRMODE_NONE
)
123 /* Compute array index. */
124 assert (bpp
>= 8 && bpp
<= 128 && is_power_of_two(bpp
));
125 i
= ffs(bpp
/ 8) - 1;
127 align
= tr_mode
== INTEL_MIPTREE_TRMODE_YF
?
131 assert(is_power_of_two(align
));
133 /* XY_FAST_COPY_BLT doesn't support horizontal alignment of 16. */
137 return (ffs(align
) - 6) << shift
;
141 get_tr_vertical_align(uint32_t tr_mode
, uint32_t cpp
, bool is_src
) {
142 /* Vertical alignment tables for YF/YS tiled surfaces. */
143 const unsigned align_2d_yf
[] = {64, 32, 32, 16, 16};
144 const uint32_t bpp
= cpp
* 8;
145 const uint32_t shift
= is_src
? 15 : 8;
149 if (tr_mode
== INTEL_MIPTREE_TRMODE_NONE
)
152 /* Compute array index. */
153 assert (bpp
>= 8 && bpp
<= 128 && is_power_of_two(bpp
));
154 i
= ffs(bpp
/ 8) - 1;
156 align
= tr_mode
== INTEL_MIPTREE_TRMODE_YF
?
160 assert(is_power_of_two(align
));
162 /* XY_FAST_COPY_BLT doesn't support vertical alignments of 16 and 32. */
163 if (align
== 16 || align
== 32)
166 return (ffs(align
) - 7) << shift
;
170 * Emits the packet for switching the blitter from X to Y tiled or back.
172 * This has to be called in a single BEGIN_BATCH_BLT_TILED() /
173 * ADVANCE_BATCH_TILED(). This is because BCS_SWCTRL is saved and restored as
174 * part of the power context, not a render context, and if the batchbuffer was
175 * to get flushed between setting and blitting, or blitting and restoring, our
176 * tiling state would leak into other unsuspecting applications (like the X
180 set_blitter_tiling(struct brw_context
*brw
,
181 bool dst_y_tiled
, bool src_y_tiled
,
184 assert(brw
->gen
>= 6);
186 /* Idle the blitter before we update how tiling is interpreted. */
187 OUT_BATCH(MI_FLUSH_DW
);
192 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
193 OUT_BATCH(BCS_SWCTRL
);
194 OUT_BATCH((BCS_SWCTRL_DST_Y
| BCS_SWCTRL_SRC_Y
) << 16 |
195 (dst_y_tiled
? BCS_SWCTRL_DST_Y
: 0) |
196 (src_y_tiled
? BCS_SWCTRL_SRC_Y
: 0));
199 #define SET_BLITTER_TILING(...) __map = set_blitter_tiling(__VA_ARGS__, __map)
201 #define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled) \
202 BEGIN_BATCH_BLT(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0)); \
203 if (dst_y_tiled || src_y_tiled) \
204 SET_BLITTER_TILING(brw, dst_y_tiled, src_y_tiled)
206 #define ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled) \
207 if (dst_y_tiled || src_y_tiled) \
208 SET_BLITTER_TILING(brw, false, false); \
212 blt_pitch(struct intel_mipmap_tree
*mt
)
214 int pitch
= mt
->pitch
;
221 intel_miptree_blit_compatible_formats(mesa_format src
, mesa_format dst
)
223 /* The BLT doesn't handle sRGB conversion */
224 assert(src
== _mesa_get_srgb_format_linear(src
));
225 assert(dst
== _mesa_get_srgb_format_linear(dst
));
227 /* No swizzle or format conversions possible, except... */
231 /* ...we can either discard the alpha channel when going from A->X,
232 * or we can fill the alpha channel with 0xff when going from X->A
234 if (src
== MESA_FORMAT_B8G8R8A8_UNORM
|| src
== MESA_FORMAT_B8G8R8X8_UNORM
)
235 return (dst
== MESA_FORMAT_B8G8R8A8_UNORM
||
236 dst
== MESA_FORMAT_B8G8R8X8_UNORM
);
238 if (src
== MESA_FORMAT_R8G8B8A8_UNORM
|| src
== MESA_FORMAT_R8G8B8X8_UNORM
)
239 return (dst
== MESA_FORMAT_R8G8B8A8_UNORM
||
240 dst
== MESA_FORMAT_R8G8B8X8_UNORM
);
246 * Implements a rectangular block transfer (blit) of pixels between two
249 * Our blitter can operate on 1, 2, or 4-byte-per-pixel data, with generous,
250 * but limited, pitches and sizes allowed.
252 * The src/dst coordinates are relative to the given level/slice of the
255 * If @src_flip or @dst_flip is set, then the rectangle within that miptree
256 * will be inverted (including scanline order) when copying. This is common
257 * in GL when copying between window system and user-created
258 * renderbuffers/textures.
261 intel_miptree_blit(struct brw_context
*brw
,
262 struct intel_mipmap_tree
*src_mt
,
263 int src_level
, int src_slice
,
264 uint32_t src_x
, uint32_t src_y
, bool src_flip
,
265 struct intel_mipmap_tree
*dst_mt
,
266 int dst_level
, int dst_slice
,
267 uint32_t dst_x
, uint32_t dst_y
, bool dst_flip
,
268 uint32_t width
, uint32_t height
,
271 /* The blitter doesn't understand multisampling at all. */
272 if (src_mt
->num_samples
> 0 || dst_mt
->num_samples
> 0)
275 /* No sRGB decode or encode is done by the hardware blitter, which is
276 * consistent with what we want in the callers (glCopyTexSubImage(),
277 * glBlitFramebuffer(), texture validation, etc.).
279 mesa_format src_format
= _mesa_get_srgb_format_linear(src_mt
->format
);
280 mesa_format dst_format
= _mesa_get_srgb_format_linear(dst_mt
->format
);
282 /* The blitter doesn't support doing any format conversions. We do also
283 * support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into
284 * the X channel don't matter), and XRGB8888 to ARGB8888 by setting the A
285 * channel to 1.0 at the end.
287 if (!intel_miptree_blit_compatible_formats(src_format
, dst_format
)) {
288 perf_debug("%s: Can't use hardware blitter from %s to %s, "
289 "falling back.\n", __func__
,
290 _mesa_get_format_name(src_format
),
291 _mesa_get_format_name(dst_format
));
295 /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
296 * Data Size Limitations):
298 * The BLT engine is capable of transferring very large quantities of
299 * graphics data. Any graphics data read from and written to the
300 * destination is permitted to represent a number of pixels that
301 * occupies up to 65,536 scan lines and up to 32,768 bytes per scan line
302 * at the destination. The maximum number of pixels that may be
303 * represented per scan line’s worth of graphics data depends on the
306 * Furthermore, intelEmitCopyBlit (which is called below) uses a signed
307 * 16-bit integer to represent buffer pitch, so it can only handle buffer
308 * pitches < 32k. However, the pitch is measured in bytes for linear buffers
309 * and dwords for tiled buffers.
311 * As a result of these two limitations, we can only use the blitter to do
312 * this copy when the miptree's pitch is less than 32k linear or 128k tiled.
314 if (blt_pitch(src_mt
) >= 32768 || blt_pitch(dst_mt
) >= 32768) {
315 perf_debug("Falling back due to >= 32k/128k pitch\n");
319 /* The blitter has no idea about HiZ or fast color clears, so we need to
320 * resolve the miptrees before we do anything.
322 intel_miptree_slice_resolve_depth(brw
, src_mt
, src_level
, src_slice
);
323 intel_miptree_slice_resolve_depth(brw
, dst_mt
, dst_level
, dst_slice
);
324 intel_miptree_resolve_color(brw
, src_mt
);
325 intel_miptree_resolve_color(brw
, dst_mt
);
328 src_y
= minify(src_mt
->physical_height0
, src_level
- src_mt
->first_level
) - src_y
- height
;
331 dst_y
= minify(dst_mt
->physical_height0
, dst_level
- dst_mt
->first_level
) - dst_y
- height
;
333 int src_pitch
= src_mt
->pitch
;
334 if (src_flip
!= dst_flip
)
335 src_pitch
= -src_pitch
;
337 uint32_t src_image_x
, src_image_y
, dst_image_x
, dst_image_y
;
338 intel_miptree_get_image_offset(src_mt
, src_level
, src_slice
,
339 &src_image_x
, &src_image_y
);
340 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_slice
,
341 &dst_image_x
, &dst_image_y
);
342 src_x
+= src_image_x
;
343 src_y
+= src_image_y
;
344 dst_x
+= dst_image_x
;
345 dst_y
+= dst_image_y
;
347 /* The blitter interprets the 16-bit destination x/y as a signed 16-bit
348 * value. The values we're working with are unsigned, so make sure we don't
351 if (src_x
>= 32768 || src_y
>= 32768 || dst_x
>= 32768 || dst_y
>= 32768) {
352 perf_debug("Falling back due to >=32k offset [src(%d, %d) dst(%d, %d)]\n",
353 src_x
, src_y
, dst_x
, dst_y
);
357 if (!intelEmitCopyBlit(brw
,
360 src_mt
->bo
, src_mt
->offset
,
364 dst_mt
->bo
, dst_mt
->offset
,
374 /* XXX This could be done in a single pass using XY_FULL_MONO_PATTERN_BLT */
375 if (_mesa_get_format_bits(src_format
, GL_ALPHA_BITS
) == 0 &&
376 _mesa_get_format_bits(dst_format
, GL_ALPHA_BITS
) > 0) {
377 intel_miptree_set_alpha_to_one(brw
, dst_mt
,
386 alignment_valid(struct brw_context
*brw
, unsigned offset
, uint32_t tiling
)
388 /* Tiled buffers must be page-aligned (4K). */
389 if (tiling
!= I915_TILING_NONE
)
390 return (offset
& 4095) == 0;
392 /* On Gen8+, linear buffers must be cacheline-aligned. */
394 return (offset
& 63) == 0;
400 can_fast_copy_blit(struct brw_context
*brw
,
401 drm_intel_bo
*src_buffer
,
402 int16_t src_x
, int16_t src_y
,
403 uintptr_t src_offset
, uint32_t src_pitch
,
404 uint32_t src_tiling
, uint32_t src_tr_mode
,
405 drm_intel_bo
*dst_buffer
,
406 int16_t dst_x
, int16_t dst_y
,
407 uintptr_t dst_offset
, uint32_t dst_pitch
,
408 uint32_t dst_tiling
, uint32_t dst_tr_mode
,
409 int16_t w
, int16_t h
, uint32_t cpp
)
411 const bool dst_tiling_none
= dst_tiling
== I915_TILING_NONE
;
412 const bool src_tiling_none
= src_tiling
== I915_TILING_NONE
;
417 if (src_buffer
->handle
== dst_buffer
->handle
&&
418 _mesa_regions_overlap(src_x
, src_y
, src_x
+ w
, src_y
+ h
,
419 dst_x
, dst_y
, dst_x
+ w
, dst_y
+ h
))
422 /* Enable fast copy blit only if the surfaces are Yf/Ys tiled.
423 * FIXME: Based on performance data, remove this condition later to
424 * enable for all types of surfaces.
426 if (src_tr_mode
== INTEL_MIPTREE_TRMODE_NONE
&&
427 dst_tr_mode
== INTEL_MIPTREE_TRMODE_NONE
)
430 /* For all surface types buffers must be cacheline-aligned. */
431 if ((dst_offset
| src_offset
) & 63)
434 /* Color depth greater than 128 bits not supported. */
438 /* For Fast Copy Blits the pitch cannot be a negative number. So, bit 15
439 * of the destination pitch must be zero.
441 if ((src_pitch
>> 15 & 1) != 0 || (dst_pitch
>> 15 & 1) != 0)
444 /* For Linear surfaces, the pitch has to be an OWord (16byte) multiple. */
445 if ((src_tiling_none
&& src_pitch
% 16 != 0) ||
446 (dst_tiling_none
&& dst_pitch
% 16 != 0))
449 /* For Tiled surfaces, the pitch has to be a multiple of the Tile width
450 * (X direction width of the Tile). This means the pitch value will
451 * always be Cache Line aligned (64byte multiple).
453 if ((!dst_tiling_none
&& dst_pitch
% 64 != 0) ||
454 (!src_tiling_none
&& src_pitch
% 64 != 0))
461 xy_blit_cmd(uint32_t src_tiling
, uint32_t src_tr_mode
,
462 uint32_t dst_tiling
, uint32_t dst_tr_mode
,
463 uint32_t cpp
, bool use_fast_copy_blit
)
467 if (use_fast_copy_blit
) {
468 CMD
= XY_FAST_COPY_BLT_CMD
;
470 if (dst_tiling
!= I915_TILING_NONE
)
471 SET_TILING_XY_FAST_COPY_BLT(dst_tiling
, dst_tr_mode
, XY_FAST_DST
);
473 if (src_tiling
!= I915_TILING_NONE
)
474 SET_TILING_XY_FAST_COPY_BLT(src_tiling
, src_tr_mode
, XY_FAST_SRC
);
476 CMD
|= get_tr_horizontal_align(src_tr_mode
, cpp
, true /* is_src */);
477 CMD
|= get_tr_vertical_align(src_tr_mode
, cpp
, true /* is_src */);
479 CMD
|= get_tr_horizontal_align(dst_tr_mode
, cpp
, false /* is_src */);
480 CMD
|= get_tr_vertical_align(dst_tr_mode
, cpp
, false /* is_src */);
487 CMD
= XY_SRC_COPY_BLT_CMD
;
490 CMD
= XY_SRC_COPY_BLT_CMD
| XY_BLT_WRITE_ALPHA
| XY_BLT_WRITE_RGB
;
493 unreachable("not reached");
496 if (dst_tiling
!= I915_TILING_NONE
)
499 if (src_tiling
!= I915_TILING_NONE
)
508 intelEmitCopyBlit(struct brw_context
*brw
,
511 drm_intel_bo
*src_buffer
,
514 uint32_t src_tr_mode
,
516 drm_intel_bo
*dst_buffer
,
519 uint32_t dst_tr_mode
,
520 GLshort src_x
, GLshort src_y
,
521 GLshort dst_x
, GLshort dst_y
,
522 GLshort w
, GLshort h
,
525 GLuint CMD
, BR13
, pass
= 0;
526 int dst_y2
= dst_y
+ h
;
527 int dst_x2
= dst_x
+ w
;
528 drm_intel_bo
*aper_array
[3];
529 bool dst_y_tiled
= dst_tiling
== I915_TILING_Y
;
530 bool src_y_tiled
= src_tiling
== I915_TILING_Y
;
531 bool use_fast_copy_blit
= false;
533 if ((dst_y_tiled
|| src_y_tiled
) && brw
->gen
< 6)
536 /* do space check before going any further */
538 aper_array
[0] = brw
->batch
.bo
;
539 aper_array
[1] = dst_buffer
;
540 aper_array
[2] = src_buffer
;
542 if (dri_bufmgr_check_aperture_space(aper_array
, 3) != 0) {
543 intel_batchbuffer_flush(brw
);
552 unsigned length
= brw
->gen
>= 8 ? 10 : 8;
554 intel_batchbuffer_require_space(brw
, length
* 4, BLT_RING
);
555 DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
557 src_buffer
, src_pitch
, src_offset
, src_x
, src_y
,
558 dst_buffer
, dst_pitch
, dst_offset
, dst_x
, dst_y
, w
, h
);
560 use_fast_copy_blit
= can_fast_copy_blit(brw
,
563 src_offset
, src_pitch
,
564 src_tiling
, src_tr_mode
,
567 dst_offset
, dst_pitch
,
568 dst_tiling
, dst_tr_mode
,
570 assert(use_fast_copy_blit
||
571 (src_tr_mode
== INTEL_MIPTREE_TRMODE_NONE
&&
572 dst_tr_mode
== INTEL_MIPTREE_TRMODE_NONE
));
574 if (use_fast_copy_blit
) {
575 /* When two sequential fast copy blits have different source surfaces,
576 * but their destinations refer to the same destination surfaces and
577 * therefore destinations overlap it is imperative that a flush be
578 * inserted between the two blits.
580 * FIXME: Figure out a way to avoid flushing when not required.
582 brw_emit_mi_flush(brw
);
585 BR13
= br13_for_cpp(cpp
);
587 if (src_tr_mode
== INTEL_MIPTREE_TRMODE_YF
)
588 BR13
|= XY_FAST_SRC_TRMODE_YF
;
590 if (dst_tr_mode
== INTEL_MIPTREE_TRMODE_YF
)
591 BR13
|= XY_FAST_DST_TRMODE_YF
;
593 CMD
= xy_blit_cmd(src_tiling
, src_tr_mode
,
594 dst_tiling
, dst_tr_mode
,
595 cpp
, use_fast_copy_blit
);
597 /* For tiled source and destination, pitch value should be specified
598 * as a number of Dwords.
600 if (dst_tiling
!= I915_TILING_NONE
)
603 if (src_tiling
!= I915_TILING_NONE
)
607 assert(!dst_y_tiled
|| (dst_pitch
% 128) == 0);
608 assert(!src_y_tiled
|| (src_pitch
% 128) == 0);
610 /* For big formats (such as floating point), do the copy using 16 or
611 * 32bpp and multiply the coordinates.
620 assert(cpp
% 4 == 0);
628 if (!alignment_valid(brw
, dst_offset
, dst_tiling
))
630 if (!alignment_valid(brw
, src_offset
, src_tiling
))
633 /* Blit pitch must be dword-aligned. Otherwise, the hardware appears to drop
634 * the low bits. Offsets must be naturally aligned.
636 if (src_pitch
% 4 != 0 || src_offset
% cpp
!= 0 ||
637 dst_pitch
% 4 != 0 || dst_offset
% cpp
!= 0)
641 BR13
= br13_for_cpp(cpp
) | translate_raster_op(logic_op
) << 16;
643 CMD
= xy_blit_cmd(src_tiling
, src_tr_mode
,
644 dst_tiling
, dst_tr_mode
,
645 cpp
, use_fast_copy_blit
);
647 if (dst_tiling
!= I915_TILING_NONE
)
650 if (src_tiling
!= I915_TILING_NONE
)
654 if (dst_y2
<= dst_y
|| dst_x2
<= dst_x
) {
658 assert(dst_x
< dst_x2
);
659 assert(dst_y
< dst_y2
);
660 assert(src_offset
+ (src_y
+ h
- 1) * abs(src_pitch
) +
661 (w
* cpp
) <= src_buffer
->size
);
662 assert(dst_offset
+ (dst_y
+ h
- 1) * abs(dst_pitch
) +
663 (w
* cpp
) <= dst_buffer
->size
);
665 BEGIN_BATCH_BLT_TILED(length
, dst_y_tiled
, src_y_tiled
);
666 OUT_BATCH(CMD
| (length
- 2));
667 OUT_BATCH(BR13
| (uint16_t)dst_pitch
);
668 OUT_BATCH(SET_FIELD(dst_y
, BLT_Y
) | SET_FIELD(dst_x
, BLT_X
));
669 OUT_BATCH(SET_FIELD(dst_y2
, BLT_Y
) | SET_FIELD(dst_x2
, BLT_X
));
671 OUT_RELOC64(dst_buffer
,
672 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
675 OUT_RELOC(dst_buffer
,
676 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
679 OUT_BATCH(SET_FIELD(src_y
, BLT_Y
) | SET_FIELD(src_x
, BLT_X
));
680 OUT_BATCH((uint16_t)src_pitch
);
682 OUT_RELOC64(src_buffer
,
683 I915_GEM_DOMAIN_RENDER
, 0,
686 OUT_RELOC(src_buffer
,
687 I915_GEM_DOMAIN_RENDER
, 0,
691 ADVANCE_BATCH_TILED(dst_y_tiled
, src_y_tiled
);
693 brw_emit_mi_flush(brw
);
699 intelEmitImmediateColorExpandBlit(struct brw_context
*brw
,
701 GLubyte
*src_bits
, GLuint src_size
,
704 drm_intel_bo
*dst_buffer
,
707 GLshort x
, GLshort y
,
708 GLshort w
, GLshort h
,
711 int dwords
= ALIGN(src_size
, 8) / 4;
712 uint32_t opcode
, br13
, blit_cmd
;
714 if (dst_tiling
!= I915_TILING_NONE
) {
715 if (dst_offset
& 4095)
717 if (dst_tiling
== I915_TILING_Y
)
721 assert((logic_op
>= GL_CLEAR
) && (logic_op
<= (GL_CLEAR
+ 0x0f)));
722 assert(dst_pitch
> 0);
727 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
729 dst_buffer
, dst_pitch
, dst_offset
, x
, y
, w
, h
, src_size
, dwords
);
731 unsigned xy_setup_blt_length
= brw
->gen
>= 8 ? 10 : 8;
732 intel_batchbuffer_require_space(brw
, (xy_setup_blt_length
* 4) +
733 (3 * 4) + dwords
* 4, BLT_RING
);
735 opcode
= XY_SETUP_BLT_CMD
;
737 opcode
|= XY_BLT_WRITE_ALPHA
| XY_BLT_WRITE_RGB
;
738 if (dst_tiling
!= I915_TILING_NONE
) {
739 opcode
|= XY_DST_TILED
;
743 br13
= dst_pitch
| (translate_raster_op(logic_op
) << 16) | (1 << 29);
744 br13
|= br13_for_cpp(cpp
);
746 blit_cmd
= XY_TEXT_IMMEDIATE_BLIT_CMD
| XY_TEXT_BYTE_PACKED
; /* packing? */
747 if (dst_tiling
!= I915_TILING_NONE
)
748 blit_cmd
|= XY_DST_TILED
;
750 BEGIN_BATCH_BLT(xy_setup_blt_length
+ 3);
751 OUT_BATCH(opcode
| (xy_setup_blt_length
- 2));
753 OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
754 OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
756 OUT_RELOC64(dst_buffer
,
757 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
760 OUT_RELOC(dst_buffer
,
761 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
764 OUT_BATCH(0); /* bg */
765 OUT_BATCH(fg_color
); /* fg */
766 OUT_BATCH(0); /* pattern base addr */
770 OUT_BATCH(blit_cmd
| ((3 - 2) + dwords
));
771 OUT_BATCH(SET_FIELD(y
, BLT_Y
) | SET_FIELD(x
, BLT_X
));
772 OUT_BATCH(SET_FIELD(y
+ h
, BLT_Y
) | SET_FIELD(x
+ w
, BLT_X
));
775 intel_batchbuffer_data(brw
, src_bits
, dwords
* 4, BLT_RING
);
777 brw_emit_mi_flush(brw
);
782 /* We don't have a memmove-type blit like some other hardware, so we'll do a
783 * rectangular blit covering a large space, then emit 1-scanline blit at the
784 * end to cover the last if we need.
787 intel_emit_linear_blit(struct brw_context
*brw
,
788 drm_intel_bo
*dst_bo
,
789 unsigned int dst_offset
,
790 drm_intel_bo
*src_bo
,
791 unsigned int src_offset
,
794 struct gl_context
*ctx
= &brw
->ctx
;
795 GLuint pitch
, height
;
796 int16_t src_x
, dst_x
;
799 /* The pitch given to the GPU must be DWORD aligned, and
800 * we want width to match pitch. Max width is (1 << 15 - 1),
801 * rounding that down to the nearest DWORD is 1 << 15 - 4
803 pitch
= ROUND_DOWN_TO(MIN2(size
, (1 << 15) - 1), 4);
804 height
= (pitch
== 0) ? 1 : size
/ pitch
;
805 src_x
= src_offset
% 64;
806 dst_x
= dst_offset
% 64;
807 ok
= intelEmitCopyBlit(brw
, 1,
808 pitch
, src_bo
, src_offset
- src_x
, I915_TILING_NONE
,
809 INTEL_MIPTREE_TRMODE_NONE
,
810 pitch
, dst_bo
, dst_offset
- dst_x
, I915_TILING_NONE
,
811 INTEL_MIPTREE_TRMODE_NONE
,
812 src_x
, 0, /* src x/y */
813 dst_x
, 0, /* dst x/y */
814 pitch
, height
, /* w, h */
817 _mesa_problem(ctx
, "Failed to linear blit %dx%d\n", pitch
, height
);
819 src_offset
+= pitch
* height
;
820 dst_offset
+= pitch
* height
;
821 src_x
= src_offset
% 64;
822 dst_x
= dst_offset
% 64;
823 size
-= pitch
* height
;
824 assert (size
< (1 << 15));
825 pitch
= ALIGN(size
, 4);
828 ok
= intelEmitCopyBlit(brw
, 1,
829 pitch
, src_bo
, src_offset
- src_x
, I915_TILING_NONE
,
830 INTEL_MIPTREE_TRMODE_NONE
,
831 pitch
, dst_bo
, dst_offset
- dst_x
, I915_TILING_NONE
,
832 INTEL_MIPTREE_TRMODE_NONE
,
833 src_x
, 0, /* src x/y */
834 dst_x
, 0, /* dst x/y */
838 _mesa_problem(ctx
, "Failed to linear blit %dx%d\n", size
, 1);
843 * Used to initialize the alpha value of an ARGB8888 miptree after copying
844 * into it from an XRGB8888 source.
846 * This is very common with glCopyTexImage2D(). Note that the coordinates are
847 * relative to the start of the miptree, not relative to a slice within the
851 intel_miptree_set_alpha_to_one(struct brw_context
*brw
,
852 struct intel_mipmap_tree
*mt
,
853 int x
, int y
, int width
, int height
)
857 drm_intel_bo
*aper_array
[2];
862 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
863 __func__
, mt
->bo
, pitch
, x
, y
, width
, height
);
865 BR13
= br13_for_cpp(cpp
) | 0xf0 << 16;
866 CMD
= XY_COLOR_BLT_CMD
;
867 CMD
|= XY_BLT_WRITE_ALPHA
;
869 if (mt
->tiling
!= I915_TILING_NONE
) {
875 /* do space check before going any further */
876 aper_array
[0] = brw
->batch
.bo
;
877 aper_array
[1] = mt
->bo
;
879 if (drm_intel_bufmgr_check_aperture_space(aper_array
,
880 ARRAY_SIZE(aper_array
)) != 0) {
881 intel_batchbuffer_flush(brw
);
884 unsigned length
= brw
->gen
>= 8 ? 7 : 6;
885 bool dst_y_tiled
= mt
->tiling
== I915_TILING_Y
;
887 BEGIN_BATCH_BLT_TILED(length
, dst_y_tiled
, false);
888 OUT_BATCH(CMD
| (length
- 2));
890 OUT_BATCH(SET_FIELD(y
, BLT_Y
) | SET_FIELD(x
, BLT_X
));
891 OUT_BATCH(SET_FIELD(y
+ height
, BLT_Y
) | SET_FIELD(x
+ width
, BLT_X
));
894 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
898 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
901 OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
902 ADVANCE_BATCH_TILED(dst_y_tiled
, false);
904 brw_emit_mi_flush(brw
);