src/mesa/drivers/dri/i965/intel_blit.c

   1 /*
   2  * Copyright 2003 VMware, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include "main/mtypes.h"
  27 #include "main/blit.h"
  28 #include "main/context.h"
  29 #include "main/enums.h"
  30 #include "main/fbobject.h"
  31
  32 #include "brw_context.h"
  33 #include "brw_defines.h"
  34 #include "intel_blit.h"
  35 #include "intel_buffers.h"
  36 #include "intel_fbo.h"
  37 #include "intel_batchbuffer.h"
  38 #include "intel_mipmap_tree.h"
  39
  40 #define FILE_DEBUG_FLAG DEBUG_BLIT
  41
  42 static void
  43 intel_miptree_set_alpha_to_one(struct brw_context *brw,
  44                                struct intel_mipmap_tree *mt,
  45                                int x, int y, int width, int height);
  46
  47 static GLuint translate_raster_op(GLenum logicop)
  48 {
  49    switch(logicop) {
  50    case GL_CLEAR: return 0x00;
  51    case GL_AND: return 0x88;
  52    case GL_AND_REVERSE: return 0x44;
  53    case GL_COPY: return 0xCC;
  54    case GL_AND_INVERTED: return 0x22;
  55    case GL_NOOP: return 0xAA;
  56    case GL_XOR: return 0x66;
  57    case GL_OR: return 0xEE;
  58    case GL_NOR: return 0x11;
  59    case GL_EQUIV: return 0x99;
  60    case GL_INVERT: return 0x55;
  61    case GL_OR_REVERSE: return 0xDD;
  62    case GL_COPY_INVERTED: return 0x33;
  63    case GL_OR_INVERTED: return 0xBB;
  64    case GL_NAND: return 0x77;
  65    case GL_SET: return 0xFF;
  66    default: return 0;
  67    }
  68 }
  69
  70 static uint32_t
  71 br13_for_cpp(int cpp)
  72 {
  73    switch (cpp) {
  74    case 16:
  75       return BR13_32323232;
  76    case 8:
  77       return BR13_16161616;
  78    case 4:
  79       return BR13_8888;
  80    case 2:
  81       return BR13_565;
  82    case 1:
  83       return BR13_8;
  84    default:
  85       unreachable("not reached");
  86    }
  87 }
  88
  89 /**
  90  * Emits the packet for switching the blitter from X to Y tiled or back.
  91  *
  92  * This has to be called in a single BEGIN_BATCH_BLT_TILED() /
  93  * ADVANCE_BATCH_TILED().  This is because BCS_SWCTRL is saved and restored as
  94  * part of the power context, not a render context, and if the batchbuffer was
  95  * to get flushed between setting and blitting, or blitting and restoring, our
  96  * tiling state would leak into other unsuspecting applications (like the X
  97  * server).
  98  */
  99 static uint32_t *
 100 set_blitter_tiling(struct brw_context *brw,
 101                    bool dst_y_tiled, bool src_y_tiled,
 102                    uint32_t *__map)
 103 {
 104    const struct gen_device_info *devinfo = &brw->screen->devinfo;
 105
 106    assert(devinfo->gen >= 6);
 107
 108    /* Idle the blitter before we update how tiling is interpreted. */
 109    OUT_BATCH(MI_FLUSH_DW);
 110    OUT_BATCH(0);
 111    OUT_BATCH(0);
 112    OUT_BATCH(0);
 113
 114    OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
 115    OUT_BATCH(BCS_SWCTRL);
 116    OUT_BATCH((BCS_SWCTRL_DST_Y | BCS_SWCTRL_SRC_Y) << 16 |
 117              (dst_y_tiled ? BCS_SWCTRL_DST_Y : 0) |
 118              (src_y_tiled ? BCS_SWCTRL_SRC_Y : 0));
 119    return __map;
 120 }
 121 #define SET_BLITTER_TILING(...) __map = set_blitter_tiling(__VA_ARGS__, __map)
 122
 123 #define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled)              \
 124       BEGIN_BATCH_BLT(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0));     \
 125       if (dst_y_tiled || src_y_tiled)                                   \
 126          SET_BLITTER_TILING(brw, dst_y_tiled, src_y_tiled)
 127
 128 #define ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled)                   \
 129       if (dst_y_tiled || src_y_tiled)                                   \
 130          SET_BLITTER_TILING(brw, false, false);                         \
 131       ADVANCE_BATCH()
 132
 133 static int
 134 blt_pitch(struct intel_mipmap_tree *mt)
 135 {
 136    int pitch = mt->surf.row_pitch;
 137    if (mt->surf.tiling != ISL_TILING_LINEAR)
 138       pitch /= 4;
 139    return pitch;
 140 }
 141
 142 bool
 143 intel_miptree_blit_compatible_formats(mesa_format src, mesa_format dst)
 144 {
 145    /* The BLT doesn't handle sRGB conversion */
 146    assert(src == _mesa_get_srgb_format_linear(src));
 147    assert(dst == _mesa_get_srgb_format_linear(dst));
 148
 149    /* No swizzle or format conversions possible, except... */
 150    if (src == dst)
 151       return true;
 152
 153    /* ...we can either discard the alpha channel when going from A->X,
 154     * or we can fill the alpha channel with 0xff when going from X->A
 155     */
 156    if (src == MESA_FORMAT_B8G8R8A8_UNORM || src == MESA_FORMAT_B8G8R8X8_UNORM)
 157       return (dst == MESA_FORMAT_B8G8R8A8_UNORM ||
 158               dst == MESA_FORMAT_B8G8R8X8_UNORM);
 159
 160    if (src == MESA_FORMAT_R8G8B8A8_UNORM || src == MESA_FORMAT_R8G8B8X8_UNORM)
 161       return (dst == MESA_FORMAT_R8G8B8A8_UNORM ||
 162               dst == MESA_FORMAT_R8G8B8X8_UNORM);
 163
 164    return false;
 165 }
 166
 167 static void
 168 get_blit_intratile_offset_el(const struct brw_context *brw,
 169                              struct intel_mipmap_tree *mt,
 170                              uint32_t total_x_offset_el,
 171                              uint32_t total_y_offset_el,
 172                              uint32_t *base_address_offset,
 173                              uint32_t *x_offset_el,
 174                              uint32_t *y_offset_el)
 175 {
 176    isl_tiling_get_intratile_offset_el(mt->surf.tiling,
 177                                       mt->cpp * 8, mt->surf.row_pitch,
 178                                       total_x_offset_el, total_y_offset_el,
 179                                       base_address_offset,
 180                                       x_offset_el, y_offset_el);
 181    if (mt->surf.tiling == ISL_TILING_LINEAR) {
 182       /* From the Broadwell PRM docs for XY_SRC_COPY_BLT::SourceBaseAddress:
 183        *
 184        *    "Base address of the destination surface: X=0, Y=0. Lower 32bits
 185        *    of the 48bit addressing. When Src Tiling is enabled (Bit_15
 186        *    enabled), this address must be 4KB-aligned. When Tiling is not
 187        *    enabled, this address should be CL (64byte) aligned."
 188        *
 189        * The offsets we get from ISL in the tiled case are already aligned.
 190        * In the linear case, we need to do some of our own aligning.
 191        */
 192       uint32_t delta = *base_address_offset & 63;
 193       assert(delta % mt->cpp == 0);
 194       *base_address_offset -= delta;
 195       *x_offset_el += delta / mt->cpp;
 196    } else {
 197       assert(*base_address_offset % 4096 == 0);
 198    }
 199 }
 200
 201 static bool
 202 emit_miptree_blit(struct brw_context *brw,
 203                   struct intel_mipmap_tree *src_mt,
 204                   uint32_t src_x, uint32_t src_y,
 205                   struct intel_mipmap_tree *dst_mt,
 206                   uint32_t dst_x, uint32_t dst_y,
 207                   uint32_t width, uint32_t height,
 208                   bool reverse, GLenum logicop)
 209 {
 210    /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
 211     * Data Size Limitations):
 212     *
 213     *    The BLT engine is capable of transferring very large quantities of
 214     *    graphics data. Any graphics data read from and written to the
 215     *    destination is permitted to represent a number of pixels that
 216     *    occupies up to 65,536 scan lines and up to 32,768 bytes per scan line
 217     *    at the destination. The maximum number of pixels that may be
 218     *    represented per scan line’s worth of graphics data depends on the
 219     *    color depth.
 220     *
 221     * The blitter's pitch is a signed 16-bit integer, but measured in bytes
 222     * for linear surfaces and DWords for tiled surfaces.  So the maximum
 223     * pitch is 32k linear and 128k tiled.
 224     */
 225    if (blt_pitch(src_mt) >= 32768 || blt_pitch(dst_mt) >= 32768) {
 226       perf_debug("Falling back due to >= 32k/128k pitch\n");
 227       return false;
 228    }
 229
 230    /* We need to split the blit into chunks that each fit within the blitter's
 231     * restrictions.  We can't use a chunk size of 32768 because we need to
 232     * ensure that src_tile_x + chunk_size fits.  We choose 16384 because it's
 233     * a nice round power of two, big enough that performance won't suffer, and
 234     * small enough to guarantee everything fits.
 235     */
 236    const uint32_t max_chunk_size = 16384;
 237
 238    for (uint32_t chunk_x = 0; chunk_x < width; chunk_x += max_chunk_size) {
 239       for (uint32_t chunk_y = 0; chunk_y < height; chunk_y += max_chunk_size) {
 240          const uint32_t chunk_w = MIN2(max_chunk_size, width - chunk_x);
 241          const uint32_t chunk_h = MIN2(max_chunk_size, height - chunk_y);
 242
 243          uint32_t src_offset, src_tile_x, src_tile_y;
 244          get_blit_intratile_offset_el(brw, src_mt,
 245                                       src_x + chunk_x, src_y + chunk_y,
 246                                       &src_offset, &src_tile_x, &src_tile_y);
 247
 248          uint32_t dst_offset, dst_tile_x, dst_tile_y;
 249          get_blit_intratile_offset_el(brw, dst_mt,
 250                                       dst_x + chunk_x, dst_y + chunk_y,
 251                                       &dst_offset, &dst_tile_x, &dst_tile_y);
 252
 253          if (!intelEmitCopyBlit(brw,
 254                                 src_mt->cpp,
 255                                 reverse ? -src_mt->surf.row_pitch :
 256                                            src_mt->surf.row_pitch,
 257                                 src_mt->bo, src_mt->offset + src_offset,
 258                                 src_mt->surf.tiling,
 259                                 dst_mt->surf.row_pitch,
 260                                 dst_mt->bo, dst_mt->offset + dst_offset,
 261                                 dst_mt->surf.tiling,
 262                                 src_tile_x, src_tile_y,
 263                                 dst_tile_x, dst_tile_y,
 264                                 chunk_w, chunk_h,
 265                                 logicop)) {
 266             /* If this is ever going to fail, it will fail on the first chunk */
 267             assert(chunk_x == 0 && chunk_y == 0);
 268             return false;
 269          }
 270       }
 271    }
 272
 273    return true;
 274 }
 275
 276 /**
 277  * Implements a rectangular block transfer (blit) of pixels between two
 278  * miptrees.
 279  *
 280  * Our blitter can operate on 1, 2, or 4-byte-per-pixel data, with generous,
 281  * but limited, pitches and sizes allowed.
 282  *
 283  * The src/dst coordinates are relative to the given level/slice of the
 284  * miptree.
 285  *
 286  * If @src_flip or @dst_flip is set, then the rectangle within that miptree
 287  * will be inverted (including scanline order) when copying.  This is common
 288  * in GL when copying between window system and user-created
 289  * renderbuffers/textures.
 290  */
 291 bool
 292 intel_miptree_blit(struct brw_context *brw,
 293                    struct intel_mipmap_tree *src_mt,
 294                    int src_level, int src_slice,
 295                    uint32_t src_x, uint32_t src_y, bool src_flip,
 296                    struct intel_mipmap_tree *dst_mt,
 297                    int dst_level, int dst_slice,
 298                    uint32_t dst_x, uint32_t dst_y, bool dst_flip,
 299                    uint32_t width, uint32_t height,
 300                    GLenum logicop)
 301 {
 302    /* The blitter doesn't understand multisampling at all. */
 303    if (src_mt->surf.samples > 1 || dst_mt->surf.samples > 1)
 304       return false;
 305
 306    /* No sRGB decode or encode is done by the hardware blitter, which is
 307     * consistent with what we want in many callers (glCopyTexSubImage(),
 308     * texture validation, etc.).
 309     */
 310    mesa_format src_format = _mesa_get_srgb_format_linear(src_mt->format);
 311    mesa_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format);
 312
 313    /* The blitter doesn't support doing any format conversions.  We do also
 314     * support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into
 315     * the X channel don't matter), and XRGB8888 to ARGB8888 by setting the A
 316     * channel to 1.0 at the end.
 317     */
 318    if (!intel_miptree_blit_compatible_formats(src_format, dst_format)) {
 319       perf_debug("%s: Can't use hardware blitter from %s to %s, "
 320                  "falling back.\n", __func__,
 321                  _mesa_get_format_name(src_format),
 322                  _mesa_get_format_name(dst_format));
 323       return false;
 324    }
 325
 326    /* The blitter has no idea about HiZ or fast color clears, so we need to
 327     * resolve the miptrees before we do anything.
 328     */
 329    intel_miptree_access_raw(brw, src_mt, src_level, src_slice, false);
 330    intel_miptree_access_raw(brw, dst_mt, dst_level, dst_slice, true);
 331
 332    if (src_flip) {
 333       const unsigned h0 = src_mt->surf.phys_level0_sa.height;
 334       src_y = minify(h0, src_level - src_mt->first_level) - src_y - height;
 335    }
 336
 337    if (dst_flip) {
 338       const unsigned h0 = dst_mt->surf.phys_level0_sa.height;
 339       dst_y = minify(h0, dst_level - dst_mt->first_level) - dst_y - height;
 340    }
 341
 342    uint32_t src_image_x, src_image_y, dst_image_x, dst_image_y;
 343    intel_miptree_get_image_offset(src_mt, src_level, src_slice,
 344                                   &src_image_x, &src_image_y);
 345    intel_miptree_get_image_offset(dst_mt, dst_level, dst_slice,
 346                                   &dst_image_x, &dst_image_y);
 347    src_x += src_image_x;
 348    src_y += src_image_y;
 349    dst_x += dst_image_x;
 350    dst_y += dst_image_y;
 351
 352    if (!emit_miptree_blit(brw, src_mt, src_x, src_y,
 353                           dst_mt, dst_x, dst_y, width, height,
 354                           src_flip != dst_flip, logicop)) {
 355       return false;
 356    }
 357
 358    /* XXX This could be done in a single pass using XY_FULL_MONO_PATTERN_BLT */
 359    if (_mesa_get_format_bits(src_format, GL_ALPHA_BITS) == 0 &&
 360        _mesa_get_format_bits(dst_format, GL_ALPHA_BITS) > 0) {
 361       intel_miptree_set_alpha_to_one(brw, dst_mt,
 362                                      dst_x, dst_y,
 363                                      width, height);
 364    }
 365
 366    return true;
 367 }
 368
 369 bool
 370 intel_miptree_copy(struct brw_context *brw,
 371                    struct intel_mipmap_tree *src_mt,
 372                    int src_level, int src_slice,
 373                    uint32_t src_x, uint32_t src_y,
 374                    struct intel_mipmap_tree *dst_mt,
 375                    int dst_level, int dst_slice,
 376                    uint32_t dst_x, uint32_t dst_y,
 377                    uint32_t src_width, uint32_t src_height)
 378 {
 379    /* The blitter doesn't understand multisampling at all. */
 380    if (src_mt->surf.samples > 1 || dst_mt->surf.samples > 1)
 381       return false;
 382
 383    if (src_mt->format == MESA_FORMAT_S_UINT8)
 384       return false;
 385
 386    /* The blitter has no idea about HiZ or fast color clears, so we need to
 387     * resolve the miptrees before we do anything.
 388     */
 389    intel_miptree_access_raw(brw, src_mt, src_level, src_slice, false);
 390    intel_miptree_access_raw(brw, dst_mt, dst_level, dst_slice, true);
 391
 392    uint32_t src_image_x, src_image_y;
 393    intel_miptree_get_image_offset(src_mt, src_level, src_slice,
 394                                   &src_image_x, &src_image_y);
 395
 396    if (_mesa_is_format_compressed(src_mt->format)) {
 397       GLuint bw, bh;
 398       _mesa_get_format_block_size(src_mt->format, &bw, &bh);
 399
 400       /* Compressed textures need not have dimensions that are a multiple of
 401        * the block size.  Rectangles in compressed textures do need to be a
 402        * multiple of the block size.  The one exception is that the right and
 403        * bottom edges may be at the right or bottom edge of the miplevel even
 404        * if it's not aligned.
 405        */
 406       assert(src_x % bw == 0);
 407       assert(src_y % bh == 0);
 408
 409       assert(src_width % bw == 0 ||
 410              src_x + src_width ==
 411              minify(src_mt->surf.logical_level0_px.width, src_level));
 412       assert(src_height % bh == 0 ||
 413              src_y + src_height ==
 414              minify(src_mt->surf.logical_level0_px.height, src_level));
 415
 416       src_x /= (int)bw;
 417       src_y /= (int)bh;
 418       src_width = DIV_ROUND_UP(src_width, (int)bw);
 419       src_height = DIV_ROUND_UP(src_height, (int)bh);
 420    }
 421    src_x += src_image_x;
 422    src_y += src_image_y;
 423
 424    uint32_t dst_image_x, dst_image_y;
 425    intel_miptree_get_image_offset(dst_mt, dst_level, dst_slice,
 426                                   &dst_image_x, &dst_image_y);
 427
 428    if (_mesa_is_format_compressed(dst_mt->format)) {
 429       GLuint bw, bh;
 430       _mesa_get_format_block_size(dst_mt->format, &bw, &bh);
 431
 432       assert(dst_x % bw == 0);
 433       assert(dst_y % bh == 0);
 434
 435       dst_x /= (int)bw;
 436       dst_y /= (int)bh;
 437    }
 438    dst_x += dst_image_x;
 439    dst_y += dst_image_y;
 440
 441    return emit_miptree_blit(brw, src_mt, src_x, src_y,
 442                             dst_mt, dst_x, dst_y,
 443                             src_width, src_height, false, GL_COPY);
 444 }
 445
 446 static bool
 447 alignment_valid(struct brw_context *brw, unsigned offset,
 448                 enum isl_tiling tiling)
 449 {
 450    const struct gen_device_info *devinfo = &brw->screen->devinfo;
 451
 452    /* Tiled buffers must be page-aligned (4K). */
 453    if (tiling != ISL_TILING_LINEAR)
 454       return (offset & 4095) == 0;
 455
 456    /* On Gen8+, linear buffers must be cacheline-aligned. */
 457    if (devinfo->gen >= 8)
 458       return (offset & 63) == 0;
 459
 460    return true;
 461 }
 462
 463 static uint32_t
 464 xy_blit_cmd(enum isl_tiling src_tiling, enum isl_tiling dst_tiling,
 465             uint32_t cpp)
 466 {
 467    uint32_t CMD = 0;
 468
 469    assert(cpp <= 4);
 470    switch (cpp) {
 471    case 1:
 472    case 2:
 473       CMD = XY_SRC_COPY_BLT_CMD;
 474       break;
 475    case 4:
 476       CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 477       break;
 478    default:
 479       unreachable("not reached");
 480    }
 481
 482    if (dst_tiling != ISL_TILING_LINEAR)
 483       CMD |= XY_DST_TILED;
 484
 485    if (src_tiling != ISL_TILING_LINEAR)
 486       CMD |= XY_SRC_TILED;
 487
 488    return CMD;
 489 }
 490
 491 /* Copy BitBlt
 492  */
 493 bool
 494 intelEmitCopyBlit(struct brw_context *brw,
 495                   GLuint cpp,
 496                   int32_t src_pitch,
 497                   struct brw_bo *src_buffer,
 498                   GLuint src_offset,
 499                   enum isl_tiling src_tiling,
 500                   int32_t dst_pitch,
 501                   struct brw_bo *dst_buffer,
 502                   GLuint dst_offset,
 503                   enum isl_tiling dst_tiling,
 504                   GLshort src_x, GLshort src_y,
 505                   GLshort dst_x, GLshort dst_y,
 506                   GLshort w, GLshort h,
 507                   GLenum logic_op)
 508 {
 509    const struct gen_device_info *devinfo = &brw->screen->devinfo;
 510    GLuint CMD, BR13;
 511    int dst_y2 = dst_y + h;
 512    int dst_x2 = dst_x + w;
 513    bool dst_y_tiled = dst_tiling == ISL_TILING_Y0;
 514    bool src_y_tiled = src_tiling == ISL_TILING_Y0;
 515    uint32_t src_tile_w, src_tile_h;
 516    uint32_t dst_tile_w, dst_tile_h;
 517
 518    if ((dst_y_tiled || src_y_tiled) && devinfo->gen < 6)
 519       return false;
 520
 521    const unsigned bo_sizes = dst_buffer->size + src_buffer->size;
 522
 523    /* do space check before going any further */
 524    if (!brw_batch_has_aperture_space(brw, bo_sizes))
 525       intel_batchbuffer_flush(brw);
 526
 527    if (!brw_batch_has_aperture_space(brw, bo_sizes))
 528       return false;
 529
 530    unsigned length = devinfo->gen >= 8 ? 10 : 8;
 531
 532    intel_batchbuffer_require_space(brw, length * 4, BLT_RING);
 533    DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
 534        __func__,
 535        src_buffer, src_pitch, src_offset, src_x, src_y,
 536        dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
 537
 538    intel_get_tile_dims(src_tiling, cpp, &src_tile_w, &src_tile_h);
 539    intel_get_tile_dims(dst_tiling, cpp, &dst_tile_w, &dst_tile_h);
 540
 541    /* For Tiled surfaces, the pitch has to be a multiple of the Tile width
 542     * (X direction width of the Tile). This is ensured while allocating the
 543     * buffer object.
 544     */
 545    assert(src_tiling == ISL_TILING_LINEAR || (src_pitch % src_tile_w) == 0);
 546    assert(dst_tiling == ISL_TILING_LINEAR || (dst_pitch % dst_tile_w) == 0);
 547
 548    /* For big formats (such as floating point), do the copy using 16 or
 549     * 32bpp and multiply the coordinates.
 550     */
 551    if (cpp > 4) {
 552       if (cpp % 4 == 2) {
 553          dst_x *= cpp / 2;
 554          dst_x2 *= cpp / 2;
 555          src_x *= cpp / 2;
 556          cpp = 2;
 557       } else {
 558          assert(cpp % 4 == 0);
 559          dst_x *= cpp / 4;
 560          dst_x2 *= cpp / 4;
 561          src_x *= cpp / 4;
 562          cpp = 4;
 563       }
 564    }
 565
 566    if (!alignment_valid(brw, dst_offset, dst_tiling))
 567       return false;
 568    if (!alignment_valid(brw, src_offset, src_tiling))
 569       return false;
 570
 571    /* Blit pitch must be dword-aligned.  Otherwise, the hardware appears to drop
 572     * the low bits.  Offsets must be naturally aligned.
 573     */
 574    if (src_pitch % 4 != 0 || src_offset % cpp != 0 ||
 575        dst_pitch % 4 != 0 || dst_offset % cpp != 0)
 576       return false;
 577
 578    assert(cpp <= 4);
 579    BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16;
 580
 581    CMD = xy_blit_cmd(src_tiling, dst_tiling, cpp);
 582
 583    /* For tiled source and destination, pitch value should be specified
 584     * as a number of Dwords.
 585     */
 586    if (dst_tiling != ISL_TILING_LINEAR)
 587       dst_pitch /= 4;
 588
 589    if (src_tiling != ISL_TILING_LINEAR)
 590       src_pitch /= 4;
 591
 592    if (dst_y2 <= dst_y || dst_x2 <= dst_x)
 593       return true;
 594
 595    assert(dst_x < dst_x2);
 596    assert(dst_y < dst_y2);
 597
 598    BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, src_y_tiled);
 599    OUT_BATCH(CMD | (length - 2));
 600    OUT_BATCH(BR13 | (uint16_t)dst_pitch);
 601    OUT_BATCH(SET_FIELD(dst_y, BLT_Y) | SET_FIELD(dst_x, BLT_X));
 602    OUT_BATCH(SET_FIELD(dst_y2, BLT_Y) | SET_FIELD(dst_x2, BLT_X));
 603    if (devinfo->gen >= 8) {
 604       OUT_RELOC64(dst_buffer, RELOC_WRITE, dst_offset);
 605    } else {
 606       OUT_RELOC(dst_buffer, RELOC_WRITE, dst_offset);
 607    }
 608    OUT_BATCH(SET_FIELD(src_y, BLT_Y) | SET_FIELD(src_x, BLT_X));
 609    OUT_BATCH((uint16_t)src_pitch);
 610    if (devinfo->gen >= 8) {
 611       OUT_RELOC64(src_buffer, 0, src_offset);
 612    } else {
 613       OUT_RELOC(src_buffer, 0, src_offset);
 614    }
 615
 616    ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled);
 617
 618    brw_emit_mi_flush(brw);
 619
 620    return true;
 621 }
 622
 623 bool
 624 intelEmitImmediateColorExpandBlit(struct brw_context *brw,
 625                                   GLuint cpp,
 626                                   GLubyte *src_bits, GLuint src_size,
 627                                   GLuint fg_color,
 628                                   GLshort dst_pitch,
 629                                   struct brw_bo *dst_buffer,
 630                                   GLuint dst_offset,
 631                                   enum isl_tiling dst_tiling,
 632                                   GLshort x, GLshort y,
 633                                   GLshort w, GLshort h,
 634                                   GLenum logic_op)
 635 {
 636    const struct gen_device_info *devinfo = &brw->screen->devinfo;
 637    int dwords = ALIGN(src_size, 8) / 4;
 638    uint32_t opcode, br13, blit_cmd;
 639
 640    if (dst_tiling != ISL_TILING_LINEAR) {
 641       if (dst_offset & 4095)
 642          return false;
 643       if (dst_tiling == ISL_TILING_Y0)
 644          return false;
 645    }
 646
 647    assert((logic_op >= GL_CLEAR) && (logic_op <= (GL_CLEAR + 0x0f)));
 648    assert(dst_pitch > 0);
 649
 650    if (w < 0 || h < 0)
 651       return true;
 652
 653    DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
 654        __func__,
 655        dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
 656
 657    unsigned xy_setup_blt_length = devinfo->gen >= 8 ? 10 : 8;
 658    intel_batchbuffer_require_space(brw, (xy_setup_blt_length * 4) +
 659                                         (3 * 4) + dwords * 4, BLT_RING);
 660
 661    opcode = XY_SETUP_BLT_CMD;
 662    if (cpp == 4)
 663       opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 664    if (dst_tiling != ISL_TILING_LINEAR) {
 665       opcode |= XY_DST_TILED;
 666       dst_pitch /= 4;
 667    }
 668
 669    br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
 670    br13 |= br13_for_cpp(cpp);
 671
 672    blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
 673    if (dst_tiling != ISL_TILING_LINEAR)
 674       blit_cmd |= XY_DST_TILED;
 675
 676    BEGIN_BATCH_BLT(xy_setup_blt_length + 3);
 677    OUT_BATCH(opcode | (xy_setup_blt_length - 2));
 678    OUT_BATCH(br13);
 679    OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
 680    OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
 681    if (devinfo->gen >= 8) {
 682       OUT_RELOC64(dst_buffer, RELOC_WRITE, dst_offset);
 683    } else {
 684       OUT_RELOC(dst_buffer, RELOC_WRITE, dst_offset);
 685    }
 686    OUT_BATCH(0); /* bg */
 687    OUT_BATCH(fg_color); /* fg */
 688    OUT_BATCH(0); /* pattern base addr */
 689    if (devinfo->gen >= 8)
 690       OUT_BATCH(0);
 691
 692    OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
 693    OUT_BATCH(SET_FIELD(y, BLT_Y) | SET_FIELD(x, BLT_X));
 694    OUT_BATCH(SET_FIELD(y + h, BLT_Y) | SET_FIELD(x + w, BLT_X));
 695    ADVANCE_BATCH();
 696
 697    intel_batchbuffer_data(brw, src_bits, dwords * 4, BLT_RING);
 698
 699    brw_emit_mi_flush(brw);
 700
 701    return true;
 702 }
 703
 704 /* We don't have a memmove-type blit like some other hardware, so we'll do a
 705  * rectangular blit covering a large space, then emit 1-scanline blit at the
 706  * end to cover the last if we need.
 707  */
 708 void
 709 intel_emit_linear_blit(struct brw_context *brw,
 710                        struct brw_bo *dst_bo,
 711                        unsigned int dst_offset,
 712                        struct brw_bo *src_bo,
 713                        unsigned int src_offset,
 714                        unsigned int size)
 715 {
 716    struct gl_context *ctx = &brw->ctx;
 717    GLuint pitch, height;
 718    int16_t src_x, dst_x;
 719    bool ok;
 720
 721    do {
 722       /* The pitch given to the GPU must be DWORD aligned, and
 723        * we want width to match pitch. Max width is (1 << 15 - 1),
 724        * rounding that down to the nearest DWORD is 1 << 15 - 4
 725        */
 726       pitch = ROUND_DOWN_TO(MIN2(size, (1 << 15) - 64), 4);
 727       height = (size < pitch || pitch == 0) ? 1 : size / pitch;
 728
 729       src_x = src_offset % 64;
 730       dst_x = dst_offset % 64;
 731       pitch = ALIGN(MIN2(size, (1 << 15) - 64), 4);
 732       assert(src_x + pitch < 1 << 15);
 733       assert(dst_x + pitch < 1 << 15);
 734
 735       ok = intelEmitCopyBlit(brw, 1,
 736                              pitch, src_bo, src_offset - src_x,
 737                              ISL_TILING_LINEAR,
 738                              pitch, dst_bo, dst_offset - dst_x,
 739                              ISL_TILING_LINEAR,
 740                              src_x, 0, /* src x/y */
 741                              dst_x, 0, /* dst x/y */
 742                              MIN2(size, pitch), height, /* w, h */
 743                              GL_COPY);
 744       if (!ok) {
 745          _mesa_problem(ctx, "Failed to linear blit %dx%d\n",
 746                        MIN2(size, pitch), height);
 747          return;
 748       }
 749
 750       pitch *= height;
 751       if (size <= pitch)
 752          return;
 753
 754       src_offset += pitch;
 755       dst_offset += pitch;
 756       size -= pitch;
 757    } while (1);
 758 }
 759
 760 /**
 761  * Used to initialize the alpha value of an ARGB8888 miptree after copying
 762  * into it from an XRGB8888 source.
 763  *
 764  * This is very common with glCopyTexImage2D().  Note that the coordinates are
 765  * relative to the start of the miptree, not relative to a slice within the
 766  * miptree.
 767  */
 768 static void
 769 intel_miptree_set_alpha_to_one(struct brw_context *brw,
 770                               struct intel_mipmap_tree *mt,
 771                               int x, int y, int width, int height)
 772 {
 773    const struct gen_device_info *devinfo = &brw->screen->devinfo;
 774    uint32_t BR13, CMD;
 775    int pitch, cpp;
 776
 777    pitch = mt->surf.row_pitch;
 778    cpp = mt->cpp;
 779
 780    DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
 781        __func__, mt->bo, pitch, x, y, width, height);
 782
 783    BR13 = br13_for_cpp(cpp) | 0xf0 << 16;
 784    CMD = XY_COLOR_BLT_CMD;
 785    CMD |= XY_BLT_WRITE_ALPHA;
 786
 787    if (mt->surf.tiling != ISL_TILING_LINEAR) {
 788       CMD |= XY_DST_TILED;
 789       pitch /= 4;
 790    }
 791    BR13 |= pitch;
 792
 793    /* do space check before going any further */
 794    if (!brw_batch_has_aperture_space(brw, mt->bo->size))
 795       intel_batchbuffer_flush(brw);
 796
 797    unsigned length = devinfo->gen >= 8 ? 7 : 6;
 798    const bool dst_y_tiled = mt->surf.tiling == ISL_TILING_Y0;
 799
 800    /* We need to split the blit into chunks that each fit within the blitter's
 801     * restrictions.  We can't use a chunk size of 32768 because we need to
 802     * ensure that src_tile_x + chunk_size fits.  We choose 16384 because it's
 803     * a nice round power of two, big enough that performance won't suffer, and
 804     * small enough to guarantee everything fits.
 805     */
 806    const uint32_t max_chunk_size = 16384;
 807
 808    for (uint32_t chunk_x = 0; chunk_x < width; chunk_x += max_chunk_size) {
 809       for (uint32_t chunk_y = 0; chunk_y < height; chunk_y += max_chunk_size) {
 810          const uint32_t chunk_w = MIN2(max_chunk_size, width - chunk_x);
 811          const uint32_t chunk_h = MIN2(max_chunk_size, height - chunk_y);
 812
 813          uint32_t offset, tile_x, tile_y;
 814          get_blit_intratile_offset_el(brw, mt,
 815                                       x + chunk_x, y + chunk_y,
 816                                       &offset, &tile_x, &tile_y);
 817
 818          BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, false);
 819          OUT_BATCH(CMD | (length - 2));
 820          OUT_BATCH(BR13);
 821          OUT_BATCH(SET_FIELD(y + chunk_y, BLT_Y) |
 822                    SET_FIELD(x + chunk_x, BLT_X));
 823          OUT_BATCH(SET_FIELD(y + chunk_y + chunk_h, BLT_Y) |
 824                    SET_FIELD(x + chunk_x + chunk_w, BLT_X));
 825          if (devinfo->gen >= 8) {
 826             OUT_RELOC64(mt->bo, RELOC_WRITE, mt->offset + offset);
 827          } else {
 828             OUT_RELOC(mt->bo, RELOC_WRITE, mt->offset + offset);
 829          }
 830          OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
 831          ADVANCE_BATCH_TILED(dst_y_tiled, false);
 832       }
 833    }
 834
 835    brw_emit_mi_flush(brw);
 836 }