2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "main/mtypes.h"
27 #include "main/blit.h"
28 #include "main/context.h"
29 #include "main/enums.h"
30 #include "main/fbobject.h"
32 #include "brw_context.h"
33 #include "brw_defines.h"
34 #include "intel_blit.h"
35 #include "intel_buffers.h"
36 #include "intel_fbo.h"
37 #include "intel_batchbuffer.h"
38 #include "intel_mipmap_tree.h"
40 #define FILE_DEBUG_FLAG DEBUG_BLIT
42 #define SET_TILING_XY_FAST_COPY_BLT(tiling, tr_mode, type) \
46 CMD |= type ## _TILED_X; \
49 if (tr_mode == INTEL_MIPTREE_TRMODE_YS) \
50 CMD |= type ## _TILED_64K; \
52 CMD |= type ## _TILED_Y; \
55 unreachable("not reached"); \
60 intel_miptree_set_alpha_to_one(struct brw_context
*brw
,
61 struct intel_mipmap_tree
*mt
,
62 int x
, int y
, int width
, int height
);
64 static GLuint
translate_raster_op(GLenum logicop
)
67 case GL_CLEAR
: return 0x00;
68 case GL_AND
: return 0x88;
69 case GL_AND_REVERSE
: return 0x44;
70 case GL_COPY
: return 0xCC;
71 case GL_AND_INVERTED
: return 0x22;
72 case GL_NOOP
: return 0xAA;
73 case GL_XOR
: return 0x66;
74 case GL_OR
: return 0xEE;
75 case GL_NOR
: return 0x11;
76 case GL_EQUIV
: return 0x99;
77 case GL_INVERT
: return 0x55;
78 case GL_OR_REVERSE
: return 0xDD;
79 case GL_COPY_INVERTED
: return 0x33;
80 case GL_OR_INVERTED
: return 0xBB;
81 case GL_NAND
: return 0x77;
82 case GL_SET
: return 0xFF;
102 unreachable("not reached");
107 * Emits the packet for switching the blitter from X to Y tiled or back.
109 * This has to be called in a single BEGIN_BATCH_BLT_TILED() /
110 * ADVANCE_BATCH_TILED(). This is because BCS_SWCTRL is saved and restored as
111 * part of the power context, not a render context, and if the batchbuffer was
112 * to get flushed between setting and blitting, or blitting and restoring, our
113 * tiling state would leak into other unsuspecting applications (like the X
117 set_blitter_tiling(struct brw_context
*brw
,
118 bool dst_y_tiled
, bool src_y_tiled
,
121 assert(brw
->gen
>= 6);
123 /* Idle the blitter before we update how tiling is interpreted. */
124 OUT_BATCH(MI_FLUSH_DW
);
129 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
130 OUT_BATCH(BCS_SWCTRL
);
131 OUT_BATCH((BCS_SWCTRL_DST_Y
| BCS_SWCTRL_SRC_Y
) << 16 |
132 (dst_y_tiled
? BCS_SWCTRL_DST_Y
: 0) |
133 (src_y_tiled
? BCS_SWCTRL_SRC_Y
: 0));
136 #define SET_BLITTER_TILING(...) __map = set_blitter_tiling(__VA_ARGS__, __map)
138 #define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled) \
139 BEGIN_BATCH_BLT(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0)); \
140 if (dst_y_tiled || src_y_tiled) \
141 SET_BLITTER_TILING(brw, dst_y_tiled, src_y_tiled)
143 #define ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled) \
144 if (dst_y_tiled || src_y_tiled) \
145 SET_BLITTER_TILING(brw, false, false); \
149 blt_pitch(struct intel_mipmap_tree
*mt
)
151 int pitch
= mt
->pitch
;
158 intel_miptree_blit_compatible_formats(mesa_format src
, mesa_format dst
)
160 /* The BLT doesn't handle sRGB conversion */
161 assert(src
== _mesa_get_srgb_format_linear(src
));
162 assert(dst
== _mesa_get_srgb_format_linear(dst
));
164 /* No swizzle or format conversions possible, except... */
168 /* ...we can either discard the alpha channel when going from A->X,
169 * or we can fill the alpha channel with 0xff when going from X->A
171 if (src
== MESA_FORMAT_B8G8R8A8_UNORM
|| src
== MESA_FORMAT_B8G8R8X8_UNORM
)
172 return (dst
== MESA_FORMAT_B8G8R8A8_UNORM
||
173 dst
== MESA_FORMAT_B8G8R8X8_UNORM
);
175 if (src
== MESA_FORMAT_R8G8B8A8_UNORM
|| src
== MESA_FORMAT_R8G8B8X8_UNORM
)
176 return (dst
== MESA_FORMAT_R8G8B8A8_UNORM
||
177 dst
== MESA_FORMAT_R8G8B8X8_UNORM
);
183 * Implements a rectangular block transfer (blit) of pixels between two
186 * Our blitter can operate on 1, 2, or 4-byte-per-pixel data, with generous,
187 * but limited, pitches and sizes allowed.
189 * The src/dst coordinates are relative to the given level/slice of the
192 * If @src_flip or @dst_flip is set, then the rectangle within that miptree
193 * will be inverted (including scanline order) when copying. This is common
194 * in GL when copying between window system and user-created
195 * renderbuffers/textures.
198 intel_miptree_blit(struct brw_context
*brw
,
199 struct intel_mipmap_tree
*src_mt
,
200 int src_level
, int src_slice
,
201 uint32_t src_x
, uint32_t src_y
, bool src_flip
,
202 struct intel_mipmap_tree
*dst_mt
,
203 int dst_level
, int dst_slice
,
204 uint32_t dst_x
, uint32_t dst_y
, bool dst_flip
,
205 uint32_t width
, uint32_t height
,
208 /* The blitter doesn't understand multisampling at all. */
209 if (src_mt
->num_samples
> 0 || dst_mt
->num_samples
> 0)
212 /* No sRGB decode or encode is done by the hardware blitter, which is
213 * consistent with what we want in many callers (glCopyTexSubImage(),
214 * texture validation, etc.).
216 mesa_format src_format
= _mesa_get_srgb_format_linear(src_mt
->format
);
217 mesa_format dst_format
= _mesa_get_srgb_format_linear(dst_mt
->format
);
219 /* The blitter doesn't support doing any format conversions. We do also
220 * support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into
221 * the X channel don't matter), and XRGB8888 to ARGB8888 by setting the A
222 * channel to 1.0 at the end.
224 if (!intel_miptree_blit_compatible_formats(src_format
, dst_format
)) {
225 perf_debug("%s: Can't use hardware blitter from %s to %s, "
226 "falling back.\n", __func__
,
227 _mesa_get_format_name(src_format
),
228 _mesa_get_format_name(dst_format
));
232 /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
233 * Data Size Limitations):
235 * The BLT engine is capable of transferring very large quantities of
236 * graphics data. Any graphics data read from and written to the
237 * destination is permitted to represent a number of pixels that
238 * occupies up to 65,536 scan lines and up to 32,768 bytes per scan line
239 * at the destination. The maximum number of pixels that may be
240 * represented per scan line’s worth of graphics data depends on the
243 * Furthermore, intelEmitCopyBlit (which is called below) uses a signed
244 * 16-bit integer to represent buffer pitch, so it can only handle buffer
245 * pitches < 32k. However, the pitch is measured in bytes for linear buffers
246 * and dwords for tiled buffers.
248 * As a result of these two limitations, we can only use the blitter to do
249 * this copy when the miptree's pitch is less than 32k linear or 128k tiled.
251 if (blt_pitch(src_mt
) >= 32768 || blt_pitch(dst_mt
) >= 32768) {
252 perf_debug("Falling back due to >= 32k/128k pitch\n");
256 /* The blitter has no idea about HiZ or fast color clears, so we need to
257 * resolve the miptrees before we do anything.
259 intel_miptree_slice_resolve_depth(brw
, src_mt
, src_level
, src_slice
);
260 intel_miptree_slice_resolve_depth(brw
, dst_mt
, dst_level
, dst_slice
);
261 intel_miptree_resolve_color(brw
, src_mt
, 0);
262 intel_miptree_resolve_color(brw
, dst_mt
, 0);
265 src_y
= minify(src_mt
->physical_height0
, src_level
- src_mt
->first_level
) - src_y
- height
;
268 dst_y
= minify(dst_mt
->physical_height0
, dst_level
- dst_mt
->first_level
) - dst_y
- height
;
270 uint32_t src_image_x
, src_image_y
, dst_image_x
, dst_image_y
;
271 intel_miptree_get_image_offset(src_mt
, src_level
, src_slice
,
272 &src_image_x
, &src_image_y
);
273 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_slice
,
274 &dst_image_x
, &dst_image_y
);
275 src_x
+= src_image_x
;
276 src_y
+= src_image_y
;
277 dst_x
+= dst_image_x
;
278 dst_y
+= dst_image_y
;
280 /* The blitter interprets the 16-bit destination x/y as a signed 16-bit
281 * value. The values we're working with are unsigned, so make sure we don't
284 if (src_x
>= 32768 || src_y
>= 32768 || dst_x
>= 32768 || dst_y
>= 32768) {
285 perf_debug("Falling back due to >=32k offset [src(%d, %d) dst(%d, %d)]\n",
286 src_x
, src_y
, dst_x
, dst_y
);
290 if (!intelEmitCopyBlit(brw
,
292 src_flip
== dst_flip
? src_mt
->pitch
: -src_mt
->pitch
,
293 src_mt
->bo
, src_mt
->offset
,
297 dst_mt
->bo
, dst_mt
->offset
,
307 /* XXX This could be done in a single pass using XY_FULL_MONO_PATTERN_BLT */
308 if (_mesa_get_format_bits(src_format
, GL_ALPHA_BITS
) == 0 &&
309 _mesa_get_format_bits(dst_format
, GL_ALPHA_BITS
) > 0) {
310 intel_miptree_set_alpha_to_one(brw
, dst_mt
,
319 alignment_valid(struct brw_context
*brw
, unsigned offset
, uint32_t tiling
)
321 /* Tiled buffers must be page-aligned (4K). */
322 if (tiling
!= I915_TILING_NONE
)
323 return (offset
& 4095) == 0;
325 /* On Gen8+, linear buffers must be cacheline-aligned. */
327 return (offset
& 63) == 0;
333 can_fast_copy_blit(struct brw_context
*brw
,
334 drm_intel_bo
*src_buffer
,
335 int16_t src_x
, int16_t src_y
,
336 uintptr_t src_offset
, uint32_t src_pitch
,
337 uint32_t src_tiling
, uint32_t src_tr_mode
,
338 drm_intel_bo
*dst_buffer
,
339 int16_t dst_x
, int16_t dst_y
,
340 uintptr_t dst_offset
, uint32_t dst_pitch
,
341 uint32_t dst_tiling
, uint32_t dst_tr_mode
,
342 int16_t w
, int16_t h
, uint32_t cpp
,
345 const bool dst_tiling_none
= dst_tiling
== I915_TILING_NONE
;
346 const bool src_tiling_none
= src_tiling
== I915_TILING_NONE
;
351 /* Enable fast copy blit only if the surfaces are Yf/Ys tiled.
352 * FIXME: Based on performance data, remove this condition later to
353 * enable for all types of surfaces.
355 if (src_tr_mode
== INTEL_MIPTREE_TRMODE_NONE
&&
356 dst_tr_mode
== INTEL_MIPTREE_TRMODE_NONE
)
359 if (logic_op
!= GL_COPY
)
362 /* The start pixel for Fast Copy blit should be on an OWord boundary. */
363 if ((dst_x
* cpp
| src_x
* cpp
) & 15)
366 /* For all surface types buffers must be cacheline-aligned. */
367 if ((dst_offset
| src_offset
) & 63)
370 /* Color depths which are not power of 2 or greater than 128 bits are
373 if (!_mesa_is_pow_two(cpp
) || cpp
> 16)
376 /* For Fast Copy Blits the pitch cannot be a negative number. So, bit 15
377 * of the destination pitch must be zero.
379 if ((src_pitch
>> 15 & 1) != 0 || (dst_pitch
>> 15 & 1) != 0)
382 /* For Linear surfaces, the pitch has to be an OWord (16byte) multiple. */
383 if ((src_tiling_none
&& src_pitch
% 16 != 0) ||
384 (dst_tiling_none
&& dst_pitch
% 16 != 0))
391 xy_blit_cmd(uint32_t src_tiling
, uint32_t src_tr_mode
,
392 uint32_t dst_tiling
, uint32_t dst_tr_mode
,
393 uint32_t cpp
, bool use_fast_copy_blit
)
397 if (use_fast_copy_blit
) {
398 CMD
= XY_FAST_COPY_BLT_CMD
;
400 if (dst_tiling
!= I915_TILING_NONE
)
401 SET_TILING_XY_FAST_COPY_BLT(dst_tiling
, dst_tr_mode
, XY_FAST_DST
);
403 if (src_tiling
!= I915_TILING_NONE
)
404 SET_TILING_XY_FAST_COPY_BLT(src_tiling
, src_tr_mode
, XY_FAST_SRC
);
410 CMD
= XY_SRC_COPY_BLT_CMD
;
413 CMD
= XY_SRC_COPY_BLT_CMD
| XY_BLT_WRITE_ALPHA
| XY_BLT_WRITE_RGB
;
416 unreachable("not reached");
419 if (dst_tiling
!= I915_TILING_NONE
)
422 if (src_tiling
!= I915_TILING_NONE
)
431 intelEmitCopyBlit(struct brw_context
*brw
,
434 drm_intel_bo
*src_buffer
,
437 uint32_t src_tr_mode
,
439 drm_intel_bo
*dst_buffer
,
442 uint32_t dst_tr_mode
,
443 GLshort src_x
, GLshort src_y
,
444 GLshort dst_x
, GLshort dst_y
,
445 GLshort w
, GLshort h
,
448 GLuint CMD
, BR13
, pass
= 0;
449 int dst_y2
= dst_y
+ h
;
450 int dst_x2
= dst_x
+ w
;
451 drm_intel_bo
*aper_array
[3];
452 bool dst_y_tiled
= dst_tiling
== I915_TILING_Y
;
453 bool src_y_tiled
= src_tiling
== I915_TILING_Y
;
454 bool use_fast_copy_blit
= false;
455 uint32_t src_tile_w
, src_tile_h
;
456 uint32_t dst_tile_w
, dst_tile_h
;
458 if ((dst_y_tiled
|| src_y_tiled
) && brw
->gen
< 6)
461 /* do space check before going any further */
463 aper_array
[0] = brw
->batch
.bo
;
464 aper_array
[1] = dst_buffer
;
465 aper_array
[2] = src_buffer
;
467 if (dri_bufmgr_check_aperture_space(aper_array
, 3) != 0) {
468 intel_batchbuffer_flush(brw
);
477 unsigned length
= brw
->gen
>= 8 ? 10 : 8;
479 intel_batchbuffer_require_space(brw
, length
* 4, BLT_RING
);
480 DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
482 src_buffer
, src_pitch
, src_offset
, src_x
, src_y
,
483 dst_buffer
, dst_pitch
, dst_offset
, dst_x
, dst_y
, w
, h
);
485 intel_get_tile_dims(src_tiling
, src_tr_mode
, cpp
, &src_tile_w
, &src_tile_h
);
486 intel_get_tile_dims(dst_tiling
, dst_tr_mode
, cpp
, &dst_tile_w
, &dst_tile_h
);
488 /* For Tiled surfaces, the pitch has to be a multiple of the Tile width
489 * (X direction width of the Tile). This is ensured while allocating the
492 assert(src_tiling
== I915_TILING_NONE
|| (src_pitch
% src_tile_w
) == 0);
493 assert(dst_tiling
== I915_TILING_NONE
|| (dst_pitch
% dst_tile_w
) == 0);
495 use_fast_copy_blit
= can_fast_copy_blit(brw
,
498 src_offset
, src_pitch
,
499 src_tiling
, src_tr_mode
,
502 dst_offset
, dst_pitch
,
503 dst_tiling
, dst_tr_mode
,
504 w
, h
, cpp
, logic_op
);
505 if (!use_fast_copy_blit
&&
506 (src_tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
||
507 dst_tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
))
510 if (use_fast_copy_blit
) {
511 assert(logic_op
== GL_COPY
);
513 /* When two sequential fast copy blits have different source surfaces,
514 * but their destinations refer to the same destination surfaces and
515 * therefore destinations overlap it is imperative that a flush be
516 * inserted between the two blits.
518 * FIXME: Figure out a way to avoid flushing when not required.
520 brw_emit_mi_flush(brw
);
523 BR13
= br13_for_cpp(cpp
);
525 if (src_tr_mode
== INTEL_MIPTREE_TRMODE_YF
)
526 BR13
|= XY_FAST_SRC_TRMODE_YF
;
528 if (dst_tr_mode
== INTEL_MIPTREE_TRMODE_YF
)
529 BR13
|= XY_FAST_DST_TRMODE_YF
;
531 CMD
= xy_blit_cmd(src_tiling
, src_tr_mode
,
532 dst_tiling
, dst_tr_mode
,
533 cpp
, use_fast_copy_blit
);
536 /* For big formats (such as floating point), do the copy using 16 or
537 * 32bpp and multiply the coordinates.
546 assert(cpp
% 4 == 0);
554 if (!alignment_valid(brw
, dst_offset
, dst_tiling
))
556 if (!alignment_valid(brw
, src_offset
, src_tiling
))
559 /* Blit pitch must be dword-aligned. Otherwise, the hardware appears to drop
560 * the low bits. Offsets must be naturally aligned.
562 if (src_pitch
% 4 != 0 || src_offset
% cpp
!= 0 ||
563 dst_pitch
% 4 != 0 || dst_offset
% cpp
!= 0)
567 BR13
= br13_for_cpp(cpp
) | translate_raster_op(logic_op
) << 16;
569 CMD
= xy_blit_cmd(src_tiling
, src_tr_mode
,
570 dst_tiling
, dst_tr_mode
,
571 cpp
, use_fast_copy_blit
);
574 /* For tiled source and destination, pitch value should be specified
575 * as a number of Dwords.
577 if (dst_tiling
!= I915_TILING_NONE
)
580 if (src_tiling
!= I915_TILING_NONE
)
583 if (dst_y2
<= dst_y
|| dst_x2
<= dst_x
)
586 assert(dst_x
< dst_x2
);
587 assert(dst_y
< dst_y2
);
588 assert(src_offset
+ (src_y
+ h
- 1) * abs(src_pitch
) +
589 (w
* cpp
) <= src_buffer
->size
);
590 assert(dst_offset
+ (dst_y
+ h
- 1) * abs(dst_pitch
) +
591 (w
* cpp
) <= dst_buffer
->size
);
593 BEGIN_BATCH_BLT_TILED(length
, dst_y_tiled
, src_y_tiled
);
594 OUT_BATCH(CMD
| (length
- 2));
595 OUT_BATCH(BR13
| (uint16_t)dst_pitch
);
596 OUT_BATCH(SET_FIELD(dst_y
, BLT_Y
) | SET_FIELD(dst_x
, BLT_X
));
597 OUT_BATCH(SET_FIELD(dst_y2
, BLT_Y
) | SET_FIELD(dst_x2
, BLT_X
));
599 OUT_RELOC64(dst_buffer
,
600 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
603 OUT_RELOC(dst_buffer
,
604 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
607 OUT_BATCH(SET_FIELD(src_y
, BLT_Y
) | SET_FIELD(src_x
, BLT_X
));
608 OUT_BATCH((uint16_t)src_pitch
);
610 OUT_RELOC64(src_buffer
,
611 I915_GEM_DOMAIN_RENDER
, 0,
614 OUT_RELOC(src_buffer
,
615 I915_GEM_DOMAIN_RENDER
, 0,
619 ADVANCE_BATCH_TILED(dst_y_tiled
, src_y_tiled
);
621 brw_emit_mi_flush(brw
);
627 intelEmitImmediateColorExpandBlit(struct brw_context
*brw
,
629 GLubyte
*src_bits
, GLuint src_size
,
632 drm_intel_bo
*dst_buffer
,
635 GLshort x
, GLshort y
,
636 GLshort w
, GLshort h
,
639 int dwords
= ALIGN(src_size
, 8) / 4;
640 uint32_t opcode
, br13
, blit_cmd
;
642 if (dst_tiling
!= I915_TILING_NONE
) {
643 if (dst_offset
& 4095)
645 if (dst_tiling
== I915_TILING_Y
)
649 assert((logic_op
>= GL_CLEAR
) && (logic_op
<= (GL_CLEAR
+ 0x0f)));
650 assert(dst_pitch
> 0);
655 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
657 dst_buffer
, dst_pitch
, dst_offset
, x
, y
, w
, h
, src_size
, dwords
);
659 unsigned xy_setup_blt_length
= brw
->gen
>= 8 ? 10 : 8;
660 intel_batchbuffer_require_space(brw
, (xy_setup_blt_length
* 4) +
661 (3 * 4) + dwords
* 4, BLT_RING
);
663 opcode
= XY_SETUP_BLT_CMD
;
665 opcode
|= XY_BLT_WRITE_ALPHA
| XY_BLT_WRITE_RGB
;
666 if (dst_tiling
!= I915_TILING_NONE
) {
667 opcode
|= XY_DST_TILED
;
671 br13
= dst_pitch
| (translate_raster_op(logic_op
) << 16) | (1 << 29);
672 br13
|= br13_for_cpp(cpp
);
674 blit_cmd
= XY_TEXT_IMMEDIATE_BLIT_CMD
| XY_TEXT_BYTE_PACKED
; /* packing? */
675 if (dst_tiling
!= I915_TILING_NONE
)
676 blit_cmd
|= XY_DST_TILED
;
678 BEGIN_BATCH_BLT(xy_setup_blt_length
+ 3);
679 OUT_BATCH(opcode
| (xy_setup_blt_length
- 2));
681 OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
682 OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
684 OUT_RELOC64(dst_buffer
,
685 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
688 OUT_RELOC(dst_buffer
,
689 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
692 OUT_BATCH(0); /* bg */
693 OUT_BATCH(fg_color
); /* fg */
694 OUT_BATCH(0); /* pattern base addr */
698 OUT_BATCH(blit_cmd
| ((3 - 2) + dwords
));
699 OUT_BATCH(SET_FIELD(y
, BLT_Y
) | SET_FIELD(x
, BLT_X
));
700 OUT_BATCH(SET_FIELD(y
+ h
, BLT_Y
) | SET_FIELD(x
+ w
, BLT_X
));
703 intel_batchbuffer_data(brw
, src_bits
, dwords
* 4, BLT_RING
);
705 brw_emit_mi_flush(brw
);
710 /* We don't have a memmove-type blit like some other hardware, so we'll do a
711 * rectangular blit covering a large space, then emit 1-scanline blit at the
712 * end to cover the last if we need.
715 intel_emit_linear_blit(struct brw_context
*brw
,
716 drm_intel_bo
*dst_bo
,
717 unsigned int dst_offset
,
718 drm_intel_bo
*src_bo
,
719 unsigned int src_offset
,
722 struct gl_context
*ctx
= &brw
->ctx
;
723 GLuint pitch
, height
;
724 int16_t src_x
, dst_x
;
728 /* The pitch given to the GPU must be DWORD aligned, and
729 * we want width to match pitch. Max width is (1 << 15 - 1),
730 * rounding that down to the nearest DWORD is 1 << 15 - 4
732 pitch
= ROUND_DOWN_TO(MIN2(size
, (1 << 15) - 64), 4);
733 height
= (size
< pitch
|| pitch
== 0) ? 1 : size
/ pitch
;
735 src_x
= src_offset
% 64;
736 dst_x
= dst_offset
% 64;
737 pitch
= ALIGN(MIN2(size
, (1 << 15) - 64), 4);
738 assert(src_x
+ pitch
< 1 << 15);
739 assert(dst_x
+ pitch
< 1 << 15);
741 ok
= intelEmitCopyBlit(brw
, 1,
742 pitch
, src_bo
, src_offset
- src_x
, I915_TILING_NONE
,
743 INTEL_MIPTREE_TRMODE_NONE
,
744 pitch
, dst_bo
, dst_offset
- dst_x
, I915_TILING_NONE
,
745 INTEL_MIPTREE_TRMODE_NONE
,
746 src_x
, 0, /* src x/y */
747 dst_x
, 0, /* dst x/y */
748 MIN2(size
, pitch
), height
, /* w, h */
751 _mesa_problem(ctx
, "Failed to linear blit %dx%d\n",
752 MIN2(size
, pitch
), height
);
767 * Used to initialize the alpha value of an ARGB8888 miptree after copying
768 * into it from an XRGB8888 source.
770 * This is very common with glCopyTexImage2D(). Note that the coordinates are
771 * relative to the start of the miptree, not relative to a slice within the
775 intel_miptree_set_alpha_to_one(struct brw_context
*brw
,
776 struct intel_mipmap_tree
*mt
,
777 int x
, int y
, int width
, int height
)
781 drm_intel_bo
*aper_array
[2];
786 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
787 __func__
, mt
->bo
, pitch
, x
, y
, width
, height
);
789 BR13
= br13_for_cpp(cpp
) | 0xf0 << 16;
790 CMD
= XY_COLOR_BLT_CMD
;
791 CMD
|= XY_BLT_WRITE_ALPHA
;
793 if (mt
->tiling
!= I915_TILING_NONE
) {
799 /* do space check before going any further */
800 aper_array
[0] = brw
->batch
.bo
;
801 aper_array
[1] = mt
->bo
;
803 if (drm_intel_bufmgr_check_aperture_space(aper_array
,
804 ARRAY_SIZE(aper_array
)) != 0) {
805 intel_batchbuffer_flush(brw
);
808 unsigned length
= brw
->gen
>= 8 ? 7 : 6;
809 bool dst_y_tiled
= mt
->tiling
== I915_TILING_Y
;
811 BEGIN_BATCH_BLT_TILED(length
, dst_y_tiled
, false);
812 OUT_BATCH(CMD
| (length
- 2));
814 OUT_BATCH(SET_FIELD(y
, BLT_Y
) | SET_FIELD(x
, BLT_X
));
815 OUT_BATCH(SET_FIELD(y
+ height
, BLT_Y
) | SET_FIELD(x
+ width
, BLT_X
));
818 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
822 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
825 OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
826 ADVANCE_BATCH_TILED(dst_y_tiled
, false);
828 brw_emit_mi_flush(brw
);