src/mesa/drivers/dri/i965/intel_blit.c

   1 /*
   2  * Copyright 2003 VMware, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include "main/mtypes.h"
  27 #include "main/blit.h"
  28 #include "main/context.h"
  29 #include "main/enums.h"
  30 #include "main/fbobject.h"
  31
  32 #include "brw_context.h"
  33 #include "brw_defines.h"
  34 #include "intel_blit.h"
  35 #include "intel_buffers.h"
  36 #include "intel_fbo.h"
  37 #include "intel_reg.h"
  38 #include "intel_batchbuffer.h"
  39 #include "intel_mipmap_tree.h"
  40
  41 #define FILE_DEBUG_FLAG DEBUG_BLIT
  42
  43 #define SET_TILING_XY_FAST_COPY_BLT(tiling, tr_mode, type)           \
  44 ({                                                                   \
  45    switch (tiling) {                                                 \
  46    case I915_TILING_X:                                               \
  47       CMD |= type ## _TILED_X;                                       \
  48       break;                                                         \
  49    case I915_TILING_Y:                                               \
  50       if (tr_mode == INTEL_MIPTREE_TRMODE_YS)                        \
  51          CMD |= type ## _TILED_64K;                                  \
  52       else                                                           \
  53          CMD |= type ## _TILED_Y;                                    \
  54       break;                                                         \
  55    default:                                                          \
  56       unreachable("not reached");                                    \
  57    }                                                                 \
  58 })
  59
  60 static void
  61 intel_miptree_set_alpha_to_one(struct brw_context *brw,
  62                                struct intel_mipmap_tree *mt,
  63                                int x, int y, int width, int height);
  64
  65 static GLuint translate_raster_op(GLenum logicop)
  66 {
  67    switch(logicop) {
  68    case GL_CLEAR: return 0x00;
  69    case GL_AND: return 0x88;
  70    case GL_AND_REVERSE: return 0x44;
  71    case GL_COPY: return 0xCC;
  72    case GL_AND_INVERTED: return 0x22;
  73    case GL_NOOP: return 0xAA;
  74    case GL_XOR: return 0x66;
  75    case GL_OR: return 0xEE;
  76    case GL_NOR: return 0x11;
  77    case GL_EQUIV: return 0x99;
  78    case GL_INVERT: return 0x55;
  79    case GL_OR_REVERSE: return 0xDD;
  80    case GL_COPY_INVERTED: return 0x33;
  81    case GL_OR_INVERTED: return 0xBB;
  82    case GL_NAND: return 0x77;
  83    case GL_SET: return 0xFF;
  84    default: return 0;
  85    }
  86 }
  87
  88 static uint32_t
  89 br13_for_cpp(int cpp)
  90 {
  91    switch (cpp) {
  92    case 16:
  93       return BR13_32323232;
  94    case 8:
  95       return BR13_16161616;
  96    case 4:
  97       return BR13_8888;
  98    case 2:
  99       return BR13_565;
 100    case 1:
 101       return BR13_8;
 102    default:
 103       unreachable("not reached");
 104    }
 105 }
 106
 107 static uint32_t
 108 get_tr_horizontal_align(uint32_t tr_mode, uint32_t cpp, bool is_src) {
 109    /* Alignment tables for YF/YS tiled surfaces. */
 110    const uint32_t align_2d_yf[] = {64, 64, 32, 32, 16};
 111    const uint32_t bpp = cpp * 8;
 112    const uint32_t shift = is_src ? 17 : 10;
 113    uint32_t align;
 114    int i = 0;
 115
 116    if (tr_mode == INTEL_MIPTREE_TRMODE_NONE)
 117       return 0;
 118
 119    /* Compute array index. */
 120    assert (bpp >= 8 && bpp <= 128 && _mesa_is_pow_two(bpp));
 121    i = ffs(bpp / 8) - 1;
 122
 123    align = tr_mode == INTEL_MIPTREE_TRMODE_YF ?
 124            align_2d_yf[i] :
 125            4 * align_2d_yf[i];
 126
 127    assert(_mesa_is_pow_two(align));
 128
 129    /* XY_FAST_COPY_BLT doesn't support horizontal alignment of 16. */
 130    if (align == 16)
 131       align = 32;
 132
 133    return (ffs(align) - 6) << shift;
 134 }
 135
 136 static uint32_t
 137 get_tr_vertical_align(uint32_t tr_mode, uint32_t cpp, bool is_src) {
 138    /* Vertical alignment tables for YF/YS tiled surfaces. */
 139    const unsigned align_2d_yf[] = {64, 32, 32, 16, 16};
 140    const uint32_t bpp = cpp * 8;
 141    const uint32_t shift = is_src ? 15 : 8;
 142    uint32_t align;
 143    int i = 0;
 144
 145    if (tr_mode == INTEL_MIPTREE_TRMODE_NONE)
 146       return 0;
 147
 148    /* Compute array index. */
 149    assert (bpp >= 8 && bpp <= 128 && _mesa_is_pow_two(bpp));
 150    i = ffs(bpp / 8) - 1;
 151
 152    align = tr_mode == INTEL_MIPTREE_TRMODE_YF ?
 153            align_2d_yf[i] :
 154            4 * align_2d_yf[i];
 155
 156    assert(_mesa_is_pow_two(align));
 157
 158    /* XY_FAST_COPY_BLT doesn't support vertical alignments of 16 and 32. */
 159    if (align == 16 || align == 32)
 160       align = 64;
 161
 162    return (ffs(align) - 7) << shift;
 163 }
 164
 165 /**
 166  * Emits the packet for switching the blitter from X to Y tiled or back.
 167  *
 168  * This has to be called in a single BEGIN_BATCH_BLT_TILED() /
 169  * ADVANCE_BATCH_TILED().  This is because BCS_SWCTRL is saved and restored as
 170  * part of the power context, not a render context, and if the batchbuffer was
 171  * to get flushed between setting and blitting, or blitting and restoring, our
 172  * tiling state would leak into other unsuspecting applications (like the X
 173  * server).
 174  */
 175 static uint32_t *
 176 set_blitter_tiling(struct brw_context *brw,
 177                    bool dst_y_tiled, bool src_y_tiled,
 178                    uint32_t *__map)
 179 {
 180    assert(brw->gen >= 6);
 181
 182    /* Idle the blitter before we update how tiling is interpreted. */
 183    OUT_BATCH(MI_FLUSH_DW);
 184    OUT_BATCH(0);
 185    OUT_BATCH(0);
 186    OUT_BATCH(0);
 187
 188    OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
 189    OUT_BATCH(BCS_SWCTRL);
 190    OUT_BATCH((BCS_SWCTRL_DST_Y | BCS_SWCTRL_SRC_Y) << 16 |
 191              (dst_y_tiled ? BCS_SWCTRL_DST_Y : 0) |
 192              (src_y_tiled ? BCS_SWCTRL_SRC_Y : 0));
 193    return __map;
 194 }
 195 #define SET_BLITTER_TILING(...) __map = set_blitter_tiling(__VA_ARGS__, __map)
 196
 197 #define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled)              \
 198       BEGIN_BATCH_BLT(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0));     \
 199       if (dst_y_tiled || src_y_tiled)                                   \
 200          SET_BLITTER_TILING(brw, dst_y_tiled, src_y_tiled)
 201
 202 #define ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled)                   \
 203       if (dst_y_tiled || src_y_tiled)                                   \
 204          SET_BLITTER_TILING(brw, false, false);                         \
 205       ADVANCE_BATCH()
 206
 207 static int
 208 blt_pitch(struct intel_mipmap_tree *mt)
 209 {
 210    int pitch = mt->pitch;
 211    if (mt->tiling)
 212       pitch /= 4;
 213    return pitch;
 214 }
 215
 216 bool
 217 intel_miptree_blit_compatible_formats(mesa_format src, mesa_format dst)
 218 {
 219    /* The BLT doesn't handle sRGB conversion */
 220    assert(src == _mesa_get_srgb_format_linear(src));
 221    assert(dst == _mesa_get_srgb_format_linear(dst));
 222
 223    /* No swizzle or format conversions possible, except... */
 224    if (src == dst)
 225       return true;
 226
 227    /* ...we can either discard the alpha channel when going from A->X,
 228     * or we can fill the alpha channel with 0xff when going from X->A
 229     */
 230    if (src == MESA_FORMAT_B8G8R8A8_UNORM || src == MESA_FORMAT_B8G8R8X8_UNORM)
 231       return (dst == MESA_FORMAT_B8G8R8A8_UNORM ||
 232               dst == MESA_FORMAT_B8G8R8X8_UNORM);
 233
 234    if (src == MESA_FORMAT_R8G8B8A8_UNORM || src == MESA_FORMAT_R8G8B8X8_UNORM)
 235       return (dst == MESA_FORMAT_R8G8B8A8_UNORM ||
 236               dst == MESA_FORMAT_R8G8B8X8_UNORM);
 237
 238    return false;
 239 }
 240
 241 /**
 242  * Implements a rectangular block transfer (blit) of pixels between two
 243  * miptrees.
 244  *
 245  * Our blitter can operate on 1, 2, or 4-byte-per-pixel data, with generous,
 246  * but limited, pitches and sizes allowed.
 247  *
 248  * The src/dst coordinates are relative to the given level/slice of the
 249  * miptree.
 250  *
 251  * If @src_flip or @dst_flip is set, then the rectangle within that miptree
 252  * will be inverted (including scanline order) when copying.  This is common
 253  * in GL when copying between window system and user-created
 254  * renderbuffers/textures.
 255  */
 256 bool
 257 intel_miptree_blit(struct brw_context *brw,
 258                    struct intel_mipmap_tree *src_mt,
 259                    int src_level, int src_slice,
 260                    uint32_t src_x, uint32_t src_y, bool src_flip,
 261                    struct intel_mipmap_tree *dst_mt,
 262                    int dst_level, int dst_slice,
 263                    uint32_t dst_x, uint32_t dst_y, bool dst_flip,
 264                    uint32_t width, uint32_t height,
 265                    GLenum logicop)
 266 {
 267    /* The blitter doesn't understand multisampling at all. */
 268    if (src_mt->num_samples > 0 || dst_mt->num_samples > 0)
 269       return false;
 270
 271    /* No sRGB decode or encode is done by the hardware blitter, which is
 272     * consistent with what we want in the callers (glCopyTexSubImage(),
 273     * glBlitFramebuffer(), texture validation, etc.).
 274     */
 275    mesa_format src_format = _mesa_get_srgb_format_linear(src_mt->format);
 276    mesa_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format);
 277
 278    /* The blitter doesn't support doing any format conversions.  We do also
 279     * support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into
 280     * the X channel don't matter), and XRGB8888 to ARGB8888 by setting the A
 281     * channel to 1.0 at the end.
 282     */
 283    if (!intel_miptree_blit_compatible_formats(src_format, dst_format)) {
 284       perf_debug("%s: Can't use hardware blitter from %s to %s, "
 285                  "falling back.\n", __func__,
 286                  _mesa_get_format_name(src_format),
 287                  _mesa_get_format_name(dst_format));
 288       return false;
 289    }
 290
 291    /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
 292     * Data Size Limitations):
 293     *
 294     *    The BLT engine is capable of transferring very large quantities of
 295     *    graphics data. Any graphics data read from and written to the
 296     *    destination is permitted to represent a number of pixels that
 297     *    occupies up to 65,536 scan lines and up to 32,768 bytes per scan line
 298     *    at the destination. The maximum number of pixels that may be
 299     *    represented per scan line’s worth of graphics data depends on the
 300     *    color depth.
 301     *
 302     * Furthermore, intelEmitCopyBlit (which is called below) uses a signed
 303     * 16-bit integer to represent buffer pitch, so it can only handle buffer
 304     * pitches < 32k. However, the pitch is measured in bytes for linear buffers
 305     * and dwords for tiled buffers.
 306     *
 307     * As a result of these two limitations, we can only use the blitter to do
 308     * this copy when the miptree's pitch is less than 32k linear or 128k tiled.
 309     */
 310    if (blt_pitch(src_mt) >= 32768 || blt_pitch(dst_mt) >= 32768) {
 311       perf_debug("Falling back due to >= 32k/128k pitch\n");
 312       return false;
 313    }
 314
 315    /* The blitter has no idea about HiZ or fast color clears, so we need to
 316     * resolve the miptrees before we do anything.
 317     */
 318    intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_slice);
 319    intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_slice);
 320    intel_miptree_resolve_color(brw, src_mt);
 321    intel_miptree_resolve_color(brw, dst_mt);
 322
 323    if (src_flip)
 324       src_y = minify(src_mt->physical_height0, src_level - src_mt->first_level) - src_y - height;
 325
 326    if (dst_flip)
 327       dst_y = minify(dst_mt->physical_height0, dst_level - dst_mt->first_level) - dst_y - height;
 328
 329    uint32_t src_image_x, src_image_y, dst_image_x, dst_image_y;
 330    intel_miptree_get_image_offset(src_mt, src_level, src_slice,
 331                                   &src_image_x, &src_image_y);
 332    intel_miptree_get_image_offset(dst_mt, dst_level, dst_slice,
 333                                   &dst_image_x, &dst_image_y);
 334    src_x += src_image_x;
 335    src_y += src_image_y;
 336    dst_x += dst_image_x;
 337    dst_y += dst_image_y;
 338
 339    /* The blitter interprets the 16-bit destination x/y as a signed 16-bit
 340     * value. The values we're working with are unsigned, so make sure we don't
 341     * overflow.
 342     */
 343    if (src_x >= 32768 || src_y >= 32768 || dst_x >= 32768 || dst_y >= 32768) {
 344       perf_debug("Falling back due to >=32k offset [src(%d, %d) dst(%d, %d)]\n",
 345                  src_x, src_y, dst_x, dst_y);
 346       return false;
 347    }
 348
 349    if (!intelEmitCopyBlit(brw,
 350                           src_mt->cpp,
 351                           src_flip == dst_flip ? src_mt->pitch : -src_mt->pitch,
 352                           src_mt->bo, src_mt->offset,
 353                           src_mt->tiling,
 354                           src_mt->tr_mode,
 355                           dst_mt->pitch,
 356                           dst_mt->bo, dst_mt->offset,
 357                           dst_mt->tiling,
 358                           dst_mt->tr_mode,
 359                           src_x, src_y,
 360                           dst_x, dst_y,
 361                           width, height,
 362                           logicop)) {
 363       return false;
 364    }
 365
 366    /* XXX This could be done in a single pass using XY_FULL_MONO_PATTERN_BLT */
 367    if (_mesa_get_format_bits(src_format, GL_ALPHA_BITS) == 0 &&
 368        _mesa_get_format_bits(dst_format, GL_ALPHA_BITS) > 0) {
 369       intel_miptree_set_alpha_to_one(brw, dst_mt,
 370                                      dst_x, dst_y,
 371                                      width, height);
 372    }
 373
 374    return true;
 375 }
 376
 377 static bool
 378 alignment_valid(struct brw_context *brw, unsigned offset, uint32_t tiling)
 379 {
 380    /* Tiled buffers must be page-aligned (4K). */
 381    if (tiling != I915_TILING_NONE)
 382       return (offset & 4095) == 0;
 383
 384    /* On Gen8+, linear buffers must be cacheline-aligned. */
 385    if (brw->gen >= 8)
 386       return (offset & 63) == 0;
 387
 388    return true;
 389 }
 390
 391 static bool
 392 can_fast_copy_blit(struct brw_context *brw,
 393                    drm_intel_bo *src_buffer,
 394                    int16_t src_x, int16_t src_y,
 395                    uintptr_t src_offset, uint32_t src_pitch,
 396                    uint32_t src_tiling, uint32_t src_tr_mode,
 397                    drm_intel_bo *dst_buffer,
 398                    int16_t dst_x, int16_t dst_y,
 399                    uintptr_t dst_offset, uint32_t dst_pitch,
 400                    uint32_t dst_tiling, uint32_t dst_tr_mode,
 401                    int16_t w, int16_t h, uint32_t cpp)
 402 {
 403    const bool dst_tiling_none = dst_tiling == I915_TILING_NONE;
 404    const bool src_tiling_none = src_tiling == I915_TILING_NONE;
 405
 406    if (brw->gen < 9)
 407       return false;
 408
 409    if (src_buffer->handle == dst_buffer->handle &&
 410        _mesa_regions_overlap(src_x, src_y, src_x + w, src_y + h,
 411                              dst_x, dst_y, dst_x + w, dst_y + h))
 412       return false;
 413
 414    /* Enable fast copy blit only if the surfaces are Yf/Ys tiled.
 415     * FIXME: Based on performance data, remove this condition later to
 416     * enable for all types of surfaces.
 417     */
 418    if (src_tr_mode == INTEL_MIPTREE_TRMODE_NONE &&
 419        dst_tr_mode == INTEL_MIPTREE_TRMODE_NONE)
 420       return false;
 421
 422    /* The start pixel for Fast Copy blit should be on an OWord boundary. */
 423    if ((dst_x * cpp | src_x * cpp) & 15)
 424       return false;
 425
 426    /* For all surface types buffers must be cacheline-aligned. */
 427    if ((dst_offset | src_offset) & 63)
 428       return false;
 429
 430    /* Color depth greater than 128 bits not supported. */
 431    if (cpp > 16)
 432       return false;
 433
 434    /* For Fast Copy Blits the pitch cannot be a negative number. So, bit 15
 435     * of the destination pitch must be zero.
 436     */
 437    if ((src_pitch >> 15 & 1) != 0 || (dst_pitch >> 15 & 1) != 0)
 438       return false;
 439
 440    /* For Linear surfaces, the pitch has to be an OWord (16byte) multiple. */
 441    if ((src_tiling_none && src_pitch % 16 != 0) ||
 442        (dst_tiling_none && dst_pitch % 16 != 0))
 443       return false;
 444
 445    return true;
 446 }
 447
 448 static uint32_t
 449 xy_blit_cmd(uint32_t src_tiling, uint32_t src_tr_mode,
 450             uint32_t dst_tiling, uint32_t dst_tr_mode,
 451             uint32_t cpp, bool use_fast_copy_blit)
 452 {
 453    uint32_t CMD = 0;
 454
 455    if (use_fast_copy_blit) {
 456       CMD = XY_FAST_COPY_BLT_CMD;
 457
 458       if (dst_tiling != I915_TILING_NONE)
 459          SET_TILING_XY_FAST_COPY_BLT(dst_tiling, dst_tr_mode, XY_FAST_DST);
 460
 461       if (src_tiling != I915_TILING_NONE)
 462          SET_TILING_XY_FAST_COPY_BLT(src_tiling, src_tr_mode, XY_FAST_SRC);
 463
 464       CMD |= get_tr_horizontal_align(src_tr_mode, cpp, true /* is_src */);
 465       CMD |= get_tr_vertical_align(src_tr_mode, cpp, true /* is_src */);
 466
 467       CMD |= get_tr_horizontal_align(dst_tr_mode, cpp, false /* is_src */);
 468       CMD |= get_tr_vertical_align(dst_tr_mode, cpp, false /* is_src */);
 469
 470    } else {
 471       assert(cpp <= 4);
 472       switch (cpp) {
 473       case 1:
 474       case 2:
 475          CMD = XY_SRC_COPY_BLT_CMD;
 476          break;
 477       case 4:
 478          CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 479          break;
 480       default:
 481          unreachable("not reached");
 482       }
 483
 484       if (dst_tiling != I915_TILING_NONE)
 485          CMD |= XY_DST_TILED;
 486
 487       if (src_tiling != I915_TILING_NONE)
 488          CMD |= XY_SRC_TILED;
 489    }
 490    return CMD;
 491 }
 492
 493 /* Copy BitBlt
 494  */
 495 bool
 496 intelEmitCopyBlit(struct brw_context *brw,
 497                   GLuint cpp,
 498                   GLshort src_pitch,
 499                   drm_intel_bo *src_buffer,
 500                   GLuint src_offset,
 501                   uint32_t src_tiling,
 502                   uint32_t src_tr_mode,
 503                   GLshort dst_pitch,
 504                   drm_intel_bo *dst_buffer,
 505                   GLuint dst_offset,
 506                   uint32_t dst_tiling,
 507                   uint32_t dst_tr_mode,
 508                   GLshort src_x, GLshort src_y,
 509                   GLshort dst_x, GLshort dst_y,
 510                   GLshort w, GLshort h,
 511                   GLenum logic_op)
 512 {
 513    GLuint CMD, BR13, pass = 0;
 514    int dst_y2 = dst_y + h;
 515    int dst_x2 = dst_x + w;
 516    drm_intel_bo *aper_array[3];
 517    bool dst_y_tiled = dst_tiling == I915_TILING_Y;
 518    bool src_y_tiled = src_tiling == I915_TILING_Y;
 519    bool use_fast_copy_blit = false;
 520    uint32_t src_tile_w, src_tile_h;
 521    uint32_t dst_tile_w, dst_tile_h;
 522
 523    if ((dst_y_tiled || src_y_tiled) && brw->gen < 6)
 524       return false;
 525
 526    /* do space check before going any further */
 527    do {
 528        aper_array[0] = brw->batch.bo;
 529        aper_array[1] = dst_buffer;
 530        aper_array[2] = src_buffer;
 531
 532        if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
 533            intel_batchbuffer_flush(brw);
 534            pass++;
 535        } else
 536            break;
 537    } while (pass < 2);
 538
 539    if (pass >= 2)
 540       return false;
 541
 542    unsigned length = brw->gen >= 8 ? 10 : 8;
 543
 544    intel_batchbuffer_require_space(brw, length * 4, BLT_RING);
 545    DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
 546        __func__,
 547        src_buffer, src_pitch, src_offset, src_x, src_y,
 548        dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
 549
 550    intel_get_tile_dims(src_tiling, src_tr_mode, cpp, &src_tile_w, &src_tile_h);
 551    intel_get_tile_dims(dst_tiling, dst_tr_mode, cpp, &dst_tile_w, &dst_tile_h);
 552
 553    /* For Tiled surfaces, the pitch has to be a multiple of the Tile width
 554     * (X direction width of the Tile). This is ensured while allocating the
 555     * buffer object.
 556     */
 557    assert(src_tiling == I915_TILING_NONE || (src_pitch % src_tile_w) == 0);
 558    assert(dst_tiling == I915_TILING_NONE || (dst_pitch % dst_tile_w) == 0);
 559
 560    use_fast_copy_blit = can_fast_copy_blit(brw,
 561                                            src_buffer,
 562                                            src_x, src_y,
 563                                            src_offset, src_pitch,
 564                                            src_tiling, src_tr_mode,
 565                                            dst_buffer,
 566                                            dst_x, dst_y,
 567                                            dst_offset, dst_pitch,
 568                                            dst_tiling, dst_tr_mode,
 569                                            w, h, cpp);
 570    assert(use_fast_copy_blit ||
 571           (src_tr_mode == INTEL_MIPTREE_TRMODE_NONE &&
 572            dst_tr_mode == INTEL_MIPTREE_TRMODE_NONE));
 573
 574    if (use_fast_copy_blit) {
 575       /* When two sequential fast copy blits have different source surfaces,
 576        * but their destinations refer to the same destination surfaces and
 577        * therefore destinations overlap it is imperative that a flush be
 578        * inserted between the two blits.
 579        *
 580        * FIXME: Figure out a way to avoid flushing when not required.
 581        */
 582       brw_emit_mi_flush(brw);
 583
 584       assert(cpp <= 16);
 585       BR13 = br13_for_cpp(cpp);
 586
 587       if (src_tr_mode == INTEL_MIPTREE_TRMODE_YF)
 588          BR13 |= XY_FAST_SRC_TRMODE_YF;
 589
 590       if (dst_tr_mode == INTEL_MIPTREE_TRMODE_YF)
 591          BR13 |= XY_FAST_DST_TRMODE_YF;
 592
 593       CMD = xy_blit_cmd(src_tiling, src_tr_mode,
 594                         dst_tiling, dst_tr_mode,
 595                         cpp, use_fast_copy_blit);
 596
 597    } else {
 598       /* For big formats (such as floating point), do the copy using 16 or
 599        * 32bpp and multiply the coordinates.
 600        */
 601       if (cpp > 4) {
 602          if (cpp % 4 == 2) {
 603             dst_x *= cpp / 2;
 604             dst_x2 *= cpp / 2;
 605             src_x *= cpp / 2;
 606             cpp = 2;
 607          } else {
 608             assert(cpp % 4 == 0);
 609             dst_x *= cpp / 4;
 610             dst_x2 *= cpp / 4;
 611             src_x *= cpp / 4;
 612             cpp = 4;
 613          }
 614       }
 615
 616       if (!alignment_valid(brw, dst_offset, dst_tiling))
 617          return false;
 618       if (!alignment_valid(brw, src_offset, src_tiling))
 619          return false;
 620
 621       /* Blit pitch must be dword-aligned.  Otherwise, the hardware appears to drop
 622        * the low bits.  Offsets must be naturally aligned.
 623        */
 624       if (src_pitch % 4 != 0 || src_offset % cpp != 0 ||
 625           dst_pitch % 4 != 0 || dst_offset % cpp != 0)
 626          return false;
 627
 628       assert(cpp <= 4);
 629       BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16;
 630
 631       CMD = xy_blit_cmd(src_tiling, src_tr_mode,
 632                         dst_tiling, dst_tr_mode,
 633                         cpp, use_fast_copy_blit);
 634    }
 635
 636    /* For tiled source and destination, pitch value should be specified
 637     * as a number of Dwords.
 638     */
 639    if (dst_tiling != I915_TILING_NONE)
 640       dst_pitch /= 4;
 641
 642    if (src_tiling != I915_TILING_NONE)
 643       src_pitch /= 4;
 644
 645    if (dst_y2 <= dst_y || dst_x2 <= dst_x)
 646       return true;
 647
 648    assert(dst_x < dst_x2);
 649    assert(dst_y < dst_y2);
 650    assert(src_offset + (src_y + h - 1) * abs(src_pitch) +
 651           (w * cpp) <= src_buffer->size);
 652    assert(dst_offset + (dst_y + h - 1) * abs(dst_pitch) +
 653           (w * cpp) <= dst_buffer->size);
 654
 655    BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, src_y_tiled);
 656    OUT_BATCH(CMD | (length - 2));
 657    OUT_BATCH(BR13 | (uint16_t)dst_pitch);
 658    OUT_BATCH(SET_FIELD(dst_y, BLT_Y) | SET_FIELD(dst_x, BLT_X));
 659    OUT_BATCH(SET_FIELD(dst_y2, BLT_Y) | SET_FIELD(dst_x2, BLT_X));
 660    if (brw->gen >= 8) {
 661       OUT_RELOC64(dst_buffer,
 662                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 663                   dst_offset);
 664    } else {
 665       OUT_RELOC(dst_buffer,
 666                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 667                 dst_offset);
 668    }
 669    OUT_BATCH(SET_FIELD(src_y, BLT_Y) | SET_FIELD(src_x, BLT_X));
 670    OUT_BATCH((uint16_t)src_pitch);
 671    if (brw->gen >= 8) {
 672       OUT_RELOC64(src_buffer,
 673                   I915_GEM_DOMAIN_RENDER, 0,
 674                   src_offset);
 675    } else {
 676       OUT_RELOC(src_buffer,
 677                 I915_GEM_DOMAIN_RENDER, 0,
 678                 src_offset);
 679    }
 680
 681    ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled);
 682
 683    brw_emit_mi_flush(brw);
 684
 685    return true;
 686 }
 687
 688 bool
 689 intelEmitImmediateColorExpandBlit(struct brw_context *brw,
 690                                   GLuint cpp,
 691                                   GLubyte *src_bits, GLuint src_size,
 692                                   GLuint fg_color,
 693                                   GLshort dst_pitch,
 694                                   drm_intel_bo *dst_buffer,
 695                                   GLuint dst_offset,
 696                                   uint32_t dst_tiling,
 697                                   GLshort x, GLshort y,
 698                                   GLshort w, GLshort h,
 699                                   GLenum logic_op)
 700 {
 701    int dwords = ALIGN(src_size, 8) / 4;
 702    uint32_t opcode, br13, blit_cmd;
 703
 704    if (dst_tiling != I915_TILING_NONE) {
 705       if (dst_offset & 4095)
 706          return false;
 707       if (dst_tiling == I915_TILING_Y)
 708          return false;
 709    }
 710
 711    assert((logic_op >= GL_CLEAR) && (logic_op <= (GL_CLEAR + 0x0f)));
 712    assert(dst_pitch > 0);
 713
 714    if (w < 0 || h < 0)
 715       return true;
 716
 717    DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
 718        __func__,
 719        dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
 720
 721    unsigned xy_setup_blt_length = brw->gen >= 8 ? 10 : 8;
 722    intel_batchbuffer_require_space(brw, (xy_setup_blt_length * 4) +
 723                                         (3 * 4) + dwords * 4, BLT_RING);
 724
 725    opcode = XY_SETUP_BLT_CMD;
 726    if (cpp == 4)
 727       opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 728    if (dst_tiling != I915_TILING_NONE) {
 729       opcode |= XY_DST_TILED;
 730       dst_pitch /= 4;
 731    }
 732
 733    br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
 734    br13 |= br13_for_cpp(cpp);
 735
 736    blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
 737    if (dst_tiling != I915_TILING_NONE)
 738       blit_cmd |= XY_DST_TILED;
 739
 740    BEGIN_BATCH_BLT(xy_setup_blt_length + 3);
 741    OUT_BATCH(opcode | (xy_setup_blt_length - 2));
 742    OUT_BATCH(br13);
 743    OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
 744    OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
 745    if (brw->gen >= 8) {
 746       OUT_RELOC64(dst_buffer,
 747                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 748                   dst_offset);
 749    } else {
 750       OUT_RELOC(dst_buffer,
 751                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 752                 dst_offset);
 753    }
 754    OUT_BATCH(0); /* bg */
 755    OUT_BATCH(fg_color); /* fg */
 756    OUT_BATCH(0); /* pattern base addr */
 757    if (brw->gen >= 8)
 758       OUT_BATCH(0);
 759
 760    OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
 761    OUT_BATCH(SET_FIELD(y, BLT_Y) | SET_FIELD(x, BLT_X));
 762    OUT_BATCH(SET_FIELD(y + h, BLT_Y) | SET_FIELD(x + w, BLT_X));
 763    ADVANCE_BATCH();
 764
 765    intel_batchbuffer_data(brw, src_bits, dwords * 4, BLT_RING);
 766
 767    brw_emit_mi_flush(brw);
 768
 769    return true;
 770 }
 771
 772 /* We don't have a memmove-type blit like some other hardware, so we'll do a
 773  * rectangular blit covering a large space, then emit 1-scanline blit at the
 774  * end to cover the last if we need.
 775  */
 776 void
 777 intel_emit_linear_blit(struct brw_context *brw,
 778                        drm_intel_bo *dst_bo,
 779                        unsigned int dst_offset,
 780                        drm_intel_bo *src_bo,
 781                        unsigned int src_offset,
 782                        unsigned int size)
 783 {
 784    struct gl_context *ctx = &brw->ctx;
 785    GLuint pitch, height;
 786    int16_t src_x, dst_x;
 787    bool ok;
 788
 789    do {
 790       /* The pitch given to the GPU must be DWORD aligned, and
 791        * we want width to match pitch. Max width is (1 << 15 - 1),
 792        * rounding that down to the nearest DWORD is 1 << 15 - 4
 793        */
 794       pitch = ROUND_DOWN_TO(MIN2(size, (1 << 15) - 64), 4);
 795       height = (size < pitch || pitch == 0) ? 1 : size / pitch;
 796
 797       src_x = src_offset % 64;
 798       dst_x = dst_offset % 64;
 799       pitch = ALIGN(MIN2(size, (1 << 15) - 64), 4);
 800       assert(src_x + pitch < 1 << 15);
 801       assert(dst_x + pitch < 1 << 15);
 802
 803       ok = intelEmitCopyBlit(brw, 1,
 804                              pitch, src_bo, src_offset - src_x, I915_TILING_NONE,
 805                              INTEL_MIPTREE_TRMODE_NONE,
 806                              pitch, dst_bo, dst_offset - dst_x, I915_TILING_NONE,
 807                              INTEL_MIPTREE_TRMODE_NONE,
 808                              src_x, 0, /* src x/y */
 809                              dst_x, 0, /* dst x/y */
 810                              MIN2(size, pitch), height, /* w, h */
 811                              GL_COPY);
 812       if (!ok) {
 813          _mesa_problem(ctx, "Failed to linear blit %dx%d\n",
 814                        MIN2(size, pitch), height);
 815          return;
 816       }
 817
 818       pitch *= height;
 819       if (size <= pitch)
 820          return;
 821
 822       src_offset += pitch;
 823       dst_offset += pitch;
 824       size -= pitch;
 825    } while (1);
 826 }
 827
 828 /**
 829  * Used to initialize the alpha value of an ARGB8888 miptree after copying
 830  * into it from an XRGB8888 source.
 831  *
 832  * This is very common with glCopyTexImage2D().  Note that the coordinates are
 833  * relative to the start of the miptree, not relative to a slice within the
 834  * miptree.
 835  */
 836 static void
 837 intel_miptree_set_alpha_to_one(struct brw_context *brw,
 838                               struct intel_mipmap_tree *mt,
 839                               int x, int y, int width, int height)
 840 {
 841    uint32_t BR13, CMD;
 842    int pitch, cpp;
 843    drm_intel_bo *aper_array[2];
 844
 845    pitch = mt->pitch;
 846    cpp = mt->cpp;
 847
 848    DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
 849        __func__, mt->bo, pitch, x, y, width, height);
 850
 851    BR13 = br13_for_cpp(cpp) | 0xf0 << 16;
 852    CMD = XY_COLOR_BLT_CMD;
 853    CMD |= XY_BLT_WRITE_ALPHA;
 854
 855    if (mt->tiling != I915_TILING_NONE) {
 856       CMD |= XY_DST_TILED;
 857       pitch /= 4;
 858    }
 859    BR13 |= pitch;
 860
 861    /* do space check before going any further */
 862    aper_array[0] = brw->batch.bo;
 863    aper_array[1] = mt->bo;
 864
 865    if (drm_intel_bufmgr_check_aperture_space(aper_array,
 866                                              ARRAY_SIZE(aper_array)) != 0) {
 867       intel_batchbuffer_flush(brw);
 868    }
 869
 870    unsigned length = brw->gen >= 8 ? 7 : 6;
 871    bool dst_y_tiled = mt->tiling == I915_TILING_Y;
 872
 873    BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, false);
 874    OUT_BATCH(CMD | (length - 2));
 875    OUT_BATCH(BR13);
 876    OUT_BATCH(SET_FIELD(y, BLT_Y) | SET_FIELD(x, BLT_X));
 877    OUT_BATCH(SET_FIELD(y + height, BLT_Y) | SET_FIELD(x + width, BLT_X));
 878    if (brw->gen >= 8) {
 879       OUT_RELOC64(mt->bo,
 880                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 881                   0);
 882    } else {
 883       OUT_RELOC(mt->bo,
 884                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 885                 0);
 886    }
 887    OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
 888    ADVANCE_BATCH_TILED(dst_y_tiled, false);
 889
 890    brw_emit_mi_flush(brw);
 891 }