src/mesa/drivers/dri/i965/intel_blit.c

   1 /*
   2  * Copyright 2003 VMware, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include "main/mtypes.h"
  27 #include "main/blit.h"
  28 #include "main/context.h"
  29 #include "main/enums.h"
  30 #include "main/fbobject.h"
  31
  32 #include "brw_context.h"
  33 #include "brw_defines.h"
  34 #include "intel_blit.h"
  35 #include "intel_buffers.h"
  36 #include "intel_fbo.h"
  37 #include "intel_reg.h"
  38 #include "intel_batchbuffer.h"
  39 #include "intel_mipmap_tree.h"
  40
  41 #define FILE_DEBUG_FLAG DEBUG_BLIT
  42
  43 #define SET_TILING_XY_FAST_COPY_BLT(tiling, tr_mode, type)           \
  44 ({                                                                   \
  45    switch (tiling) {                                                 \
  46    case I915_TILING_X:                                               \
  47       CMD |= type ## _TILED_X;                                       \
  48       break;                                                         \
  49    case I915_TILING_Y:                                               \
  50       if (tr_mode == INTEL_MIPTREE_TRMODE_YS)                        \
  51          CMD |= type ## _TILED_64K;                                  \
  52       else                                                           \
  53          CMD |= type ## _TILED_Y;                                    \
  54       break;                                                         \
  55    default:                                                          \
  56       unreachable("not reached");                                    \
  57    }                                                                 \
  58 })
  59
  60 static void
  61 intel_miptree_set_alpha_to_one(struct brw_context *brw,
  62                                struct intel_mipmap_tree *mt,
  63                                int x, int y, int width, int height);
  64
  65 static GLuint translate_raster_op(GLenum logicop)
  66 {
  67    switch(logicop) {
  68    case GL_CLEAR: return 0x00;
  69    case GL_AND: return 0x88;
  70    case GL_AND_REVERSE: return 0x44;
  71    case GL_COPY: return 0xCC;
  72    case GL_AND_INVERTED: return 0x22;
  73    case GL_NOOP: return 0xAA;
  74    case GL_XOR: return 0x66;
  75    case GL_OR: return 0xEE;
  76    case GL_NOR: return 0x11;
  77    case GL_EQUIV: return 0x99;
  78    case GL_INVERT: return 0x55;
  79    case GL_OR_REVERSE: return 0xDD;
  80    case GL_COPY_INVERTED: return 0x33;
  81    case GL_OR_INVERTED: return 0xBB;
  82    case GL_NAND: return 0x77;
  83    case GL_SET: return 0xFF;
  84    default: return 0;
  85    }
  86 }
  87
  88 static uint32_t
  89 br13_for_cpp(int cpp)
  90 {
  91    switch (cpp) {
  92    case 16:
  93       return BR13_32323232;
  94    case 8:
  95       return BR13_16161616;
  96    case 4:
  97       return BR13_8888;
  98    case 2:
  99       return BR13_565;
 100    case 1:
 101       return BR13_8;
 102    default:
 103       unreachable("not reached");
 104    }
 105 }
 106
 107 /**
 108  * Emits the packet for switching the blitter from X to Y tiled or back.
 109  *
 110  * This has to be called in a single BEGIN_BATCH_BLT_TILED() /
 111  * ADVANCE_BATCH_TILED().  This is because BCS_SWCTRL is saved and restored as
 112  * part of the power context, not a render context, and if the batchbuffer was
 113  * to get flushed between setting and blitting, or blitting and restoring, our
 114  * tiling state would leak into other unsuspecting applications (like the X
 115  * server).
 116  */
 117 static uint32_t *
 118 set_blitter_tiling(struct brw_context *brw,
 119                    bool dst_y_tiled, bool src_y_tiled,
 120                    uint32_t *__map)
 121 {
 122    assert(brw->gen >= 6);
 123
 124    /* Idle the blitter before we update how tiling is interpreted. */
 125    OUT_BATCH(MI_FLUSH_DW);
 126    OUT_BATCH(0);
 127    OUT_BATCH(0);
 128    OUT_BATCH(0);
 129
 130    OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
 131    OUT_BATCH(BCS_SWCTRL);
 132    OUT_BATCH((BCS_SWCTRL_DST_Y | BCS_SWCTRL_SRC_Y) << 16 |
 133              (dst_y_tiled ? BCS_SWCTRL_DST_Y : 0) |
 134              (src_y_tiled ? BCS_SWCTRL_SRC_Y : 0));
 135    return __map;
 136 }
 137 #define SET_BLITTER_TILING(...) __map = set_blitter_tiling(__VA_ARGS__, __map)
 138
 139 #define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled)              \
 140       BEGIN_BATCH_BLT(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0));     \
 141       if (dst_y_tiled || src_y_tiled)                                   \
 142          SET_BLITTER_TILING(brw, dst_y_tiled, src_y_tiled)
 143
 144 #define ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled)                   \
 145       if (dst_y_tiled || src_y_tiled)                                   \
 146          SET_BLITTER_TILING(brw, false, false);                         \
 147       ADVANCE_BATCH()
 148
 149 static int
 150 blt_pitch(struct intel_mipmap_tree *mt)
 151 {
 152    int pitch = mt->pitch;
 153    if (mt->tiling)
 154       pitch /= 4;
 155    return pitch;
 156 }
 157
 158 bool
 159 intel_miptree_blit_compatible_formats(mesa_format src, mesa_format dst)
 160 {
 161    /* The BLT doesn't handle sRGB conversion */
 162    assert(src == _mesa_get_srgb_format_linear(src));
 163    assert(dst == _mesa_get_srgb_format_linear(dst));
 164
 165    /* No swizzle or format conversions possible, except... */
 166    if (src == dst)
 167       return true;
 168
 169    /* ...we can either discard the alpha channel when going from A->X,
 170     * or we can fill the alpha channel with 0xff when going from X->A
 171     */
 172    if (src == MESA_FORMAT_B8G8R8A8_UNORM || src == MESA_FORMAT_B8G8R8X8_UNORM)
 173       return (dst == MESA_FORMAT_B8G8R8A8_UNORM ||
 174               dst == MESA_FORMAT_B8G8R8X8_UNORM);
 175
 176    if (src == MESA_FORMAT_R8G8B8A8_UNORM || src == MESA_FORMAT_R8G8B8X8_UNORM)
 177       return (dst == MESA_FORMAT_R8G8B8A8_UNORM ||
 178               dst == MESA_FORMAT_R8G8B8X8_UNORM);
 179
 180    return false;
 181 }
 182
 183 /**
 184  * Implements a rectangular block transfer (blit) of pixels between two
 185  * miptrees.
 186  *
 187  * Our blitter can operate on 1, 2, or 4-byte-per-pixel data, with generous,
 188  * but limited, pitches and sizes allowed.
 189  *
 190  * The src/dst coordinates are relative to the given level/slice of the
 191  * miptree.
 192  *
 193  * If @src_flip or @dst_flip is set, then the rectangle within that miptree
 194  * will be inverted (including scanline order) when copying.  This is common
 195  * in GL when copying between window system and user-created
 196  * renderbuffers/textures.
 197  */
 198 bool
 199 intel_miptree_blit(struct brw_context *brw,
 200                    struct intel_mipmap_tree *src_mt,
 201                    int src_level, int src_slice,
 202                    uint32_t src_x, uint32_t src_y, bool src_flip,
 203                    struct intel_mipmap_tree *dst_mt,
 204                    int dst_level, int dst_slice,
 205                    uint32_t dst_x, uint32_t dst_y, bool dst_flip,
 206                    uint32_t width, uint32_t height,
 207                    GLenum logicop)
 208 {
 209    /* The blitter doesn't understand multisampling at all. */
 210    if (src_mt->num_samples > 0 || dst_mt->num_samples > 0)
 211       return false;
 212
 213    /* No sRGB decode or encode is done by the hardware blitter, which is
 214     * consistent with what we want in the callers (glCopyTexSubImage(),
 215     * glBlitFramebuffer(), texture validation, etc.).
 216     */
 217    mesa_format src_format = _mesa_get_srgb_format_linear(src_mt->format);
 218    mesa_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format);
 219
 220    /* The blitter doesn't support doing any format conversions.  We do also
 221     * support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into
 222     * the X channel don't matter), and XRGB8888 to ARGB8888 by setting the A
 223     * channel to 1.0 at the end.
 224     */
 225    if (!intel_miptree_blit_compatible_formats(src_format, dst_format)) {
 226       perf_debug("%s: Can't use hardware blitter from %s to %s, "
 227                  "falling back.\n", __func__,
 228                  _mesa_get_format_name(src_format),
 229                  _mesa_get_format_name(dst_format));
 230       return false;
 231    }
 232
 233    /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
 234     * Data Size Limitations):
 235     *
 236     *    The BLT engine is capable of transferring very large quantities of
 237     *    graphics data. Any graphics data read from and written to the
 238     *    destination is permitted to represent a number of pixels that
 239     *    occupies up to 65,536 scan lines and up to 32,768 bytes per scan line
 240     *    at the destination. The maximum number of pixels that may be
 241     *    represented per scan line’s worth of graphics data depends on the
 242     *    color depth.
 243     *
 244     * Furthermore, intelEmitCopyBlit (which is called below) uses a signed
 245     * 16-bit integer to represent buffer pitch, so it can only handle buffer
 246     * pitches < 32k. However, the pitch is measured in bytes for linear buffers
 247     * and dwords for tiled buffers.
 248     *
 249     * As a result of these two limitations, we can only use the blitter to do
 250     * this copy when the miptree's pitch is less than 32k linear or 128k tiled.
 251     */
 252    if (blt_pitch(src_mt) >= 32768 || blt_pitch(dst_mt) >= 32768) {
 253       perf_debug("Falling back due to >= 32k/128k pitch\n");
 254       return false;
 255    }
 256
 257    /* The blitter has no idea about HiZ or fast color clears, so we need to
 258     * resolve the miptrees before we do anything.
 259     */
 260    intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_slice);
 261    intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_slice);
 262    intel_miptree_resolve_color(brw, src_mt, 0);
 263    intel_miptree_resolve_color(brw, dst_mt, 0);
 264
 265    if (src_flip)
 266       src_y = minify(src_mt->physical_height0, src_level - src_mt->first_level) - src_y - height;
 267
 268    if (dst_flip)
 269       dst_y = minify(dst_mt->physical_height0, dst_level - dst_mt->first_level) - dst_y - height;
 270
 271    uint32_t src_image_x, src_image_y, dst_image_x, dst_image_y;
 272    intel_miptree_get_image_offset(src_mt, src_level, src_slice,
 273                                   &src_image_x, &src_image_y);
 274    intel_miptree_get_image_offset(dst_mt, dst_level, dst_slice,
 275                                   &dst_image_x, &dst_image_y);
 276    src_x += src_image_x;
 277    src_y += src_image_y;
 278    dst_x += dst_image_x;
 279    dst_y += dst_image_y;
 280
 281    /* The blitter interprets the 16-bit destination x/y as a signed 16-bit
 282     * value. The values we're working with are unsigned, so make sure we don't
 283     * overflow.
 284     */
 285    if (src_x >= 32768 || src_y >= 32768 || dst_x >= 32768 || dst_y >= 32768) {
 286       perf_debug("Falling back due to >=32k offset [src(%d, %d) dst(%d, %d)]\n",
 287                  src_x, src_y, dst_x, dst_y);
 288       return false;
 289    }
 290
 291    if (!intelEmitCopyBlit(brw,
 292                           src_mt->cpp,
 293                           src_flip == dst_flip ? src_mt->pitch : -src_mt->pitch,
 294                           src_mt->bo, src_mt->offset,
 295                           src_mt->tiling,
 296                           src_mt->tr_mode,
 297                           dst_mt->pitch,
 298                           dst_mt->bo, dst_mt->offset,
 299                           dst_mt->tiling,
 300                           dst_mt->tr_mode,
 301                           src_x, src_y,
 302                           dst_x, dst_y,
 303                           width, height,
 304                           logicop)) {
 305       return false;
 306    }
 307
 308    /* XXX This could be done in a single pass using XY_FULL_MONO_PATTERN_BLT */
 309    if (_mesa_get_format_bits(src_format, GL_ALPHA_BITS) == 0 &&
 310        _mesa_get_format_bits(dst_format, GL_ALPHA_BITS) > 0) {
 311       intel_miptree_set_alpha_to_one(brw, dst_mt,
 312                                      dst_x, dst_y,
 313                                      width, height);
 314    }
 315
 316    return true;
 317 }
 318
 319 static bool
 320 alignment_valid(struct brw_context *brw, unsigned offset, uint32_t tiling)
 321 {
 322    /* Tiled buffers must be page-aligned (4K). */
 323    if (tiling != I915_TILING_NONE)
 324       return (offset & 4095) == 0;
 325
 326    /* On Gen8+, linear buffers must be cacheline-aligned. */
 327    if (brw->gen >= 8)
 328       return (offset & 63) == 0;
 329
 330    return true;
 331 }
 332
 333 static bool
 334 can_fast_copy_blit(struct brw_context *brw,
 335                    drm_intel_bo *src_buffer,
 336                    int16_t src_x, int16_t src_y,
 337                    uintptr_t src_offset, uint32_t src_pitch,
 338                    uint32_t src_tiling, uint32_t src_tr_mode,
 339                    drm_intel_bo *dst_buffer,
 340                    int16_t dst_x, int16_t dst_y,
 341                    uintptr_t dst_offset, uint32_t dst_pitch,
 342                    uint32_t dst_tiling, uint32_t dst_tr_mode,
 343                    int16_t w, int16_t h, uint32_t cpp,
 344                    GLenum logic_op)
 345 {
 346    const bool dst_tiling_none = dst_tiling == I915_TILING_NONE;
 347    const bool src_tiling_none = src_tiling == I915_TILING_NONE;
 348
 349    if (brw->gen < 9)
 350       return false;
 351
 352    /* Enable fast copy blit only if the surfaces are Yf/Ys tiled.
 353     * FIXME: Based on performance data, remove this condition later to
 354     * enable for all types of surfaces.
 355     */
 356    if (src_tr_mode == INTEL_MIPTREE_TRMODE_NONE &&
 357        dst_tr_mode == INTEL_MIPTREE_TRMODE_NONE)
 358
 359    if (logic_op != GL_COPY)
 360       return false;
 361
 362    /* The start pixel for Fast Copy blit should be on an OWord boundary. */
 363    if ((dst_x * cpp | src_x * cpp) & 15)
 364       return false;
 365
 366    /* For all surface types buffers must be cacheline-aligned. */
 367    if ((dst_offset | src_offset) & 63)
 368       return false;
 369
 370    /* Color depths which are not power of 2 or greater than 128 bits are
 371     * not supported.
 372     */
 373    if (!_mesa_is_pow_two(cpp) || cpp > 16)
 374       return false;
 375
 376    /* For Fast Copy Blits the pitch cannot be a negative number. So, bit 15
 377     * of the destination pitch must be zero.
 378     */
 379    if ((src_pitch >> 15 & 1) != 0 || (dst_pitch >> 15 & 1) != 0)
 380       return false;
 381
 382    /* For Linear surfaces, the pitch has to be an OWord (16byte) multiple. */
 383    if ((src_tiling_none && src_pitch % 16 != 0) ||
 384        (dst_tiling_none && dst_pitch % 16 != 0))
 385       return false;
 386
 387    return true;
 388 }
 389
 390 static uint32_t
 391 xy_blit_cmd(uint32_t src_tiling, uint32_t src_tr_mode,
 392             uint32_t dst_tiling, uint32_t dst_tr_mode,
 393             uint32_t cpp, bool use_fast_copy_blit)
 394 {
 395    uint32_t CMD = 0;
 396
 397    if (use_fast_copy_blit) {
 398       CMD = XY_FAST_COPY_BLT_CMD;
 399
 400       if (dst_tiling != I915_TILING_NONE)
 401          SET_TILING_XY_FAST_COPY_BLT(dst_tiling, dst_tr_mode, XY_FAST_DST);
 402
 403       if (src_tiling != I915_TILING_NONE)
 404          SET_TILING_XY_FAST_COPY_BLT(src_tiling, src_tr_mode, XY_FAST_SRC);
 405    } else {
 406       assert(cpp <= 4);
 407       switch (cpp) {
 408       case 1:
 409       case 2:
 410          CMD = XY_SRC_COPY_BLT_CMD;
 411          break;
 412       case 4:
 413          CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 414          break;
 415       default:
 416          unreachable("not reached");
 417       }
 418
 419       if (dst_tiling != I915_TILING_NONE)
 420          CMD |= XY_DST_TILED;
 421
 422       if (src_tiling != I915_TILING_NONE)
 423          CMD |= XY_SRC_TILED;
 424    }
 425    return CMD;
 426 }
 427
 428 /* Copy BitBlt
 429  */
 430 bool
 431 intelEmitCopyBlit(struct brw_context *brw,
 432                   GLuint cpp,
 433                   GLshort src_pitch,
 434                   drm_intel_bo *src_buffer,
 435                   GLuint src_offset,
 436                   uint32_t src_tiling,
 437                   uint32_t src_tr_mode,
 438                   GLshort dst_pitch,
 439                   drm_intel_bo *dst_buffer,
 440                   GLuint dst_offset,
 441                   uint32_t dst_tiling,
 442                   uint32_t dst_tr_mode,
 443                   GLshort src_x, GLshort src_y,
 444                   GLshort dst_x, GLshort dst_y,
 445                   GLshort w, GLshort h,
 446                   GLenum logic_op)
 447 {
 448    GLuint CMD, BR13, pass = 0;
 449    int dst_y2 = dst_y + h;
 450    int dst_x2 = dst_x + w;
 451    drm_intel_bo *aper_array[3];
 452    bool dst_y_tiled = dst_tiling == I915_TILING_Y;
 453    bool src_y_tiled = src_tiling == I915_TILING_Y;
 454    bool use_fast_copy_blit = false;
 455    uint32_t src_tile_w, src_tile_h;
 456    uint32_t dst_tile_w, dst_tile_h;
 457
 458    if ((dst_y_tiled || src_y_tiled) && brw->gen < 6)
 459       return false;
 460
 461    /* do space check before going any further */
 462    do {
 463        aper_array[0] = brw->batch.bo;
 464        aper_array[1] = dst_buffer;
 465        aper_array[2] = src_buffer;
 466
 467        if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
 468            intel_batchbuffer_flush(brw);
 469            pass++;
 470        } else
 471            break;
 472    } while (pass < 2);
 473
 474    if (pass >= 2)
 475       return false;
 476
 477    unsigned length = brw->gen >= 8 ? 10 : 8;
 478
 479    intel_batchbuffer_require_space(brw, length * 4, BLT_RING);
 480    DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
 481        __func__,
 482        src_buffer, src_pitch, src_offset, src_x, src_y,
 483        dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
 484
 485    intel_get_tile_dims(src_tiling, src_tr_mode, cpp, &src_tile_w, &src_tile_h);
 486    intel_get_tile_dims(dst_tiling, dst_tr_mode, cpp, &dst_tile_w, &dst_tile_h);
 487
 488    /* For Tiled surfaces, the pitch has to be a multiple of the Tile width
 489     * (X direction width of the Tile). This is ensured while allocating the
 490     * buffer object.
 491     */
 492    assert(src_tiling == I915_TILING_NONE || (src_pitch % src_tile_w) == 0);
 493    assert(dst_tiling == I915_TILING_NONE || (dst_pitch % dst_tile_w) == 0);
 494
 495    use_fast_copy_blit = can_fast_copy_blit(brw,
 496                                            src_buffer,
 497                                            src_x, src_y,
 498                                            src_offset, src_pitch,
 499                                            src_tiling, src_tr_mode,
 500                                            dst_buffer,
 501                                            dst_x, dst_y,
 502                                            dst_offset, dst_pitch,
 503                                            dst_tiling, dst_tr_mode,
 504                                            w, h, cpp, logic_op);
 505    if (!use_fast_copy_blit &&
 506        (src_tr_mode != INTEL_MIPTREE_TRMODE_NONE ||
 507         dst_tr_mode != INTEL_MIPTREE_TRMODE_NONE))
 508       return false;
 509
 510    if (use_fast_copy_blit) {
 511       assert(logic_op == GL_COPY);
 512
 513       /* When two sequential fast copy blits have different source surfaces,
 514        * but their destinations refer to the same destination surfaces and
 515        * therefore destinations overlap it is imperative that a flush be
 516        * inserted between the two blits.
 517        *
 518        * FIXME: Figure out a way to avoid flushing when not required.
 519        */
 520       brw_emit_mi_flush(brw);
 521
 522       assert(cpp <= 16);
 523       BR13 = br13_for_cpp(cpp);
 524
 525       if (src_tr_mode == INTEL_MIPTREE_TRMODE_YF)
 526          BR13 |= XY_FAST_SRC_TRMODE_YF;
 527
 528       if (dst_tr_mode == INTEL_MIPTREE_TRMODE_YF)
 529          BR13 |= XY_FAST_DST_TRMODE_YF;
 530
 531       CMD = xy_blit_cmd(src_tiling, src_tr_mode,
 532                         dst_tiling, dst_tr_mode,
 533                         cpp, use_fast_copy_blit);
 534
 535    } else {
 536       /* For big formats (such as floating point), do the copy using 16 or
 537        * 32bpp and multiply the coordinates.
 538        */
 539       if (cpp > 4) {
 540          if (cpp % 4 == 2) {
 541             dst_x *= cpp / 2;
 542             dst_x2 *= cpp / 2;
 543             src_x *= cpp / 2;
 544             cpp = 2;
 545          } else {
 546             assert(cpp % 4 == 0);
 547             dst_x *= cpp / 4;
 548             dst_x2 *= cpp / 4;
 549             src_x *= cpp / 4;
 550             cpp = 4;
 551          }
 552       }
 553
 554       if (!alignment_valid(brw, dst_offset, dst_tiling))
 555          return false;
 556       if (!alignment_valid(brw, src_offset, src_tiling))
 557          return false;
 558
 559       /* Blit pitch must be dword-aligned.  Otherwise, the hardware appears to drop
 560        * the low bits.  Offsets must be naturally aligned.
 561        */
 562       if (src_pitch % 4 != 0 || src_offset % cpp != 0 ||
 563           dst_pitch % 4 != 0 || dst_offset % cpp != 0)
 564          return false;
 565
 566       assert(cpp <= 4);
 567       BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16;
 568
 569       CMD = xy_blit_cmd(src_tiling, src_tr_mode,
 570                         dst_tiling, dst_tr_mode,
 571                         cpp, use_fast_copy_blit);
 572    }
 573
 574    /* For tiled source and destination, pitch value should be specified
 575     * as a number of Dwords.
 576     */
 577    if (dst_tiling != I915_TILING_NONE)
 578       dst_pitch /= 4;
 579
 580    if (src_tiling != I915_TILING_NONE)
 581       src_pitch /= 4;
 582
 583    if (dst_y2 <= dst_y || dst_x2 <= dst_x)
 584       return true;
 585
 586    assert(dst_x < dst_x2);
 587    assert(dst_y < dst_y2);
 588    assert(src_offset + (src_y + h - 1) * abs(src_pitch) +
 589           (w * cpp) <= src_buffer->size);
 590    assert(dst_offset + (dst_y + h - 1) * abs(dst_pitch) +
 591           (w * cpp) <= dst_buffer->size);
 592
 593    BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, src_y_tiled);
 594    OUT_BATCH(CMD | (length - 2));
 595    OUT_BATCH(BR13 | (uint16_t)dst_pitch);
 596    OUT_BATCH(SET_FIELD(dst_y, BLT_Y) | SET_FIELD(dst_x, BLT_X));
 597    OUT_BATCH(SET_FIELD(dst_y2, BLT_Y) | SET_FIELD(dst_x2, BLT_X));
 598    if (brw->gen >= 8) {
 599       OUT_RELOC64(dst_buffer,
 600                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 601                   dst_offset);
 602    } else {
 603       OUT_RELOC(dst_buffer,
 604                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 605                 dst_offset);
 606    }
 607    OUT_BATCH(SET_FIELD(src_y, BLT_Y) | SET_FIELD(src_x, BLT_X));
 608    OUT_BATCH((uint16_t)src_pitch);
 609    if (brw->gen >= 8) {
 610       OUT_RELOC64(src_buffer,
 611                   I915_GEM_DOMAIN_RENDER, 0,
 612                   src_offset);
 613    } else {
 614       OUT_RELOC(src_buffer,
 615                 I915_GEM_DOMAIN_RENDER, 0,
 616                 src_offset);
 617    }
 618
 619    ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled);
 620
 621    brw_emit_mi_flush(brw);
 622
 623    return true;
 624 }
 625
 626 bool
 627 intelEmitImmediateColorExpandBlit(struct brw_context *brw,
 628                                   GLuint cpp,
 629                                   GLubyte *src_bits, GLuint src_size,
 630                                   GLuint fg_color,
 631                                   GLshort dst_pitch,
 632                                   drm_intel_bo *dst_buffer,
 633                                   GLuint dst_offset,
 634                                   uint32_t dst_tiling,
 635                                   GLshort x, GLshort y,
 636                                   GLshort w, GLshort h,
 637                                   GLenum logic_op)
 638 {
 639    int dwords = ALIGN(src_size, 8) / 4;
 640    uint32_t opcode, br13, blit_cmd;
 641
 642    if (dst_tiling != I915_TILING_NONE) {
 643       if (dst_offset & 4095)
 644          return false;
 645       if (dst_tiling == I915_TILING_Y)
 646          return false;
 647    }
 648
 649    assert((logic_op >= GL_CLEAR) && (logic_op <= (GL_CLEAR + 0x0f)));
 650    assert(dst_pitch > 0);
 651
 652    if (w < 0 || h < 0)
 653       return true;
 654
 655    DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
 656        __func__,
 657        dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
 658
 659    unsigned xy_setup_blt_length = brw->gen >= 8 ? 10 : 8;
 660    intel_batchbuffer_require_space(brw, (xy_setup_blt_length * 4) +
 661                                         (3 * 4) + dwords * 4, BLT_RING);
 662
 663    opcode = XY_SETUP_BLT_CMD;
 664    if (cpp == 4)
 665       opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 666    if (dst_tiling != I915_TILING_NONE) {
 667       opcode |= XY_DST_TILED;
 668       dst_pitch /= 4;
 669    }
 670
 671    br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
 672    br13 |= br13_for_cpp(cpp);
 673
 674    blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
 675    if (dst_tiling != I915_TILING_NONE)
 676       blit_cmd |= XY_DST_TILED;
 677
 678    BEGIN_BATCH_BLT(xy_setup_blt_length + 3);
 679    OUT_BATCH(opcode | (xy_setup_blt_length - 2));
 680    OUT_BATCH(br13);
 681    OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
 682    OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
 683    if (brw->gen >= 8) {
 684       OUT_RELOC64(dst_buffer,
 685                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 686                   dst_offset);
 687    } else {
 688       OUT_RELOC(dst_buffer,
 689                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 690                 dst_offset);
 691    }
 692    OUT_BATCH(0); /* bg */
 693    OUT_BATCH(fg_color); /* fg */
 694    OUT_BATCH(0); /* pattern base addr */
 695    if (brw->gen >= 8)
 696       OUT_BATCH(0);
 697
 698    OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
 699    OUT_BATCH(SET_FIELD(y, BLT_Y) | SET_FIELD(x, BLT_X));
 700    OUT_BATCH(SET_FIELD(y + h, BLT_Y) | SET_FIELD(x + w, BLT_X));
 701    ADVANCE_BATCH();
 702
 703    intel_batchbuffer_data(brw, src_bits, dwords * 4, BLT_RING);
 704
 705    brw_emit_mi_flush(brw);
 706
 707    return true;
 708 }
 709
 710 /* We don't have a memmove-type blit like some other hardware, so we'll do a
 711  * rectangular blit covering a large space, then emit 1-scanline blit at the
 712  * end to cover the last if we need.
 713  */
 714 void
 715 intel_emit_linear_blit(struct brw_context *brw,
 716                        drm_intel_bo *dst_bo,
 717                        unsigned int dst_offset,
 718                        drm_intel_bo *src_bo,
 719                        unsigned int src_offset,
 720                        unsigned int size)
 721 {
 722    struct gl_context *ctx = &brw->ctx;
 723    GLuint pitch, height;
 724    int16_t src_x, dst_x;
 725    bool ok;
 726
 727    do {
 728       /* The pitch given to the GPU must be DWORD aligned, and
 729        * we want width to match pitch. Max width is (1 << 15 - 1),
 730        * rounding that down to the nearest DWORD is 1 << 15 - 4
 731        */
 732       pitch = ROUND_DOWN_TO(MIN2(size, (1 << 15) - 64), 4);
 733       height = (size < pitch || pitch == 0) ? 1 : size / pitch;
 734
 735       src_x = src_offset % 64;
 736       dst_x = dst_offset % 64;
 737       pitch = ALIGN(MIN2(size, (1 << 15) - 64), 4);
 738       assert(src_x + pitch < 1 << 15);
 739       assert(dst_x + pitch < 1 << 15);
 740
 741       ok = intelEmitCopyBlit(brw, 1,
 742                              pitch, src_bo, src_offset - src_x, I915_TILING_NONE,
 743                              INTEL_MIPTREE_TRMODE_NONE,
 744                              pitch, dst_bo, dst_offset - dst_x, I915_TILING_NONE,
 745                              INTEL_MIPTREE_TRMODE_NONE,
 746                              src_x, 0, /* src x/y */
 747                              dst_x, 0, /* dst x/y */
 748                              MIN2(size, pitch), height, /* w, h */
 749                              GL_COPY);
 750       if (!ok) {
 751          _mesa_problem(ctx, "Failed to linear blit %dx%d\n",
 752                        MIN2(size, pitch), height);
 753          return;
 754       }
 755
 756       pitch *= height;
 757       if (size <= pitch)
 758          return;
 759
 760       src_offset += pitch;
 761       dst_offset += pitch;
 762       size -= pitch;
 763    } while (1);
 764 }
 765
 766 /**
 767  * Used to initialize the alpha value of an ARGB8888 miptree after copying
 768  * into it from an XRGB8888 source.
 769  *
 770  * This is very common with glCopyTexImage2D().  Note that the coordinates are
 771  * relative to the start of the miptree, not relative to a slice within the
 772  * miptree.
 773  */
 774 static void
 775 intel_miptree_set_alpha_to_one(struct brw_context *brw,
 776                               struct intel_mipmap_tree *mt,
 777                               int x, int y, int width, int height)
 778 {
 779    uint32_t BR13, CMD;
 780    int pitch, cpp;
 781    drm_intel_bo *aper_array[2];
 782
 783    pitch = mt->pitch;
 784    cpp = mt->cpp;
 785
 786    DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
 787        __func__, mt->bo, pitch, x, y, width, height);
 788
 789    BR13 = br13_for_cpp(cpp) | 0xf0 << 16;
 790    CMD = XY_COLOR_BLT_CMD;
 791    CMD |= XY_BLT_WRITE_ALPHA;
 792
 793    if (mt->tiling != I915_TILING_NONE) {
 794       CMD |= XY_DST_TILED;
 795       pitch /= 4;
 796    }
 797    BR13 |= pitch;
 798
 799    /* do space check before going any further */
 800    aper_array[0] = brw->batch.bo;
 801    aper_array[1] = mt->bo;
 802
 803    if (drm_intel_bufmgr_check_aperture_space(aper_array,
 804                                              ARRAY_SIZE(aper_array)) != 0) {
 805       intel_batchbuffer_flush(brw);
 806    }
 807
 808    unsigned length = brw->gen >= 8 ? 7 : 6;
 809    bool dst_y_tiled = mt->tiling == I915_TILING_Y;
 810
 811    BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, false);
 812    OUT_BATCH(CMD | (length - 2));
 813    OUT_BATCH(BR13);
 814    OUT_BATCH(SET_FIELD(y, BLT_Y) | SET_FIELD(x, BLT_X));
 815    OUT_BATCH(SET_FIELD(y + height, BLT_Y) | SET_FIELD(x + width, BLT_X));
 816    if (brw->gen >= 8) {
 817       OUT_RELOC64(mt->bo,
 818                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 819                   0);
 820    } else {
 821       OUT_RELOC(mt->bo,
 822                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 823                 0);
 824    }
 825    OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
 826    ADVANCE_BATCH_TILED(dst_y_tiled, false);
 827
 828    brw_emit_mi_flush(brw);
 829 }