src/mesa/drivers/dri/i965/intel_blit.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29 #include "main/mtypes.h"
  30 #include "main/context.h"
  31 #include "main/enums.h"
  32 #include "main/colormac.h"
  33 #include "main/fbobject.h"
  34
  35 #include "brw_context.h"
  36 #include "intel_blit.h"
  37 #include "intel_buffers.h"
  38 #include "intel_fbo.h"
  39 #include "intel_reg.h"
  40 #include "intel_regions.h"
  41 #include "intel_batchbuffer.h"
  42 #include "intel_mipmap_tree.h"
  43
  44 #define FILE_DEBUG_FLAG DEBUG_BLIT
  45
  46 static void
  47 intel_miptree_set_alpha_to_one(struct brw_context *brw,
  48                                struct intel_mipmap_tree *mt,
  49                                int x, int y, int width, int height);
  50
  51 static GLuint translate_raster_op(GLenum logicop)
  52 {
  53    switch(logicop) {
  54    case GL_CLEAR: return 0x00;
  55    case GL_AND: return 0x88;
  56    case GL_AND_REVERSE: return 0x44;
  57    case GL_COPY: return 0xCC;
  58    case GL_AND_INVERTED: return 0x22;
  59    case GL_NOOP: return 0xAA;
  60    case GL_XOR: return 0x66;
  61    case GL_OR: return 0xEE;
  62    case GL_NOR: return 0x11;
  63    case GL_EQUIV: return 0x99;
  64    case GL_INVERT: return 0x55;
  65    case GL_OR_REVERSE: return 0xDD;
  66    case GL_COPY_INVERTED: return 0x33;
  67    case GL_OR_INVERTED: return 0xBB;
  68    case GL_NAND: return 0x77;
  69    case GL_SET: return 0xFF;
  70    default: return 0;
  71    }
  72 }
  73
  74 static uint32_t
  75 br13_for_cpp(int cpp)
  76 {
  77    switch (cpp) {
  78    case 4:
  79       return BR13_8888;
  80       break;
  81    case 2:
  82       return BR13_565;
  83       break;
  84    case 1:
  85       return BR13_8;
  86       break;
  87    default:
  88       assert(0);
  89       return 0;
  90    }
  91 }
  92
  93 /**
  94  * Emits the packet for switching the blitter from X to Y tiled or back.
  95  *
  96  * This has to be called in a single BEGIN_BATCH_BLT_TILED() /
  97  * ADVANCE_BATCH_TILED().  This is because BCS_SWCTRL is saved and restored as
  98  * part of the power context, not a render context, and if the batchbuffer was
  99  * to get flushed between setting and blitting, or blitting and restoring, our
 100  * tiling state would leak into other unsuspecting applications (like the X
 101  * server).
 102  */
 103 static void
 104 set_blitter_tiling(struct brw_context *brw,
 105                    bool dst_y_tiled, bool src_y_tiled)
 106 {
 107    struct intel_context *intel = &brw->intel;
 108    assert(intel->gen >= 6);
 109
 110    /* Idle the blitter before we update how tiling is interpreted. */
 111    OUT_BATCH(MI_FLUSH_DW);
 112    OUT_BATCH(0);
 113    OUT_BATCH(0);
 114    OUT_BATCH(0);
 115
 116    OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
 117    OUT_BATCH(BCS_SWCTRL);
 118    OUT_BATCH((BCS_SWCTRL_DST_Y | BCS_SWCTRL_SRC_Y) << 16 |
 119              (dst_y_tiled ? BCS_SWCTRL_DST_Y : 0) |
 120              (src_y_tiled ? BCS_SWCTRL_SRC_Y : 0));
 121 }
 122
 123 #define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled) do {         \
 124       BEGIN_BATCH_BLT(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0));     \
 125       if (dst_y_tiled || src_y_tiled)                                   \
 126          set_blitter_tiling(brw, dst_y_tiled, src_y_tiled);             \
 127    } while (0)
 128
 129 #define ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled) do {              \
 130       if (dst_y_tiled || src_y_tiled)                                   \
 131          set_blitter_tiling(brw, false, false);                         \
 132       ADVANCE_BATCH();                                                  \
 133    } while (0)
 134
 135 /**
 136  * Implements a rectangular block transfer (blit) of pixels between two
 137  * miptrees.
 138  *
 139  * Our blitter can operate on 1, 2, or 4-byte-per-pixel data, with generous,
 140  * but limited, pitches and sizes allowed.
 141  *
 142  * The src/dst coordinates are relative to the given level/slice of the
 143  * miptree.
 144  *
 145  * If @src_flip or @dst_flip is set, then the rectangle within that miptree
 146  * will be inverted (including scanline order) when copying.  This is common
 147  * in GL when copying between window system and user-created
 148  * renderbuffers/textures.
 149  */
 150 bool
 151 intel_miptree_blit(struct brw_context *brw,
 152                    struct intel_mipmap_tree *src_mt,
 153                    int src_level, int src_slice,
 154                    uint32_t src_x, uint32_t src_y, bool src_flip,
 155                    struct intel_mipmap_tree *dst_mt,
 156                    int dst_level, int dst_slice,
 157                    uint32_t dst_x, uint32_t dst_y, bool dst_flip,
 158                    uint32_t width, uint32_t height,
 159                    GLenum logicop)
 160 {
 161    struct intel_context *intel = &brw->intel;
 162    /* No sRGB decode or encode is done by the hardware blitter, which is
 163     * consistent with what we want in the callers (glCopyTexSubImage(),
 164     * glBlitFramebuffer(), texture validation, etc.).
 165     */
 166    gl_format src_format = _mesa_get_srgb_format_linear(src_mt->format);
 167    gl_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format);
 168
 169    /* The blitter doesn't support doing any format conversions.  We do also
 170     * support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into
 171     * the X channel don't matter), and XRGB8888 to ARGB8888 by setting the A
 172     * channel to 1.0 at the end.
 173     */
 174    if (src_format != dst_format &&
 175       ((src_format != MESA_FORMAT_ARGB8888 &&
 176         src_format != MESA_FORMAT_XRGB8888) ||
 177        (dst_format != MESA_FORMAT_ARGB8888 &&
 178         dst_format != MESA_FORMAT_XRGB8888))) {
 179       perf_debug("%s: Can't use hardware blitter from %s to %s, "
 180                  "falling back.\n", __FUNCTION__,
 181                  _mesa_get_format_name(src_format),
 182                  _mesa_get_format_name(dst_format));
 183       return false;
 184    }
 185
 186    /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
 187     * Data Size Limitations):
 188     *
 189     *    The BLT engine is capable of transferring very large quantities of
 190     *    graphics data. Any graphics data read from and written to the
 191     *    destination is permitted to represent a number of pixels that
 192     *    occupies up to 65,536 scan lines and up to 32,768 bytes per scan line
 193     *    at the destination. The maximum number of pixels that may be
 194     *    represented per scan line’s worth of graphics data depends on the
 195     *    color depth.
 196     *
 197     * Furthermore, intelEmitCopyBlit (which is called below) uses a signed
 198     * 16-bit integer to represent buffer pitch, so it can only handle buffer
 199     * pitches < 32k.
 200     *
 201     * As a result of these two limitations, we can only use the blitter to do
 202     * this copy when the region's pitch is less than 32k.
 203     */
 204    if (src_mt->region->pitch > 32768 ||
 205        dst_mt->region->pitch > 32768) {
 206       perf_debug("Falling back due to >32k pitch\n");
 207       return false;
 208    }
 209
 210    /* The blitter has no idea about HiZ or fast color clears, so we need to
 211     * resolve the miptrees before we do anything.
 212     */
 213    intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_slice);
 214    intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_slice);
 215    intel_miptree_resolve_color(brw, src_mt);
 216    intel_miptree_resolve_color(brw, dst_mt);
 217
 218    if (src_flip)
 219       src_y = src_mt->level[src_level].height - src_y - height;
 220
 221    if (dst_flip)
 222       dst_y = dst_mt->level[dst_level].height - dst_y - height;
 223
 224    int src_pitch = src_mt->region->pitch;
 225    if (src_flip != dst_flip)
 226       src_pitch = -src_pitch;
 227
 228    uint32_t src_image_x, src_image_y;
 229    intel_miptree_get_image_offset(src_mt, src_level, src_slice,
 230                                   &src_image_x, &src_image_y);
 231    src_x += src_image_x;
 232    src_y += src_image_y;
 233
 234    uint32_t dst_image_x, dst_image_y;
 235    intel_miptree_get_image_offset(dst_mt, dst_level, dst_slice,
 236                                   &dst_image_x, &dst_image_y);
 237    dst_x += dst_image_x;
 238    dst_y += dst_image_y;
 239
 240    if (!intelEmitCopyBlit(brw,
 241                           src_mt->cpp,
 242                           src_pitch,
 243                           src_mt->region->bo, src_mt->offset,
 244                           src_mt->region->tiling,
 245                           dst_mt->region->pitch,
 246                           dst_mt->region->bo, dst_mt->offset,
 247                           dst_mt->region->tiling,
 248                           src_x, src_y,
 249                           dst_x, dst_y,
 250                           width, height,
 251                           logicop)) {
 252       return false;
 253    }
 254
 255    if (src_mt->format == MESA_FORMAT_XRGB8888 &&
 256        dst_mt->format == MESA_FORMAT_ARGB8888) {
 257       intel_miptree_set_alpha_to_one(brw, dst_mt,
 258                                      dst_x, dst_y,
 259                                      width, height);
 260    }
 261
 262    return true;
 263 }
 264
 265 /* Copy BitBlt
 266  */
 267 bool
 268 intelEmitCopyBlit(struct brw_context *brw,
 269                   GLuint cpp,
 270                   GLshort src_pitch,
 271                   drm_intel_bo *src_buffer,
 272                   GLuint src_offset,
 273                   uint32_t src_tiling,
 274                   GLshort dst_pitch,
 275                   drm_intel_bo *dst_buffer,
 276                   GLuint dst_offset,
 277                   uint32_t dst_tiling,
 278                   GLshort src_x, GLshort src_y,
 279                   GLshort dst_x, GLshort dst_y,
 280                   GLshort w, GLshort h,
 281                   GLenum logic_op)
 282 {
 283    struct intel_context *intel = &brw->intel;
 284    GLuint CMD, BR13, pass = 0;
 285    int dst_y2 = dst_y + h;
 286    int dst_x2 = dst_x + w;
 287    drm_intel_bo *aper_array[3];
 288    bool dst_y_tiled = dst_tiling == I915_TILING_Y;
 289    bool src_y_tiled = src_tiling == I915_TILING_Y;
 290    BATCH_LOCALS;
 291
 292    if (dst_tiling != I915_TILING_NONE) {
 293       if (dst_offset & 4095)
 294          return false;
 295    }
 296    if (src_tiling != I915_TILING_NONE) {
 297       if (src_offset & 4095)
 298          return false;
 299    }
 300    if ((dst_y_tiled || src_y_tiled) && intel->gen < 6)
 301       return false;
 302
 303    /* do space check before going any further */
 304    do {
 305        aper_array[0] = brw->batch.bo;
 306        aper_array[1] = dst_buffer;
 307        aper_array[2] = src_buffer;
 308
 309        if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
 310            intel_batchbuffer_flush(brw);
 311            pass++;
 312        } else
 313            break;
 314    } while (pass < 2);
 315
 316    if (pass >= 2)
 317       return false;
 318
 319    intel_batchbuffer_require_space(brw, 8 * 4, true);
 320    DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
 321        __FUNCTION__,
 322        src_buffer, src_pitch, src_offset, src_x, src_y,
 323        dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
 324
 325    /* Blit pitch must be dword-aligned.  Otherwise, the hardware appears to drop
 326     * the low bits.
 327     */
 328    if (src_pitch % 4 != 0 || dst_pitch % 4 != 0)
 329       return false;
 330
 331    /* For big formats (such as floating point), do the copy using 16 or 32bpp
 332     * and multiply the coordinates.
 333     */
 334    if (cpp > 4) {
 335       if (cpp % 4 == 2) {
 336          dst_x *= cpp / 2;
 337          dst_x2 *= cpp / 2;
 338          src_x *= cpp / 2;
 339          cpp = 2;
 340       } else {
 341          assert(cpp % 4 == 0);
 342          dst_x *= cpp / 4;
 343          dst_x2 *= cpp / 4;
 344          src_x *= cpp / 4;
 345          cpp = 4;
 346       }
 347    }
 348
 349    BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16;
 350
 351    switch (cpp) {
 352    case 1:
 353    case 2:
 354       CMD = XY_SRC_COPY_BLT_CMD;
 355       break;
 356    case 4:
 357       CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 358       break;
 359    default:
 360       return false;
 361    }
 362
 363    if (dst_tiling != I915_TILING_NONE) {
 364       CMD |= XY_DST_TILED;
 365       dst_pitch /= 4;
 366    }
 367    if (src_tiling != I915_TILING_NONE) {
 368       CMD |= XY_SRC_TILED;
 369       src_pitch /= 4;
 370    }
 371
 372    if (dst_y2 <= dst_y || dst_x2 <= dst_x) {
 373       return true;
 374    }
 375
 376    assert(dst_x < dst_x2);
 377    assert(dst_y < dst_y2);
 378
 379    BEGIN_BATCH_BLT_TILED(8, dst_y_tiled, src_y_tiled);
 380
 381    OUT_BATCH(CMD | (8 - 2));
 382    OUT_BATCH(BR13 | (uint16_t)dst_pitch);
 383    OUT_BATCH((dst_y << 16) | dst_x);
 384    OUT_BATCH((dst_y2 << 16) | dst_x2);
 385    OUT_RELOC_FENCED(dst_buffer,
 386                     I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 387                     dst_offset);
 388    OUT_BATCH((src_y << 16) | src_x);
 389    OUT_BATCH((uint16_t)src_pitch);
 390    OUT_RELOC_FENCED(src_buffer,
 391                     I915_GEM_DOMAIN_RENDER, 0,
 392                     src_offset);
 393
 394    ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled);
 395
 396    intel_batchbuffer_emit_mi_flush(brw);
 397
 398    return true;
 399 }
 400
 401 bool
 402 intelEmitImmediateColorExpandBlit(struct brw_context *brw,
 403                                   GLuint cpp,
 404                                   GLubyte *src_bits, GLuint src_size,
 405                                   GLuint fg_color,
 406                                   GLshort dst_pitch,
 407                                   drm_intel_bo *dst_buffer,
 408                                   GLuint dst_offset,
 409                                   uint32_t dst_tiling,
 410                                   GLshort x, GLshort y,
 411                                   GLshort w, GLshort h,
 412                                   GLenum logic_op)
 413 {
 414    int dwords = ALIGN(src_size, 8) / 4;
 415    uint32_t opcode, br13, blit_cmd;
 416
 417    if (dst_tiling != I915_TILING_NONE) {
 418       if (dst_offset & 4095)
 419          return false;
 420       if (dst_tiling == I915_TILING_Y)
 421          return false;
 422    }
 423
 424    assert( logic_op - GL_CLEAR >= 0 );
 425    assert( logic_op - GL_CLEAR < 0x10 );
 426    assert(dst_pitch > 0);
 427
 428    if (w < 0 || h < 0)
 429       return true;
 430
 431    DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
 432        __FUNCTION__,
 433        dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
 434
 435    intel_batchbuffer_require_space(brw, (8 * 4) + (3 * 4) + dwords * 4, true);
 436
 437    opcode = XY_SETUP_BLT_CMD;
 438    if (cpp == 4)
 439       opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 440    if (dst_tiling != I915_TILING_NONE) {
 441       opcode |= XY_DST_TILED;
 442       dst_pitch /= 4;
 443    }
 444
 445    br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
 446    br13 |= br13_for_cpp(cpp);
 447
 448    blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
 449    if (dst_tiling != I915_TILING_NONE)
 450       blit_cmd |= XY_DST_TILED;
 451
 452    BEGIN_BATCH_BLT(8 + 3);
 453    OUT_BATCH(opcode | (8 - 2));
 454    OUT_BATCH(br13);
 455    OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
 456    OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
 457    OUT_RELOC_FENCED(dst_buffer,
 458                     I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 459                     dst_offset);
 460    OUT_BATCH(0); /* bg */
 461    OUT_BATCH(fg_color); /* fg */
 462    OUT_BATCH(0); /* pattern base addr */
 463
 464    OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
 465    OUT_BATCH((y << 16) | x);
 466    OUT_BATCH(((y + h) << 16) | (x + w));
 467    ADVANCE_BATCH();
 468
 469    intel_batchbuffer_data(brw, src_bits, dwords * 4, true);
 470
 471    intel_batchbuffer_emit_mi_flush(brw);
 472
 473    return true;
 474 }
 475
 476 /* We don't have a memmove-type blit like some other hardware, so we'll do a
 477  * rectangular blit covering a large space, then emit 1-scanline blit at the
 478  * end to cover the last if we need.
 479  */
 480 void
 481 intel_emit_linear_blit(struct brw_context *brw,
 482                        drm_intel_bo *dst_bo,
 483                        unsigned int dst_offset,
 484                        drm_intel_bo *src_bo,
 485                        unsigned int src_offset,
 486                        unsigned int size)
 487 {
 488    struct intel_context *intel = &brw->intel;
 489    struct gl_context *ctx = &intel->ctx;
 490    GLuint pitch, height;
 491    bool ok;
 492
 493    /* The pitch given to the GPU must be DWORD aligned, and
 494     * we want width to match pitch. Max width is (1 << 15 - 1),
 495     * rounding that down to the nearest DWORD is 1 << 15 - 4
 496     */
 497    pitch = ROUND_DOWN_TO(MIN2(size, (1 << 15) - 1), 4);
 498    height = (pitch == 0) ? 1 : size / pitch;
 499    ok = intelEmitCopyBlit(brw, 1,
 500                           pitch, src_bo, src_offset, I915_TILING_NONE,
 501                           pitch, dst_bo, dst_offset, I915_TILING_NONE,
 502                           0, 0, /* src x/y */
 503                           0, 0, /* dst x/y */
 504                           pitch, height, /* w, h */
 505                           GL_COPY);
 506    if (!ok)
 507       _mesa_problem(ctx, "Failed to linear blit %dx%d\n", pitch, height);
 508
 509    src_offset += pitch * height;
 510    dst_offset += pitch * height;
 511    size -= pitch * height;
 512    assert (size < (1 << 15));
 513    pitch = ALIGN(size, 4);
 514    if (size != 0) {
 515       ok = intelEmitCopyBlit(brw, 1,
 516                              pitch, src_bo, src_offset, I915_TILING_NONE,
 517                              pitch, dst_bo, dst_offset, I915_TILING_NONE,
 518                              0, 0, /* src x/y */
 519                              0, 0, /* dst x/y */
 520                              size, 1, /* w, h */
 521                              GL_COPY);
 522       if (!ok)
 523          _mesa_problem(ctx, "Failed to linear blit %dx%d\n", size, 1);
 524    }
 525 }
 526
 527 /**
 528  * Used to initialize the alpha value of an ARGB8888 miptree after copying
 529  * into it from an XRGB8888 source.
 530  *
 531  * This is very common with glCopyTexImage2D().  Note that the coordinates are
 532  * relative to the start of the miptree, not relative to a slice within the
 533  * miptree.
 534  */
 535 static void
 536 intel_miptree_set_alpha_to_one(struct brw_context *brw,
 537                               struct intel_mipmap_tree *mt,
 538                               int x, int y, int width, int height)
 539 {
 540    struct intel_region *region = mt->region;
 541    uint32_t BR13, CMD;
 542    int pitch, cpp;
 543    drm_intel_bo *aper_array[2];
 544    BATCH_LOCALS;
 545
 546    pitch = region->pitch;
 547    cpp = region->cpp;
 548
 549    DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
 550        __FUNCTION__, region->bo, pitch, x, y, width, height);
 551
 552    BR13 = br13_for_cpp(cpp) | 0xf0 << 16;
 553    CMD = XY_COLOR_BLT_CMD;
 554    CMD |= XY_BLT_WRITE_ALPHA;
 555
 556    if (region->tiling != I915_TILING_NONE) {
 557       CMD |= XY_DST_TILED;
 558       pitch /= 4;
 559    }
 560    BR13 |= pitch;
 561
 562    /* do space check before going any further */
 563    aper_array[0] = brw->batch.bo;
 564    aper_array[1] = region->bo;
 565
 566    if (drm_intel_bufmgr_check_aperture_space(aper_array,
 567                                              ARRAY_SIZE(aper_array)) != 0) {
 568       intel_batchbuffer_flush(brw);
 569    }
 570
 571    bool dst_y_tiled = region->tiling == I915_TILING_Y;
 572
 573    BEGIN_BATCH_BLT_TILED(6, dst_y_tiled, false);
 574    OUT_BATCH(CMD | (6 - 2));
 575    OUT_BATCH(BR13);
 576    OUT_BATCH((y << 16) | x);
 577    OUT_BATCH(((y + height) << 16) | (x + width));
 578    OUT_RELOC_FENCED(region->bo,
 579                     I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 580                     0);
 581    OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
 582    ADVANCE_BATCH_TILED(dst_y_tiled, false);
 583
 584    intel_batchbuffer_emit_mi_flush(brw);
 585 }