1 /**************************************************************************
3 * Copyright 2003 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include "main/mtypes.h"
30 #include "main/blit.h"
31 #include "main/context.h"
32 #include "main/enums.h"
33 #include "main/colormac.h"
34 #include "main/fbobject.h"
36 #include "brw_context.h"
37 #include "brw_defines.h"
38 #include "intel_blit.h"
39 #include "intel_buffers.h"
40 #include "intel_fbo.h"
41 #include "intel_reg.h"
42 #include "intel_batchbuffer.h"
43 #include "intel_mipmap_tree.h"
45 #define FILE_DEBUG_FLAG DEBUG_BLIT
47 #define SET_TILING_XY_FAST_COPY_BLT(tiling, tr_mode, type) \
51 CMD |= type ## _TILED_X; \
54 if (tr_mode == INTEL_MIPTREE_TRMODE_YS) \
55 CMD |= type ## _TILED_64K; \
57 CMD |= type ## _TILED_Y; \
60 unreachable("not reached"); \
65 intel_miptree_set_alpha_to_one(struct brw_context
*brw
,
66 struct intel_mipmap_tree
*mt
,
67 int x
, int y
, int width
, int height
);
69 static GLuint
translate_raster_op(GLenum logicop
)
72 case GL_CLEAR
: return 0x00;
73 case GL_AND
: return 0x88;
74 case GL_AND_REVERSE
: return 0x44;
75 case GL_COPY
: return 0xCC;
76 case GL_AND_INVERTED
: return 0x22;
77 case GL_NOOP
: return 0xAA;
78 case GL_XOR
: return 0x66;
79 case GL_OR
: return 0xEE;
80 case GL_NOR
: return 0x11;
81 case GL_EQUIV
: return 0x99;
82 case GL_INVERT
: return 0x55;
83 case GL_OR_REVERSE
: return 0xDD;
84 case GL_COPY_INVERTED
: return 0x33;
85 case GL_OR_INVERTED
: return 0xBB;
86 case GL_NAND
: return 0x77;
87 case GL_SET
: return 0xFF;
107 unreachable("not reached");
112 get_tr_horizontal_align(uint32_t tr_mode
, uint32_t cpp
, bool is_src
) {
113 /* Alignment tables for YF/YS tiled surfaces. */
114 const uint32_t align_2d_yf
[] = {64, 64, 32, 32, 16};
115 const uint32_t bpp
= cpp
* 8;
116 const uint32_t shift
= is_src
? 17 : 10;
120 if (tr_mode
== INTEL_MIPTREE_TRMODE_NONE
)
123 /* Compute array index. */
124 assert (bpp
>= 8 && bpp
<= 128 && is_power_of_two(bpp
));
125 i
= ffs(bpp
/ 8) - 1;
127 align
= tr_mode
== INTEL_MIPTREE_TRMODE_YF
?
131 assert(is_power_of_two(align
));
133 /* XY_FAST_COPY_BLT doesn't support horizontal alignment of 16. */
137 return (ffs(align
) - 6) << shift
;
141 get_tr_vertical_align(uint32_t tr_mode
, uint32_t cpp
, bool is_src
) {
142 /* Vertical alignment tables for YF/YS tiled surfaces. */
143 const unsigned align_2d_yf
[] = {64, 32, 32, 16, 16};
144 const uint32_t bpp
= cpp
* 8;
145 const uint32_t shift
= is_src
? 15 : 8;
149 if (tr_mode
== INTEL_MIPTREE_TRMODE_NONE
)
152 /* Compute array index. */
153 assert (bpp
>= 8 && bpp
<= 128 && is_power_of_two(bpp
));
154 i
= ffs(bpp
/ 8) - 1;
156 align
= tr_mode
== INTEL_MIPTREE_TRMODE_YF
?
160 assert(is_power_of_two(align
));
162 /* XY_FAST_COPY_BLT doesn't support vertical alignments of 16 and 32. */
163 if (align
== 16 || align
== 32)
166 return (ffs(align
) - 7) << shift
;
170 * Emits the packet for switching the blitter from X to Y tiled or back.
172 * This has to be called in a single BEGIN_BATCH_BLT_TILED() /
173 * ADVANCE_BATCH_TILED(). This is because BCS_SWCTRL is saved and restored as
174 * part of the power context, not a render context, and if the batchbuffer was
175 * to get flushed between setting and blitting, or blitting and restoring, our
176 * tiling state would leak into other unsuspecting applications (like the X
180 set_blitter_tiling(struct brw_context
*brw
,
181 bool dst_y_tiled
, bool src_y_tiled
)
183 assert(brw
->gen
>= 6);
185 /* Idle the blitter before we update how tiling is interpreted. */
186 OUT_BATCH(MI_FLUSH_DW
);
191 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
192 OUT_BATCH(BCS_SWCTRL
);
193 OUT_BATCH((BCS_SWCTRL_DST_Y
| BCS_SWCTRL_SRC_Y
) << 16 |
194 (dst_y_tiled
? BCS_SWCTRL_DST_Y
: 0) |
195 (src_y_tiled
? BCS_SWCTRL_SRC_Y
: 0));
198 #define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled) do { \
199 BEGIN_BATCH_BLT(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0)); \
200 if (dst_y_tiled || src_y_tiled) \
201 set_blitter_tiling(brw, dst_y_tiled, src_y_tiled); \
204 #define ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled) do { \
205 if (dst_y_tiled || src_y_tiled) \
206 set_blitter_tiling(brw, false, false); \
211 blt_pitch(struct intel_mipmap_tree
*mt
)
213 int pitch
= mt
->pitch
;
220 intel_miptree_blit_compatible_formats(mesa_format src
, mesa_format dst
)
222 /* The BLT doesn't handle sRGB conversion */
223 assert(src
== _mesa_get_srgb_format_linear(src
));
224 assert(dst
== _mesa_get_srgb_format_linear(dst
));
226 /* No swizzle or format conversions possible, except... */
230 /* ...we can either discard the alpha channel when going from A->X,
231 * or we can fill the alpha channel with 0xff when going from X->A
233 if (src
== MESA_FORMAT_B8G8R8A8_UNORM
|| src
== MESA_FORMAT_B8G8R8X8_UNORM
)
234 return (dst
== MESA_FORMAT_B8G8R8A8_UNORM
||
235 dst
== MESA_FORMAT_B8G8R8X8_UNORM
);
237 if (src
== MESA_FORMAT_R8G8B8A8_UNORM
|| src
== MESA_FORMAT_R8G8B8X8_UNORM
)
238 return (dst
== MESA_FORMAT_R8G8B8A8_UNORM
||
239 dst
== MESA_FORMAT_R8G8B8X8_UNORM
);
245 * Implements a rectangular block transfer (blit) of pixels between two
248 * Our blitter can operate on 1, 2, or 4-byte-per-pixel data, with generous,
249 * but limited, pitches and sizes allowed.
251 * The src/dst coordinates are relative to the given level/slice of the
254 * If @src_flip or @dst_flip is set, then the rectangle within that miptree
255 * will be inverted (including scanline order) when copying. This is common
256 * in GL when copying between window system and user-created
257 * renderbuffers/textures.
260 intel_miptree_blit(struct brw_context
*brw
,
261 struct intel_mipmap_tree
*src_mt
,
262 int src_level
, int src_slice
,
263 uint32_t src_x
, uint32_t src_y
, bool src_flip
,
264 struct intel_mipmap_tree
*dst_mt
,
265 int dst_level
, int dst_slice
,
266 uint32_t dst_x
, uint32_t dst_y
, bool dst_flip
,
267 uint32_t width
, uint32_t height
,
270 /* The blitter doesn't understand multisampling at all. */
271 if (src_mt
->num_samples
> 0 || dst_mt
->num_samples
> 0)
274 /* No sRGB decode or encode is done by the hardware blitter, which is
275 * consistent with what we want in the callers (glCopyTexSubImage(),
276 * glBlitFramebuffer(), texture validation, etc.).
278 mesa_format src_format
= _mesa_get_srgb_format_linear(src_mt
->format
);
279 mesa_format dst_format
= _mesa_get_srgb_format_linear(dst_mt
->format
);
281 /* The blitter doesn't support doing any format conversions. We do also
282 * support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into
283 * the X channel don't matter), and XRGB8888 to ARGB8888 by setting the A
284 * channel to 1.0 at the end.
286 if (!intel_miptree_blit_compatible_formats(src_format
, dst_format
)) {
287 perf_debug("%s: Can't use hardware blitter from %s to %s, "
288 "falling back.\n", __func__
,
289 _mesa_get_format_name(src_format
),
290 _mesa_get_format_name(dst_format
));
294 /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
295 * Data Size Limitations):
297 * The BLT engine is capable of transferring very large quantities of
298 * graphics data. Any graphics data read from and written to the
299 * destination is permitted to represent a number of pixels that
300 * occupies up to 65,536 scan lines and up to 32,768 bytes per scan line
301 * at the destination. The maximum number of pixels that may be
302 * represented per scan line’s worth of graphics data depends on the
305 * Furthermore, intelEmitCopyBlit (which is called below) uses a signed
306 * 16-bit integer to represent buffer pitch, so it can only handle buffer
307 * pitches < 32k. However, the pitch is measured in bytes for linear buffers
308 * and dwords for tiled buffers.
310 * As a result of these two limitations, we can only use the blitter to do
311 * this copy when the miptree's pitch is less than 32k linear or 128k tiled.
313 if (blt_pitch(src_mt
) >= 32768 || blt_pitch(dst_mt
) >= 32768) {
314 perf_debug("Falling back due to >= 32k/128k pitch\n");
318 /* The blitter has no idea about HiZ or fast color clears, so we need to
319 * resolve the miptrees before we do anything.
321 intel_miptree_slice_resolve_depth(brw
, src_mt
, src_level
, src_slice
);
322 intel_miptree_slice_resolve_depth(brw
, dst_mt
, dst_level
, dst_slice
);
323 intel_miptree_resolve_color(brw
, src_mt
);
324 intel_miptree_resolve_color(brw
, dst_mt
);
327 src_y
= minify(src_mt
->physical_height0
, src_level
- src_mt
->first_level
) - src_y
- height
;
330 dst_y
= minify(dst_mt
->physical_height0
, dst_level
- dst_mt
->first_level
) - dst_y
- height
;
332 int src_pitch
= src_mt
->pitch
;
333 if (src_flip
!= dst_flip
)
334 src_pitch
= -src_pitch
;
336 uint32_t src_image_x
, src_image_y
, dst_image_x
, dst_image_y
;
337 intel_miptree_get_image_offset(src_mt
, src_level
, src_slice
,
338 &src_image_x
, &src_image_y
);
339 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_slice
,
340 &dst_image_x
, &dst_image_y
);
341 src_x
+= src_image_x
;
342 src_y
+= src_image_y
;
343 dst_x
+= dst_image_x
;
344 dst_y
+= dst_image_y
;
346 /* The blitter interprets the 16-bit destination x/y as a signed 16-bit
347 * value. The values we're working with are unsigned, so make sure we don't
350 if (src_x
>= 32768 || src_y
>= 32768 || dst_x
>= 32768 || dst_y
>= 32768) {
351 perf_debug("Falling back due to >=32k offset [src(%d, %d) dst(%d, %d)]\n",
352 src_x
, src_y
, dst_x
, dst_y
);
356 if (!intelEmitCopyBlit(brw
,
359 src_mt
->bo
, src_mt
->offset
,
363 dst_mt
->bo
, dst_mt
->offset
,
373 /* XXX This could be done in a single pass using XY_FULL_MONO_PATTERN_BLT */
374 if (_mesa_get_format_bits(src_format
, GL_ALPHA_BITS
) == 0 &&
375 _mesa_get_format_bits(dst_format
, GL_ALPHA_BITS
) > 0) {
376 intel_miptree_set_alpha_to_one(brw
, dst_mt
,
385 alignment_valid(struct brw_context
*brw
, unsigned offset
, uint32_t tiling
)
387 /* Tiled buffers must be page-aligned (4K). */
388 if (tiling
!= I915_TILING_NONE
)
389 return (offset
& 4095) == 0;
391 /* On Gen8+, linear buffers must be cacheline-aligned. */
393 return (offset
& 63) == 0;
399 can_fast_copy_blit(struct brw_context
*brw
,
400 drm_intel_bo
*src_buffer
,
401 int16_t src_x
, int16_t src_y
,
402 uintptr_t src_offset
, uint32_t src_pitch
,
403 uint32_t src_tiling
, uint32_t src_tr_mode
,
404 drm_intel_bo
*dst_buffer
,
405 int16_t dst_x
, int16_t dst_y
,
406 uintptr_t dst_offset
, uint32_t dst_pitch
,
407 uint32_t dst_tiling
, uint32_t dst_tr_mode
,
408 int16_t w
, int16_t h
, uint32_t cpp
)
410 const bool dst_tiling_none
= dst_tiling
== I915_TILING_NONE
;
411 const bool src_tiling_none
= src_tiling
== I915_TILING_NONE
;
416 if (src_buffer
->handle
== dst_buffer
->handle
&&
417 _mesa_regions_overlap(src_x
, src_y
, src_x
+ w
, src_y
+ h
,
418 dst_x
, dst_y
, dst_x
+ w
, dst_y
+ h
))
421 /* Enable fast copy blit only if the surfaces are Yf/Ys tiled.
422 * FIXME: Based on performance data, remove this condition later to
423 * enable for all types of surfaces.
425 if (src_tr_mode
== INTEL_MIPTREE_TRMODE_NONE
&&
426 dst_tr_mode
== INTEL_MIPTREE_TRMODE_NONE
)
429 /* For all surface types buffers must be cacheline-aligned. */
430 if ((dst_offset
| src_offset
) & 63)
433 /* Color depth greater than 128 bits not supported. */
437 /* For Fast Copy Blits the pitch cannot be a negative number. So, bit 15
438 * of the destination pitch must be zero.
440 if ((src_pitch
>> 15 & 1) != 0 || (dst_pitch
>> 15 & 1) != 0)
443 /* For Linear surfaces, the pitch has to be an OWord (16byte) multiple. */
444 if ((src_tiling_none
&& src_pitch
% 16 != 0) ||
445 (dst_tiling_none
&& dst_pitch
% 16 != 0))
448 /* For Tiled surfaces, the pitch has to be a multiple of the Tile width
449 * (X direction width of the Tile). This means the pitch value will
450 * always be Cache Line aligned (64byte multiple).
452 if ((!dst_tiling_none
&& dst_pitch
% 64 != 0) ||
453 (!src_tiling_none
&& src_pitch
% 64 != 0))
462 intelEmitCopyBlit(struct brw_context
*brw
,
465 drm_intel_bo
*src_buffer
,
468 uint32_t src_tr_mode
,
470 drm_intel_bo
*dst_buffer
,
473 uint32_t dst_tr_mode
,
474 GLshort src_x
, GLshort src_y
,
475 GLshort dst_x
, GLshort dst_y
,
476 GLshort w
, GLshort h
,
479 GLuint CMD
, BR13
, pass
= 0;
480 int dst_y2
= dst_y
+ h
;
481 int dst_x2
= dst_x
+ w
;
482 drm_intel_bo
*aper_array
[3];
483 bool dst_y_tiled
= dst_tiling
== I915_TILING_Y
;
484 bool src_y_tiled
= src_tiling
== I915_TILING_Y
;
485 bool use_fast_copy_blit
= false;
487 if ((dst_y_tiled
|| src_y_tiled
) && brw
->gen
< 6)
490 /* do space check before going any further */
492 aper_array
[0] = brw
->batch
.bo
;
493 aper_array
[1] = dst_buffer
;
494 aper_array
[2] = src_buffer
;
496 if (dri_bufmgr_check_aperture_space(aper_array
, 3) != 0) {
497 intel_batchbuffer_flush(brw
);
506 unsigned length
= brw
->gen
>= 8 ? 10 : 8;
508 intel_batchbuffer_require_space(brw
, length
* 4, BLT_RING
);
509 DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
511 src_buffer
, src_pitch
, src_offset
, src_x
, src_y
,
512 dst_buffer
, dst_pitch
, dst_offset
, dst_x
, dst_y
, w
, h
);
514 use_fast_copy_blit
= can_fast_copy_blit(brw
,
517 src_offset
, src_pitch
,
518 src_tiling
, src_tr_mode
,
521 dst_offset
, dst_pitch
,
522 dst_tiling
, dst_tr_mode
,
524 assert(use_fast_copy_blit
||
525 (src_tr_mode
== INTEL_MIPTREE_TRMODE_NONE
&&
526 dst_tr_mode
== INTEL_MIPTREE_TRMODE_NONE
));
528 if (use_fast_copy_blit
) {
529 /* When two sequential fast copy blits have different source surfaces,
530 * but their destinations refer to the same destination surfaces and
531 * therefore destinations overlap it is imperative that a flush be
532 * inserted between the two blits.
534 * FIXME: Figure out a way to avoid flushing when not required.
536 brw_emit_mi_flush(brw
);
539 BR13
= br13_for_cpp(cpp
);
541 if (src_tr_mode
== INTEL_MIPTREE_TRMODE_YF
)
542 BR13
|= XY_FAST_SRC_TRMODE_YF
;
544 if (dst_tr_mode
== INTEL_MIPTREE_TRMODE_YF
)
545 BR13
|= XY_FAST_DST_TRMODE_YF
;
547 CMD
= XY_FAST_COPY_BLT_CMD
;
549 if (dst_tiling
!= I915_TILING_NONE
) {
550 SET_TILING_XY_FAST_COPY_BLT(dst_tiling
, dst_tr_mode
, XY_FAST_DST
);
551 /* Pitch value should be specified as a number of Dwords. */
554 if (src_tiling
!= I915_TILING_NONE
) {
555 SET_TILING_XY_FAST_COPY_BLT(src_tiling
, src_tr_mode
, XY_FAST_SRC
);
556 /* Pitch value should be specified as a number of Dwords. */
560 CMD
|= get_tr_horizontal_align(src_tr_mode
, cpp
, true /* is_src */);
561 CMD
|= get_tr_vertical_align(src_tr_mode
, cpp
, true /* is_src */);
563 CMD
|= get_tr_horizontal_align(dst_tr_mode
, cpp
, false /* is_src */);
564 CMD
|= get_tr_vertical_align(dst_tr_mode
, cpp
, false /* is_src */);
567 assert(!dst_y_tiled
|| (dst_pitch
% 128) == 0);
568 assert(!src_y_tiled
|| (src_pitch
% 128) == 0);
570 /* For big formats (such as floating point), do the copy using 16 or
571 * 32bpp and multiply the coordinates.
580 assert(cpp
% 4 == 0);
588 if (!alignment_valid(brw
, dst_offset
, dst_tiling
))
590 if (!alignment_valid(brw
, src_offset
, src_tiling
))
593 /* Blit pitch must be dword-aligned. Otherwise, the hardware appears to drop
594 * the low bits. Offsets must be naturally aligned.
596 if (src_pitch
% 4 != 0 || src_offset
% cpp
!= 0 ||
597 dst_pitch
% 4 != 0 || dst_offset
% cpp
!= 0)
601 BR13
= br13_for_cpp(cpp
) | translate_raster_op(logic_op
) << 16;
605 CMD
= XY_SRC_COPY_BLT_CMD
;
608 CMD
= XY_SRC_COPY_BLT_CMD
| XY_BLT_WRITE_ALPHA
| XY_BLT_WRITE_RGB
;
614 if (dst_tiling
!= I915_TILING_NONE
) {
618 if (src_tiling
!= I915_TILING_NONE
) {
624 if (dst_y2
<= dst_y
|| dst_x2
<= dst_x
) {
628 assert(dst_x
< dst_x2
);
629 assert(dst_y
< dst_y2
);
630 assert(src_offset
+ (src_y
+ h
- 1) * abs(src_pitch
) +
631 (w
* cpp
) <= src_buffer
->size
);
632 assert(dst_offset
+ (dst_y
+ h
- 1) * abs(dst_pitch
) +
633 (w
* cpp
) <= dst_buffer
->size
);
635 BEGIN_BATCH_BLT_TILED(length
, dst_y_tiled
, src_y_tiled
);
636 OUT_BATCH(CMD
| (length
- 2));
637 OUT_BATCH(BR13
| (uint16_t)dst_pitch
);
638 OUT_BATCH(SET_FIELD(dst_y
, BLT_Y
) | SET_FIELD(dst_x
, BLT_X
));
639 OUT_BATCH(SET_FIELD(dst_y2
, BLT_Y
) | SET_FIELD(dst_x2
, BLT_X
));
641 OUT_RELOC64(dst_buffer
,
642 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
645 OUT_RELOC(dst_buffer
,
646 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
649 OUT_BATCH(SET_FIELD(src_y
, BLT_Y
) | SET_FIELD(src_x
, BLT_X
));
650 OUT_BATCH((uint16_t)src_pitch
);
652 OUT_RELOC64(src_buffer
,
653 I915_GEM_DOMAIN_RENDER
, 0,
656 OUT_RELOC(src_buffer
,
657 I915_GEM_DOMAIN_RENDER
, 0,
661 ADVANCE_BATCH_TILED(dst_y_tiled
, src_y_tiled
);
663 brw_emit_mi_flush(brw
);
669 intelEmitImmediateColorExpandBlit(struct brw_context
*brw
,
671 GLubyte
*src_bits
, GLuint src_size
,
674 drm_intel_bo
*dst_buffer
,
677 GLshort x
, GLshort y
,
678 GLshort w
, GLshort h
,
681 int dwords
= ALIGN(src_size
, 8) / 4;
682 uint32_t opcode
, br13
, blit_cmd
;
684 if (dst_tiling
!= I915_TILING_NONE
) {
685 if (dst_offset
& 4095)
687 if (dst_tiling
== I915_TILING_Y
)
691 assert((logic_op
>= GL_CLEAR
) && (logic_op
<= (GL_CLEAR
+ 0x0f)));
692 assert(dst_pitch
> 0);
697 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
699 dst_buffer
, dst_pitch
, dst_offset
, x
, y
, w
, h
, src_size
, dwords
);
701 unsigned xy_setup_blt_length
= brw
->gen
>= 8 ? 10 : 8;
702 intel_batchbuffer_require_space(brw
, (xy_setup_blt_length
* 4) +
703 (3 * 4) + dwords
* 4, BLT_RING
);
705 opcode
= XY_SETUP_BLT_CMD
;
707 opcode
|= XY_BLT_WRITE_ALPHA
| XY_BLT_WRITE_RGB
;
708 if (dst_tiling
!= I915_TILING_NONE
) {
709 opcode
|= XY_DST_TILED
;
713 br13
= dst_pitch
| (translate_raster_op(logic_op
) << 16) | (1 << 29);
714 br13
|= br13_for_cpp(cpp
);
716 blit_cmd
= XY_TEXT_IMMEDIATE_BLIT_CMD
| XY_TEXT_BYTE_PACKED
; /* packing? */
717 if (dst_tiling
!= I915_TILING_NONE
)
718 blit_cmd
|= XY_DST_TILED
;
720 BEGIN_BATCH_BLT(xy_setup_blt_length
+ 3);
721 OUT_BATCH(opcode
| (xy_setup_blt_length
- 2));
723 OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
724 OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
726 OUT_RELOC64(dst_buffer
,
727 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
730 OUT_RELOC(dst_buffer
,
731 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
734 OUT_BATCH(0); /* bg */
735 OUT_BATCH(fg_color
); /* fg */
736 OUT_BATCH(0); /* pattern base addr */
740 OUT_BATCH(blit_cmd
| ((3 - 2) + dwords
));
741 OUT_BATCH(SET_FIELD(y
, BLT_Y
) | SET_FIELD(x
, BLT_X
));
742 OUT_BATCH(SET_FIELD(y
+ h
, BLT_Y
) | SET_FIELD(x
+ w
, BLT_X
));
745 intel_batchbuffer_data(brw
, src_bits
, dwords
* 4, BLT_RING
);
747 brw_emit_mi_flush(brw
);
752 /* We don't have a memmove-type blit like some other hardware, so we'll do a
753 * rectangular blit covering a large space, then emit 1-scanline blit at the
754 * end to cover the last if we need.
757 intel_emit_linear_blit(struct brw_context
*brw
,
758 drm_intel_bo
*dst_bo
,
759 unsigned int dst_offset
,
760 drm_intel_bo
*src_bo
,
761 unsigned int src_offset
,
764 struct gl_context
*ctx
= &brw
->ctx
;
765 GLuint pitch
, height
;
766 int16_t src_x
, dst_x
;
769 /* The pitch given to the GPU must be DWORD aligned, and
770 * we want width to match pitch. Max width is (1 << 15 - 1),
771 * rounding that down to the nearest DWORD is 1 << 15 - 4
773 pitch
= ROUND_DOWN_TO(MIN2(size
, (1 << 15) - 1), 4);
774 height
= (pitch
== 0) ? 1 : size
/ pitch
;
775 src_x
= src_offset
% 64;
776 dst_x
= dst_offset
% 64;
777 ok
= intelEmitCopyBlit(brw
, 1,
778 pitch
, src_bo
, src_offset
- src_x
, I915_TILING_NONE
,
779 INTEL_MIPTREE_TRMODE_NONE
,
780 pitch
, dst_bo
, dst_offset
- dst_x
, I915_TILING_NONE
,
781 INTEL_MIPTREE_TRMODE_NONE
,
782 src_x
, 0, /* src x/y */
783 dst_x
, 0, /* dst x/y */
784 pitch
, height
, /* w, h */
787 _mesa_problem(ctx
, "Failed to linear blit %dx%d\n", pitch
, height
);
789 src_offset
+= pitch
* height
;
790 dst_offset
+= pitch
* height
;
791 src_x
= src_offset
% 64;
792 dst_x
= dst_offset
% 64;
793 size
-= pitch
* height
;
794 assert (size
< (1 << 15));
795 pitch
= ALIGN(size
, 4);
798 ok
= intelEmitCopyBlit(brw
, 1,
799 pitch
, src_bo
, src_offset
- src_x
, I915_TILING_NONE
,
800 INTEL_MIPTREE_TRMODE_NONE
,
801 pitch
, dst_bo
, dst_offset
- dst_x
, I915_TILING_NONE
,
802 INTEL_MIPTREE_TRMODE_NONE
,
803 src_x
, 0, /* src x/y */
804 dst_x
, 0, /* dst x/y */
808 _mesa_problem(ctx
, "Failed to linear blit %dx%d\n", size
, 1);
813 * Used to initialize the alpha value of an ARGB8888 miptree after copying
814 * into it from an XRGB8888 source.
816 * This is very common with glCopyTexImage2D(). Note that the coordinates are
817 * relative to the start of the miptree, not relative to a slice within the
821 intel_miptree_set_alpha_to_one(struct brw_context
*brw
,
822 struct intel_mipmap_tree
*mt
,
823 int x
, int y
, int width
, int height
)
827 drm_intel_bo
*aper_array
[2];
832 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
833 __func__
, mt
->bo
, pitch
, x
, y
, width
, height
);
835 BR13
= br13_for_cpp(cpp
) | 0xf0 << 16;
836 CMD
= XY_COLOR_BLT_CMD
;
837 CMD
|= XY_BLT_WRITE_ALPHA
;
839 if (mt
->tiling
!= I915_TILING_NONE
) {
845 /* do space check before going any further */
846 aper_array
[0] = brw
->batch
.bo
;
847 aper_array
[1] = mt
->bo
;
849 if (drm_intel_bufmgr_check_aperture_space(aper_array
,
850 ARRAY_SIZE(aper_array
)) != 0) {
851 intel_batchbuffer_flush(brw
);
854 unsigned length
= brw
->gen
>= 8 ? 7 : 6;
855 bool dst_y_tiled
= mt
->tiling
== I915_TILING_Y
;
857 BEGIN_BATCH_BLT_TILED(length
, dst_y_tiled
, false);
858 OUT_BATCH(CMD
| (length
- 2));
860 OUT_BATCH(SET_FIELD(y
, BLT_Y
) | SET_FIELD(x
, BLT_X
));
861 OUT_BATCH(SET_FIELD(y
+ height
, BLT_Y
) | SET_FIELD(x
+ width
, BLT_X
));
864 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
868 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
871 OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
872 ADVANCE_BATCH_TILED(dst_y_tiled
, false);
874 brw_emit_mi_flush(brw
);