2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "main/mtypes.h"
27 #include "main/blit.h"
28 #include "main/context.h"
29 #include "main/enums.h"
30 #include "main/fbobject.h"
32 #include "brw_context.h"
33 #include "brw_defines.h"
34 #include "intel_blit.h"
35 #include "intel_buffers.h"
36 #include "intel_fbo.h"
37 #include "intel_batchbuffer.h"
38 #include "intel_mipmap_tree.h"
40 #define FILE_DEBUG_FLAG DEBUG_BLIT
43 intel_miptree_set_alpha_to_one(struct brw_context
*brw
,
44 struct intel_mipmap_tree
*mt
,
45 int x
, int y
, int width
, int height
);
47 static GLuint
translate_raster_op(GLenum logicop
)
50 case GL_CLEAR
: return 0x00;
51 case GL_AND
: return 0x88;
52 case GL_AND_REVERSE
: return 0x44;
53 case GL_COPY
: return 0xCC;
54 case GL_AND_INVERTED
: return 0x22;
55 case GL_NOOP
: return 0xAA;
56 case GL_XOR
: return 0x66;
57 case GL_OR
: return 0xEE;
58 case GL_NOR
: return 0x11;
59 case GL_EQUIV
: return 0x99;
60 case GL_INVERT
: return 0x55;
61 case GL_OR_REVERSE
: return 0xDD;
62 case GL_COPY_INVERTED
: return 0x33;
63 case GL_OR_INVERTED
: return 0xBB;
64 case GL_NAND
: return 0x77;
65 case GL_SET
: return 0xFF;
85 unreachable("not reached");
90 * Emits the packet for switching the blitter from X to Y tiled or back.
92 * This has to be called in a single BEGIN_BATCH_BLT_TILED() /
93 * ADVANCE_BATCH_TILED(). This is because BCS_SWCTRL is saved and restored as
94 * part of the power context, not a render context, and if the batchbuffer was
95 * to get flushed between setting and blitting, or blitting and restoring, our
96 * tiling state would leak into other unsuspecting applications (like the X
100 set_blitter_tiling(struct brw_context
*brw
,
101 bool dst_y_tiled
, bool src_y_tiled
,
104 assert(brw
->gen
>= 6);
106 /* Idle the blitter before we update how tiling is interpreted. */
107 OUT_BATCH(MI_FLUSH_DW
);
112 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
113 OUT_BATCH(BCS_SWCTRL
);
114 OUT_BATCH((BCS_SWCTRL_DST_Y
| BCS_SWCTRL_SRC_Y
) << 16 |
115 (dst_y_tiled
? BCS_SWCTRL_DST_Y
: 0) |
116 (src_y_tiled
? BCS_SWCTRL_SRC_Y
: 0));
119 #define SET_BLITTER_TILING(...) __map = set_blitter_tiling(__VA_ARGS__, __map)
121 #define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled) \
122 BEGIN_BATCH_BLT(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0)); \
123 if (dst_y_tiled || src_y_tiled) \
124 SET_BLITTER_TILING(brw, dst_y_tiled, src_y_tiled)
126 #define ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled) \
127 if (dst_y_tiled || src_y_tiled) \
128 SET_BLITTER_TILING(brw, false, false); \
132 blt_pitch(struct intel_mipmap_tree
*mt
)
134 int pitch
= mt
->pitch
;
141 intel_miptree_blit_compatible_formats(mesa_format src
, mesa_format dst
)
143 /* The BLT doesn't handle sRGB conversion */
144 assert(src
== _mesa_get_srgb_format_linear(src
));
145 assert(dst
== _mesa_get_srgb_format_linear(dst
));
147 /* No swizzle or format conversions possible, except... */
151 /* ...we can either discard the alpha channel when going from A->X,
152 * or we can fill the alpha channel with 0xff when going from X->A
154 if (src
== MESA_FORMAT_B8G8R8A8_UNORM
|| src
== MESA_FORMAT_B8G8R8X8_UNORM
)
155 return (dst
== MESA_FORMAT_B8G8R8A8_UNORM
||
156 dst
== MESA_FORMAT_B8G8R8X8_UNORM
);
158 if (src
== MESA_FORMAT_R8G8B8A8_UNORM
|| src
== MESA_FORMAT_R8G8B8X8_UNORM
)
159 return (dst
== MESA_FORMAT_R8G8B8A8_UNORM
||
160 dst
== MESA_FORMAT_R8G8B8X8_UNORM
);
166 get_blit_intratile_offset_el(const struct brw_context
*brw
,
167 struct intel_mipmap_tree
*mt
,
168 uint32_t total_x_offset_el
,
169 uint32_t total_y_offset_el
,
170 uint32_t *base_address_offset
,
171 uint32_t *x_offset_el
,
172 uint32_t *y_offset_el
)
174 enum isl_tiling tiling
= intel_miptree_get_isl_tiling(mt
);
175 isl_tiling_get_intratile_offset_el(tiling
, mt
->cpp
* 8, mt
->pitch
,
176 total_x_offset_el
, total_y_offset_el
,
178 x_offset_el
, y_offset_el
);
179 if (tiling
== ISL_TILING_LINEAR
) {
180 /* From the Broadwell PRM docs for XY_SRC_COPY_BLT::SourceBaseAddress:
182 * "Base address of the destination surface: X=0, Y=0. Lower 32bits
183 * of the 48bit addressing. When Src Tiling is enabled (Bit_15
184 * enabled), this address must be 4KB-aligned. When Tiling is not
185 * enabled, this address should be CL (64byte) aligned."
187 * The offsets we get from ISL in the tiled case are already aligned.
188 * In the linear case, we need to do some of our own aligning.
190 assert(mt
->pitch
% 64 == 0);
191 uint32_t delta
= *base_address_offset
& 63;
192 assert(delta
% mt
->cpp
== 0);
193 *base_address_offset
-= delta
;
194 *x_offset_el
+= delta
/ mt
->cpp
;
196 assert(*base_address_offset
% 4096 == 0);
201 emit_miptree_blit(struct brw_context
*brw
,
202 struct intel_mipmap_tree
*src_mt
,
203 uint32_t src_x
, uint32_t src_y
,
204 struct intel_mipmap_tree
*dst_mt
,
205 uint32_t dst_x
, uint32_t dst_y
,
206 uint32_t width
, uint32_t height
,
207 bool reverse
, GLenum logicop
)
209 /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
210 * Data Size Limitations):
212 * The BLT engine is capable of transferring very large quantities of
213 * graphics data. Any graphics data read from and written to the
214 * destination is permitted to represent a number of pixels that
215 * occupies up to 65,536 scan lines and up to 32,768 bytes per scan line
216 * at the destination. The maximum number of pixels that may be
217 * represented per scan line’s worth of graphics data depends on the
220 * The blitter's pitch is a signed 16-bit integer, but measured in bytes
221 * for linear surfaces and DWords for tiled surfaces. So the maximum
222 * pitch is 32k linear and 128k tiled.
224 if (blt_pitch(src_mt
) >= 32768 || blt_pitch(dst_mt
) >= 32768) {
225 perf_debug("Falling back due to >= 32k/128k pitch\n");
229 /* We need to split the blit into chunks that each fit within the blitter's
230 * restrictions. We can't use a chunk size of 32768 because we need to
231 * ensure that src_tile_x + chunk_size fits. We choose 16384 because it's
232 * a nice round power of two, big enough that performance won't suffer, and
233 * small enough to guarantee everything fits.
235 const uint32_t max_chunk_size
= 16384;
237 for (uint32_t chunk_x
= 0; chunk_x
< width
; chunk_x
+= max_chunk_size
) {
238 for (uint32_t chunk_y
= 0; chunk_y
< height
; chunk_y
+= max_chunk_size
) {
239 const uint32_t chunk_w
= MIN2(max_chunk_size
, width
- chunk_x
);
240 const uint32_t chunk_h
= MIN2(max_chunk_size
, height
- chunk_y
);
242 uint32_t src_offset
, src_tile_x
, src_tile_y
;
243 get_blit_intratile_offset_el(brw
, src_mt
,
244 src_x
+ chunk_x
, src_y
+ chunk_y
,
245 &src_offset
, &src_tile_x
, &src_tile_y
);
247 uint32_t dst_offset
, dst_tile_x
, dst_tile_y
;
248 get_blit_intratile_offset_el(brw
, dst_mt
,
249 dst_x
+ chunk_x
, dst_y
+ chunk_y
,
250 &dst_offset
, &dst_tile_x
, &dst_tile_y
);
252 if (!intelEmitCopyBlit(brw
,
254 reverse
? -src_mt
->pitch
: src_mt
->pitch
,
255 src_mt
->bo
, src_mt
->offset
+ src_offset
,
258 dst_mt
->bo
, dst_mt
->offset
+ dst_offset
,
260 src_tile_x
, src_tile_y
,
261 dst_tile_x
, dst_tile_y
,
264 /* If this is ever going to fail, it will fail on the first chunk */
265 assert(chunk_x
== 0 && chunk_y
== 0);
275 * Implements a rectangular block transfer (blit) of pixels between two
278 * Our blitter can operate on 1, 2, or 4-byte-per-pixel data, with generous,
279 * but limited, pitches and sizes allowed.
281 * The src/dst coordinates are relative to the given level/slice of the
284 * If @src_flip or @dst_flip is set, then the rectangle within that miptree
285 * will be inverted (including scanline order) when copying. This is common
286 * in GL when copying between window system and user-created
287 * renderbuffers/textures.
290 intel_miptree_blit(struct brw_context
*brw
,
291 struct intel_mipmap_tree
*src_mt
,
292 int src_level
, int src_slice
,
293 uint32_t src_x
, uint32_t src_y
, bool src_flip
,
294 struct intel_mipmap_tree
*dst_mt
,
295 int dst_level
, int dst_slice
,
296 uint32_t dst_x
, uint32_t dst_y
, bool dst_flip
,
297 uint32_t width
, uint32_t height
,
300 /* The blitter doesn't understand multisampling at all. */
301 if (src_mt
->num_samples
> 0 || dst_mt
->num_samples
> 0)
304 /* No sRGB decode or encode is done by the hardware blitter, which is
305 * consistent with what we want in many callers (glCopyTexSubImage(),
306 * texture validation, etc.).
308 mesa_format src_format
= _mesa_get_srgb_format_linear(src_mt
->format
);
309 mesa_format dst_format
= _mesa_get_srgb_format_linear(dst_mt
->format
);
311 /* The blitter doesn't support doing any format conversions. We do also
312 * support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into
313 * the X channel don't matter), and XRGB8888 to ARGB8888 by setting the A
314 * channel to 1.0 at the end.
316 if (!intel_miptree_blit_compatible_formats(src_format
, dst_format
)) {
317 perf_debug("%s: Can't use hardware blitter from %s to %s, "
318 "falling back.\n", __func__
,
319 _mesa_get_format_name(src_format
),
320 _mesa_get_format_name(dst_format
));
324 /* The blitter has no idea about HiZ or fast color clears, so we need to
325 * resolve the miptrees before we do anything.
327 intel_miptree_slice_resolve_depth(brw
, src_mt
, src_level
, src_slice
);
328 intel_miptree_slice_resolve_depth(brw
, dst_mt
, dst_level
, dst_slice
);
329 intel_miptree_resolve_color(brw
, src_mt
, src_level
, src_slice
, 1, 0);
330 intel_miptree_resolve_color(brw
, dst_mt
, dst_level
, dst_slice
, 1, 0);
331 intel_miptree_slice_set_needs_hiz_resolve(dst_mt
, dst_level
, dst_slice
);
334 src_y
= minify(src_mt
->physical_height0
, src_level
- src_mt
->first_level
) - src_y
- height
;
337 dst_y
= minify(dst_mt
->physical_height0
, dst_level
- dst_mt
->first_level
) - dst_y
- height
;
339 uint32_t src_image_x
, src_image_y
, dst_image_x
, dst_image_y
;
340 intel_miptree_get_image_offset(src_mt
, src_level
, src_slice
,
341 &src_image_x
, &src_image_y
);
342 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_slice
,
343 &dst_image_x
, &dst_image_y
);
344 src_x
+= src_image_x
;
345 src_y
+= src_image_y
;
346 dst_x
+= dst_image_x
;
347 dst_y
+= dst_image_y
;
349 if (!emit_miptree_blit(brw
, src_mt
, src_x
, src_y
,
350 dst_mt
, dst_x
, dst_y
, width
, height
,
351 src_flip
!= dst_flip
, logicop
)) {
355 /* XXX This could be done in a single pass using XY_FULL_MONO_PATTERN_BLT */
356 if (_mesa_get_format_bits(src_format
, GL_ALPHA_BITS
) == 0 &&
357 _mesa_get_format_bits(dst_format
, GL_ALPHA_BITS
) > 0) {
358 intel_miptree_set_alpha_to_one(brw
, dst_mt
,
367 intel_miptree_copy(struct brw_context
*brw
,
368 struct intel_mipmap_tree
*src_mt
,
369 int src_level
, int src_slice
,
370 uint32_t src_x
, uint32_t src_y
,
371 struct intel_mipmap_tree
*dst_mt
,
372 int dst_level
, int dst_slice
,
373 uint32_t dst_x
, uint32_t dst_y
,
374 uint32_t src_width
, uint32_t src_height
)
376 /* The blitter doesn't understand multisampling at all. */
377 if (src_mt
->num_samples
> 0 || dst_mt
->num_samples
> 0)
380 if (src_mt
->format
== MESA_FORMAT_S_UINT8
)
383 /* The blitter has no idea about HiZ or fast color clears, so we need to
384 * resolve the miptrees before we do anything.
386 intel_miptree_slice_resolve_depth(brw
, src_mt
, src_level
, src_slice
);
387 intel_miptree_slice_resolve_depth(brw
, dst_mt
, dst_level
, dst_slice
);
388 intel_miptree_resolve_color(brw
, src_mt
, src_level
, src_slice
, 1, 0);
389 intel_miptree_resolve_color(brw
, dst_mt
, dst_level
, dst_slice
, 1, 0);
390 intel_miptree_slice_set_needs_hiz_resolve(dst_mt
, dst_level
, dst_slice
);
392 uint32_t src_image_x
, src_image_y
;
393 intel_miptree_get_image_offset(src_mt
, src_level
, src_slice
,
394 &src_image_x
, &src_image_y
);
396 if (_mesa_is_format_compressed(src_mt
->format
)) {
398 _mesa_get_format_block_size(src_mt
->format
, &bw
, &bh
);
400 /* Compressed textures need not have dimensions that are a multiple of
401 * the block size. Rectangles in compressed textures do need to be a
402 * multiple of the block size. The one exception is that the right and
403 * bottom edges may be at the right or bottom edge of the miplevel even
404 * if it's not aligned.
406 assert(src_x
% bw
== 0);
407 assert(src_y
% bh
== 0);
408 assert(src_width
% bw
== 0 ||
409 src_x
+ src_width
== minify(src_mt
->logical_width0
, src_level
));
410 assert(src_height
% bh
== 0 ||
411 src_y
+ src_height
== minify(src_mt
->logical_height0
, src_level
));
415 src_width
= DIV_ROUND_UP(src_width
, (int)bw
);
416 src_height
= DIV_ROUND_UP(src_height
, (int)bh
);
418 src_x
+= src_image_x
;
419 src_y
+= src_image_y
;
421 uint32_t dst_image_x
, dst_image_y
;
422 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_slice
,
423 &dst_image_x
, &dst_image_y
);
425 if (_mesa_is_format_compressed(dst_mt
->format
)) {
427 _mesa_get_format_block_size(dst_mt
->format
, &bw
, &bh
);
429 assert(dst_x
% bw
== 0);
430 assert(dst_y
% bh
== 0);
435 dst_x
+= dst_image_x
;
436 dst_y
+= dst_image_y
;
438 return emit_miptree_blit(brw
, src_mt
, src_x
, src_y
,
439 dst_mt
, dst_x
, dst_y
,
440 src_width
, src_height
, false, GL_COPY
);
444 alignment_valid(struct brw_context
*brw
, unsigned offset
, uint32_t tiling
)
446 /* Tiled buffers must be page-aligned (4K). */
447 if (tiling
!= I915_TILING_NONE
)
448 return (offset
& 4095) == 0;
450 /* On Gen8+, linear buffers must be cacheline-aligned. */
452 return (offset
& 63) == 0;
458 xy_blit_cmd(uint32_t src_tiling
, uint32_t dst_tiling
, uint32_t cpp
)
466 CMD
= XY_SRC_COPY_BLT_CMD
;
469 CMD
= XY_SRC_COPY_BLT_CMD
| XY_BLT_WRITE_ALPHA
| XY_BLT_WRITE_RGB
;
472 unreachable("not reached");
475 if (dst_tiling
!= I915_TILING_NONE
)
478 if (src_tiling
!= I915_TILING_NONE
)
487 intelEmitCopyBlit(struct brw_context
*brw
,
490 struct brw_bo
*src_buffer
,
494 struct brw_bo
*dst_buffer
,
497 GLshort src_x
, GLshort src_y
,
498 GLshort dst_x
, GLshort dst_y
,
499 GLshort w
, GLshort h
,
503 int dst_y2
= dst_y
+ h
;
504 int dst_x2
= dst_x
+ w
;
505 bool dst_y_tiled
= dst_tiling
== I915_TILING_Y
;
506 bool src_y_tiled
= src_tiling
== I915_TILING_Y
;
507 uint32_t src_tile_w
, src_tile_h
;
508 uint32_t dst_tile_w
, dst_tile_h
;
510 if ((dst_y_tiled
|| src_y_tiled
) && brw
->gen
< 6)
513 const unsigned bo_sizes
= dst_buffer
->size
+ src_buffer
->size
;
515 /* do space check before going any further */
516 if (!brw_batch_has_aperture_space(brw
, bo_sizes
))
517 intel_batchbuffer_flush(brw
);
519 if (!brw_batch_has_aperture_space(brw
, bo_sizes
))
522 unsigned length
= brw
->gen
>= 8 ? 10 : 8;
524 intel_batchbuffer_require_space(brw
, length
* 4, BLT_RING
);
525 DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
527 src_buffer
, src_pitch
, src_offset
, src_x
, src_y
,
528 dst_buffer
, dst_pitch
, dst_offset
, dst_x
, dst_y
, w
, h
);
530 intel_get_tile_dims(src_tiling
, cpp
, &src_tile_w
, &src_tile_h
);
531 intel_get_tile_dims(dst_tiling
, cpp
, &dst_tile_w
, &dst_tile_h
);
533 /* For Tiled surfaces, the pitch has to be a multiple of the Tile width
534 * (X direction width of the Tile). This is ensured while allocating the
537 assert(src_tiling
== I915_TILING_NONE
|| (src_pitch
% src_tile_w
) == 0);
538 assert(dst_tiling
== I915_TILING_NONE
|| (dst_pitch
% dst_tile_w
) == 0);
540 /* For big formats (such as floating point), do the copy using 16 or
541 * 32bpp and multiply the coordinates.
550 assert(cpp
% 4 == 0);
558 if (!alignment_valid(brw
, dst_offset
, dst_tiling
))
560 if (!alignment_valid(brw
, src_offset
, src_tiling
))
563 /* Blit pitch must be dword-aligned. Otherwise, the hardware appears to drop
564 * the low bits. Offsets must be naturally aligned.
566 if (src_pitch
% 4 != 0 || src_offset
% cpp
!= 0 ||
567 dst_pitch
% 4 != 0 || dst_offset
% cpp
!= 0)
571 BR13
= br13_for_cpp(cpp
) | translate_raster_op(logic_op
) << 16;
573 CMD
= xy_blit_cmd(src_tiling
, dst_tiling
, cpp
);
575 /* For tiled source and destination, pitch value should be specified
576 * as a number of Dwords.
578 if (dst_tiling
!= I915_TILING_NONE
)
581 if (src_tiling
!= I915_TILING_NONE
)
584 if (dst_y2
<= dst_y
|| dst_x2
<= dst_x
)
587 assert(dst_x
< dst_x2
);
588 assert(dst_y
< dst_y2
);
590 BEGIN_BATCH_BLT_TILED(length
, dst_y_tiled
, src_y_tiled
);
591 OUT_BATCH(CMD
| (length
- 2));
592 OUT_BATCH(BR13
| (uint16_t)dst_pitch
);
593 OUT_BATCH(SET_FIELD(dst_y
, BLT_Y
) | SET_FIELD(dst_x
, BLT_X
));
594 OUT_BATCH(SET_FIELD(dst_y2
, BLT_Y
) | SET_FIELD(dst_x2
, BLT_X
));
596 OUT_RELOC64(dst_buffer
,
597 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
600 OUT_RELOC(dst_buffer
,
601 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
604 OUT_BATCH(SET_FIELD(src_y
, BLT_Y
) | SET_FIELD(src_x
, BLT_X
));
605 OUT_BATCH((uint16_t)src_pitch
);
607 OUT_RELOC64(src_buffer
,
608 I915_GEM_DOMAIN_RENDER
, 0,
611 OUT_RELOC(src_buffer
,
612 I915_GEM_DOMAIN_RENDER
, 0,
616 ADVANCE_BATCH_TILED(dst_y_tiled
, src_y_tiled
);
618 brw_emit_mi_flush(brw
);
624 intelEmitImmediateColorExpandBlit(struct brw_context
*brw
,
626 GLubyte
*src_bits
, GLuint src_size
,
629 struct brw_bo
*dst_buffer
,
632 GLshort x
, GLshort y
,
633 GLshort w
, GLshort h
,
636 int dwords
= ALIGN(src_size
, 8) / 4;
637 uint32_t opcode
, br13
, blit_cmd
;
639 if (dst_tiling
!= I915_TILING_NONE
) {
640 if (dst_offset
& 4095)
642 if (dst_tiling
== I915_TILING_Y
)
646 assert((logic_op
>= GL_CLEAR
) && (logic_op
<= (GL_CLEAR
+ 0x0f)));
647 assert(dst_pitch
> 0);
652 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
654 dst_buffer
, dst_pitch
, dst_offset
, x
, y
, w
, h
, src_size
, dwords
);
656 unsigned xy_setup_blt_length
= brw
->gen
>= 8 ? 10 : 8;
657 intel_batchbuffer_require_space(brw
, (xy_setup_blt_length
* 4) +
658 (3 * 4) + dwords
* 4, BLT_RING
);
660 opcode
= XY_SETUP_BLT_CMD
;
662 opcode
|= XY_BLT_WRITE_ALPHA
| XY_BLT_WRITE_RGB
;
663 if (dst_tiling
!= I915_TILING_NONE
) {
664 opcode
|= XY_DST_TILED
;
668 br13
= dst_pitch
| (translate_raster_op(logic_op
) << 16) | (1 << 29);
669 br13
|= br13_for_cpp(cpp
);
671 blit_cmd
= XY_TEXT_IMMEDIATE_BLIT_CMD
| XY_TEXT_BYTE_PACKED
; /* packing? */
672 if (dst_tiling
!= I915_TILING_NONE
)
673 blit_cmd
|= XY_DST_TILED
;
675 BEGIN_BATCH_BLT(xy_setup_blt_length
+ 3);
676 OUT_BATCH(opcode
| (xy_setup_blt_length
- 2));
678 OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
679 OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
681 OUT_RELOC64(dst_buffer
,
682 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
685 OUT_RELOC(dst_buffer
,
686 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
689 OUT_BATCH(0); /* bg */
690 OUT_BATCH(fg_color
); /* fg */
691 OUT_BATCH(0); /* pattern base addr */
695 OUT_BATCH(blit_cmd
| ((3 - 2) + dwords
));
696 OUT_BATCH(SET_FIELD(y
, BLT_Y
) | SET_FIELD(x
, BLT_X
));
697 OUT_BATCH(SET_FIELD(y
+ h
, BLT_Y
) | SET_FIELD(x
+ w
, BLT_X
));
700 intel_batchbuffer_data(brw
, src_bits
, dwords
* 4, BLT_RING
);
702 brw_emit_mi_flush(brw
);
707 /* We don't have a memmove-type blit like some other hardware, so we'll do a
708 * rectangular blit covering a large space, then emit 1-scanline blit at the
709 * end to cover the last if we need.
712 intel_emit_linear_blit(struct brw_context
*brw
,
713 struct brw_bo
*dst_bo
,
714 unsigned int dst_offset
,
715 struct brw_bo
*src_bo
,
716 unsigned int src_offset
,
719 struct gl_context
*ctx
= &brw
->ctx
;
720 GLuint pitch
, height
;
721 int16_t src_x
, dst_x
;
725 /* The pitch given to the GPU must be DWORD aligned, and
726 * we want width to match pitch. Max width is (1 << 15 - 1),
727 * rounding that down to the nearest DWORD is 1 << 15 - 4
729 pitch
= ROUND_DOWN_TO(MIN2(size
, (1 << 15) - 64), 4);
730 height
= (size
< pitch
|| pitch
== 0) ? 1 : size
/ pitch
;
732 src_x
= src_offset
% 64;
733 dst_x
= dst_offset
% 64;
734 pitch
= ALIGN(MIN2(size
, (1 << 15) - 64), 4);
735 assert(src_x
+ pitch
< 1 << 15);
736 assert(dst_x
+ pitch
< 1 << 15);
738 ok
= intelEmitCopyBlit(brw
, 1,
739 pitch
, src_bo
, src_offset
- src_x
, I915_TILING_NONE
,
740 pitch
, dst_bo
, dst_offset
- dst_x
, I915_TILING_NONE
,
741 src_x
, 0, /* src x/y */
742 dst_x
, 0, /* dst x/y */
743 MIN2(size
, pitch
), height
, /* w, h */
746 _mesa_problem(ctx
, "Failed to linear blit %dx%d\n",
747 MIN2(size
, pitch
), height
);
762 * Used to initialize the alpha value of an ARGB8888 miptree after copying
763 * into it from an XRGB8888 source.
765 * This is very common with glCopyTexImage2D(). Note that the coordinates are
766 * relative to the start of the miptree, not relative to a slice within the
770 intel_miptree_set_alpha_to_one(struct brw_context
*brw
,
771 struct intel_mipmap_tree
*mt
,
772 int x
, int y
, int width
, int height
)
780 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
781 __func__
, mt
->bo
, pitch
, x
, y
, width
, height
);
783 BR13
= br13_for_cpp(cpp
) | 0xf0 << 16;
784 CMD
= XY_COLOR_BLT_CMD
;
785 CMD
|= XY_BLT_WRITE_ALPHA
;
787 if (mt
->tiling
!= I915_TILING_NONE
) {
793 /* do space check before going any further */
794 if (!brw_batch_has_aperture_space(brw
, mt
->bo
->size
))
795 intel_batchbuffer_flush(brw
);
797 unsigned length
= brw
->gen
>= 8 ? 7 : 6;
798 bool dst_y_tiled
= mt
->tiling
== I915_TILING_Y
;
800 /* We need to split the blit into chunks that each fit within the blitter's
801 * restrictions. We can't use a chunk size of 32768 because we need to
802 * ensure that src_tile_x + chunk_size fits. We choose 16384 because it's
803 * a nice round power of two, big enough that performance won't suffer, and
804 * small enough to guarantee everything fits.
806 const uint32_t max_chunk_size
= 16384;
808 for (uint32_t chunk_x
= 0; chunk_x
< width
; chunk_x
+= max_chunk_size
) {
809 for (uint32_t chunk_y
= 0; chunk_y
< height
; chunk_y
+= max_chunk_size
) {
810 const uint32_t chunk_w
= MIN2(max_chunk_size
, width
- chunk_x
);
811 const uint32_t chunk_h
= MIN2(max_chunk_size
, height
- chunk_y
);
813 uint32_t offset
, tile_x
, tile_y
;
814 get_blit_intratile_offset_el(brw
, mt
,
815 x
+ chunk_x
, y
+ chunk_y
,
816 &offset
, &tile_x
, &tile_y
);
818 BEGIN_BATCH_BLT_TILED(length
, dst_y_tiled
, false);
819 OUT_BATCH(CMD
| (length
- 2));
821 OUT_BATCH(SET_FIELD(y
+ chunk_y
, BLT_Y
) |
822 SET_FIELD(x
+ chunk_x
, BLT_X
));
823 OUT_BATCH(SET_FIELD(y
+ chunk_y
+ chunk_h
, BLT_Y
) |
824 SET_FIELD(x
+ chunk_x
+ chunk_w
, BLT_X
));
827 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
831 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
834 OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
835 ADVANCE_BATCH_TILED(dst_y_tiled
, false);
839 brw_emit_mi_flush(brw
);