2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "main/mtypes.h"
27 #include "main/blit.h"
28 #include "main/context.h"
29 #include "main/enums.h"
30 #include "main/fbobject.h"
32 #include "brw_context.h"
33 #include "brw_defines.h"
34 #include "intel_blit.h"
35 #include "intel_buffers.h"
36 #include "intel_fbo.h"
37 #include "intel_batchbuffer.h"
38 #include "intel_mipmap_tree.h"
40 #define FILE_DEBUG_FLAG DEBUG_BLIT
42 #define SET_TILING_XY_FAST_COPY_BLT(tiling, tr_mode, type) \
46 CMD |= type ## _TILED_X; \
49 if (tr_mode == INTEL_MIPTREE_TRMODE_YS) \
50 CMD |= type ## _TILED_64K; \
52 CMD |= type ## _TILED_Y; \
55 unreachable("not reached"); \
60 intel_miptree_set_alpha_to_one(struct brw_context
*brw
,
61 struct intel_mipmap_tree
*mt
,
62 int x
, int y
, int width
, int height
);
64 static GLuint
translate_raster_op(GLenum logicop
)
67 case GL_CLEAR
: return 0x00;
68 case GL_AND
: return 0x88;
69 case GL_AND_REVERSE
: return 0x44;
70 case GL_COPY
: return 0xCC;
71 case GL_AND_INVERTED
: return 0x22;
72 case GL_NOOP
: return 0xAA;
73 case GL_XOR
: return 0x66;
74 case GL_OR
: return 0xEE;
75 case GL_NOR
: return 0x11;
76 case GL_EQUIV
: return 0x99;
77 case GL_INVERT
: return 0x55;
78 case GL_OR_REVERSE
: return 0xDD;
79 case GL_COPY_INVERTED
: return 0x33;
80 case GL_OR_INVERTED
: return 0xBB;
81 case GL_NAND
: return 0x77;
82 case GL_SET
: return 0xFF;
102 unreachable("not reached");
107 * Emits the packet for switching the blitter from X to Y tiled or back.
109 * This has to be called in a single BEGIN_BATCH_BLT_TILED() /
110 * ADVANCE_BATCH_TILED(). This is because BCS_SWCTRL is saved and restored as
111 * part of the power context, not a render context, and if the batchbuffer was
112 * to get flushed between setting and blitting, or blitting and restoring, our
113 * tiling state would leak into other unsuspecting applications (like the X
117 set_blitter_tiling(struct brw_context
*brw
,
118 bool dst_y_tiled
, bool src_y_tiled
,
121 assert(brw
->gen
>= 6);
123 /* Idle the blitter before we update how tiling is interpreted. */
124 OUT_BATCH(MI_FLUSH_DW
);
129 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
130 OUT_BATCH(BCS_SWCTRL
);
131 OUT_BATCH((BCS_SWCTRL_DST_Y
| BCS_SWCTRL_SRC_Y
) << 16 |
132 (dst_y_tiled
? BCS_SWCTRL_DST_Y
: 0) |
133 (src_y_tiled
? BCS_SWCTRL_SRC_Y
: 0));
136 #define SET_BLITTER_TILING(...) __map = set_blitter_tiling(__VA_ARGS__, __map)
138 #define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled) \
139 BEGIN_BATCH_BLT(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0)); \
140 if (dst_y_tiled || src_y_tiled) \
141 SET_BLITTER_TILING(brw, dst_y_tiled, src_y_tiled)
143 #define ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled) \
144 if (dst_y_tiled || src_y_tiled) \
145 SET_BLITTER_TILING(brw, false, false); \
149 blt_pitch(struct intel_mipmap_tree
*mt
)
151 int pitch
= mt
->pitch
;
158 intel_miptree_blit_compatible_formats(mesa_format src
, mesa_format dst
)
160 /* The BLT doesn't handle sRGB conversion */
161 assert(src
== _mesa_get_srgb_format_linear(src
));
162 assert(dst
== _mesa_get_srgb_format_linear(dst
));
164 /* No swizzle or format conversions possible, except... */
168 /* ...we can either discard the alpha channel when going from A->X,
169 * or we can fill the alpha channel with 0xff when going from X->A
171 if (src
== MESA_FORMAT_B8G8R8A8_UNORM
|| src
== MESA_FORMAT_B8G8R8X8_UNORM
)
172 return (dst
== MESA_FORMAT_B8G8R8A8_UNORM
||
173 dst
== MESA_FORMAT_B8G8R8X8_UNORM
);
175 if (src
== MESA_FORMAT_R8G8B8A8_UNORM
|| src
== MESA_FORMAT_R8G8B8X8_UNORM
)
176 return (dst
== MESA_FORMAT_R8G8B8A8_UNORM
||
177 dst
== MESA_FORMAT_R8G8B8X8_UNORM
);
183 get_blit_intratile_offset_el(const struct brw_context
*brw
,
184 struct intel_mipmap_tree
*mt
,
185 uint32_t total_x_offset_el
,
186 uint32_t total_y_offset_el
,
187 uint32_t *base_address_offset
,
188 uint32_t *x_offset_el
,
189 uint32_t *y_offset_el
)
191 enum isl_tiling tiling
= intel_miptree_get_isl_tiling(mt
);
192 isl_tiling_get_intratile_offset_el(&brw
->isl_dev
,
193 tiling
, mt
->cpp
, mt
->pitch
,
194 total_x_offset_el
, total_y_offset_el
,
196 x_offset_el
, y_offset_el
);
197 if (tiling
== ISL_TILING_LINEAR
) {
198 /* From the Broadwell PRM docs for XY_SRC_COPY_BLT::SourceBaseAddress:
200 * "Base address of the destination surface: X=0, Y=0. Lower 32bits
201 * of the 48bit addressing. When Src Tiling is enabled (Bit_15
202 * enabled), this address must be 4KB-aligned. When Tiling is not
203 * enabled, this address should be CL (64byte) aligned."
205 * The offsets we get from ISL in the tiled case are already aligned.
206 * In the linear case, we need to do some of our own aligning.
208 assert(mt
->pitch
% 64 == 0);
209 uint32_t delta
= *base_address_offset
& 63;
210 assert(delta
% mt
->cpp
== 0);
211 *base_address_offset
-= delta
;
212 *x_offset_el
+= delta
/ mt
->cpp
;
214 assert(*base_address_offset
% 4096 == 0);
219 * Implements a rectangular block transfer (blit) of pixels between two
222 * Our blitter can operate on 1, 2, or 4-byte-per-pixel data, with generous,
223 * but limited, pitches and sizes allowed.
225 * The src/dst coordinates are relative to the given level/slice of the
228 * If @src_flip or @dst_flip is set, then the rectangle within that miptree
229 * will be inverted (including scanline order) when copying. This is common
230 * in GL when copying between window system and user-created
231 * renderbuffers/textures.
234 intel_miptree_blit(struct brw_context
*brw
,
235 struct intel_mipmap_tree
*src_mt
,
236 int src_level
, int src_slice
,
237 uint32_t src_x
, uint32_t src_y
, bool src_flip
,
238 struct intel_mipmap_tree
*dst_mt
,
239 int dst_level
, int dst_slice
,
240 uint32_t dst_x
, uint32_t dst_y
, bool dst_flip
,
241 uint32_t width
, uint32_t height
,
244 /* The blitter doesn't understand multisampling at all. */
245 if (src_mt
->num_samples
> 0 || dst_mt
->num_samples
> 0)
248 /* No sRGB decode or encode is done by the hardware blitter, which is
249 * consistent with what we want in many callers (glCopyTexSubImage(),
250 * texture validation, etc.).
252 mesa_format src_format
= _mesa_get_srgb_format_linear(src_mt
->format
);
253 mesa_format dst_format
= _mesa_get_srgb_format_linear(dst_mt
->format
);
255 /* The blitter doesn't support doing any format conversions. We do also
256 * support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into
257 * the X channel don't matter), and XRGB8888 to ARGB8888 by setting the A
258 * channel to 1.0 at the end.
260 if (!intel_miptree_blit_compatible_formats(src_format
, dst_format
)) {
261 perf_debug("%s: Can't use hardware blitter from %s to %s, "
262 "falling back.\n", __func__
,
263 _mesa_get_format_name(src_format
),
264 _mesa_get_format_name(dst_format
));
268 /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
269 * Data Size Limitations):
271 * The BLT engine is capable of transferring very large quantities of
272 * graphics data. Any graphics data read from and written to the
273 * destination is permitted to represent a number of pixels that
274 * occupies up to 65,536 scan lines and up to 32,768 bytes per scan line
275 * at the destination. The maximum number of pixels that may be
276 * represented per scan line’s worth of graphics data depends on the
279 * Furthermore, intelEmitCopyBlit (which is called below) uses a signed
280 * 16-bit integer to represent buffer pitch, so it can only handle buffer
281 * pitches < 32k. However, the pitch is measured in bytes for linear buffers
282 * and dwords for tiled buffers.
284 * As a result of these two limitations, we can only use the blitter to do
285 * this copy when the miptree's pitch is less than 32k linear or 128k tiled.
287 if (blt_pitch(src_mt
) >= 32768 || blt_pitch(dst_mt
) >= 32768) {
288 perf_debug("Falling back due to >= 32k/128k pitch\n");
292 /* The blitter has no idea about HiZ or fast color clears, so we need to
293 * resolve the miptrees before we do anything.
295 intel_miptree_slice_resolve_depth(brw
, src_mt
, src_level
, src_slice
);
296 intel_miptree_slice_resolve_depth(brw
, dst_mt
, dst_level
, dst_slice
);
297 intel_miptree_resolve_color(brw
, src_mt
, 0);
298 intel_miptree_resolve_color(brw
, dst_mt
, 0);
301 src_y
= minify(src_mt
->physical_height0
, src_level
- src_mt
->first_level
) - src_y
- height
;
304 dst_y
= minify(dst_mt
->physical_height0
, dst_level
- dst_mt
->first_level
) - dst_y
- height
;
306 uint32_t src_image_x
, src_image_y
, dst_image_x
, dst_image_y
;
307 intel_miptree_get_image_offset(src_mt
, src_level
, src_slice
,
308 &src_image_x
, &src_image_y
);
309 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_slice
,
310 &dst_image_x
, &dst_image_y
);
311 src_x
+= src_image_x
;
312 src_y
+= src_image_y
;
313 dst_x
+= dst_image_x
;
314 dst_y
+= dst_image_y
;
316 /* We need to split the blit into chunks that each fit within the blitter's
317 * restrictions. We can't use a chunk size of 32768 because we need to
318 * ensure that src_tile_x + chunk_size fits. We choose 16384 because it's
319 * a nice round power of two, big enough that performance won't suffer, and
320 * small enough to guarantee everything fits.
322 const uint32_t max_chunk_size
= 16384;
324 for (uint32_t chunk_x
= 0; chunk_x
< width
; chunk_x
+= max_chunk_size
) {
325 for (uint32_t chunk_y
= 0; chunk_y
< height
; chunk_y
+= max_chunk_size
) {
326 const uint32_t chunk_w
= MIN2(max_chunk_size
, width
- chunk_x
);
327 const uint32_t chunk_h
= MIN2(max_chunk_size
, height
- chunk_y
);
329 uint32_t src_offset
, src_tile_x
, src_tile_y
;
330 get_blit_intratile_offset_el(brw
, src_mt
,
331 src_x
+ chunk_x
, src_y
+ chunk_y
,
332 &src_offset
, &src_tile_x
, &src_tile_y
);
334 uint32_t dst_offset
, dst_tile_x
, dst_tile_y
;
335 get_blit_intratile_offset_el(brw
, dst_mt
,
336 dst_x
+ chunk_x
, dst_y
+ chunk_y
,
337 &dst_offset
, &dst_tile_x
, &dst_tile_y
);
339 if (!intelEmitCopyBlit(brw
,
341 src_flip
== dst_flip
? src_mt
->pitch
:
343 src_mt
->bo
, src_mt
->offset
+ src_offset
,
347 dst_mt
->bo
, dst_mt
->offset
+ dst_offset
,
350 src_tile_x
, src_tile_y
,
351 dst_tile_x
, dst_tile_y
,
354 /* If this is ever going to fail, it will fail on the first chunk */
355 assert(chunk_x
== 0 && chunk_y
== 0);
361 /* XXX This could be done in a single pass using XY_FULL_MONO_PATTERN_BLT */
362 if (_mesa_get_format_bits(src_format
, GL_ALPHA_BITS
) == 0 &&
363 _mesa_get_format_bits(dst_format
, GL_ALPHA_BITS
) > 0) {
364 intel_miptree_set_alpha_to_one(brw
, dst_mt
,
373 alignment_valid(struct brw_context
*brw
, unsigned offset
, uint32_t tiling
)
375 /* Tiled buffers must be page-aligned (4K). */
376 if (tiling
!= I915_TILING_NONE
)
377 return (offset
& 4095) == 0;
379 /* On Gen8+, linear buffers must be cacheline-aligned. */
381 return (offset
& 63) == 0;
387 can_fast_copy_blit(struct brw_context
*brw
,
388 drm_intel_bo
*src_buffer
,
389 int16_t src_x
, int16_t src_y
,
390 uintptr_t src_offset
, uint32_t src_pitch
,
391 uint32_t src_tiling
, uint32_t src_tr_mode
,
392 drm_intel_bo
*dst_buffer
,
393 int16_t dst_x
, int16_t dst_y
,
394 uintptr_t dst_offset
, uint32_t dst_pitch
,
395 uint32_t dst_tiling
, uint32_t dst_tr_mode
,
396 int16_t w
, int16_t h
, uint32_t cpp
,
399 const bool dst_tiling_none
= dst_tiling
== I915_TILING_NONE
;
400 const bool src_tiling_none
= src_tiling
== I915_TILING_NONE
;
405 /* Enable fast copy blit only if the surfaces are Yf/Ys tiled.
406 * FIXME: Based on performance data, remove this condition later to
407 * enable for all types of surfaces.
409 if (src_tr_mode
== INTEL_MIPTREE_TRMODE_NONE
&&
410 dst_tr_mode
== INTEL_MIPTREE_TRMODE_NONE
)
413 if (logic_op
!= GL_COPY
)
416 /* The start pixel for Fast Copy blit should be on an OWord boundary. */
417 if ((dst_x
* cpp
| src_x
* cpp
) & 15)
420 /* For all surface types buffers must be cacheline-aligned. */
421 if ((dst_offset
| src_offset
) & 63)
424 /* Color depths which are not power of 2 or greater than 128 bits are
427 if (!_mesa_is_pow_two(cpp
) || cpp
> 16)
430 /* For Fast Copy Blits the pitch cannot be a negative number. So, bit 15
431 * of the destination pitch must be zero.
433 if ((src_pitch
>> 15 & 1) != 0 || (dst_pitch
>> 15 & 1) != 0)
436 /* For Linear surfaces, the pitch has to be an OWord (16byte) multiple. */
437 if ((src_tiling_none
&& src_pitch
% 16 != 0) ||
438 (dst_tiling_none
&& dst_pitch
% 16 != 0))
445 xy_blit_cmd(uint32_t src_tiling
, uint32_t src_tr_mode
,
446 uint32_t dst_tiling
, uint32_t dst_tr_mode
,
447 uint32_t cpp
, bool use_fast_copy_blit
)
451 if (use_fast_copy_blit
) {
452 CMD
= XY_FAST_COPY_BLT_CMD
;
454 if (dst_tiling
!= I915_TILING_NONE
)
455 SET_TILING_XY_FAST_COPY_BLT(dst_tiling
, dst_tr_mode
, XY_FAST_DST
);
457 if (src_tiling
!= I915_TILING_NONE
)
458 SET_TILING_XY_FAST_COPY_BLT(src_tiling
, src_tr_mode
, XY_FAST_SRC
);
464 CMD
= XY_SRC_COPY_BLT_CMD
;
467 CMD
= XY_SRC_COPY_BLT_CMD
| XY_BLT_WRITE_ALPHA
| XY_BLT_WRITE_RGB
;
470 unreachable("not reached");
473 if (dst_tiling
!= I915_TILING_NONE
)
476 if (src_tiling
!= I915_TILING_NONE
)
485 intelEmitCopyBlit(struct brw_context
*brw
,
488 drm_intel_bo
*src_buffer
,
491 uint32_t src_tr_mode
,
493 drm_intel_bo
*dst_buffer
,
496 uint32_t dst_tr_mode
,
497 GLshort src_x
, GLshort src_y
,
498 GLshort dst_x
, GLshort dst_y
,
499 GLshort w
, GLshort h
,
502 GLuint CMD
, BR13
, pass
= 0;
503 int dst_y2
= dst_y
+ h
;
504 int dst_x2
= dst_x
+ w
;
505 drm_intel_bo
*aper_array
[3];
506 bool dst_y_tiled
= dst_tiling
== I915_TILING_Y
;
507 bool src_y_tiled
= src_tiling
== I915_TILING_Y
;
508 bool use_fast_copy_blit
= false;
509 uint32_t src_tile_w
, src_tile_h
;
510 uint32_t dst_tile_w
, dst_tile_h
;
512 if ((dst_y_tiled
|| src_y_tiled
) && brw
->gen
< 6)
515 /* do space check before going any further */
517 aper_array
[0] = brw
->batch
.bo
;
518 aper_array
[1] = dst_buffer
;
519 aper_array
[2] = src_buffer
;
521 if (dri_bufmgr_check_aperture_space(aper_array
, 3) != 0) {
522 intel_batchbuffer_flush(brw
);
531 unsigned length
= brw
->gen
>= 8 ? 10 : 8;
533 intel_batchbuffer_require_space(brw
, length
* 4, BLT_RING
);
534 DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
536 src_buffer
, src_pitch
, src_offset
, src_x
, src_y
,
537 dst_buffer
, dst_pitch
, dst_offset
, dst_x
, dst_y
, w
, h
);
539 intel_get_tile_dims(src_tiling
, src_tr_mode
, cpp
, &src_tile_w
, &src_tile_h
);
540 intel_get_tile_dims(dst_tiling
, dst_tr_mode
, cpp
, &dst_tile_w
, &dst_tile_h
);
542 /* For Tiled surfaces, the pitch has to be a multiple of the Tile width
543 * (X direction width of the Tile). This is ensured while allocating the
546 assert(src_tiling
== I915_TILING_NONE
|| (src_pitch
% src_tile_w
) == 0);
547 assert(dst_tiling
== I915_TILING_NONE
|| (dst_pitch
% dst_tile_w
) == 0);
549 use_fast_copy_blit
= can_fast_copy_blit(brw
,
552 src_offset
, src_pitch
,
553 src_tiling
, src_tr_mode
,
556 dst_offset
, dst_pitch
,
557 dst_tiling
, dst_tr_mode
,
558 w
, h
, cpp
, logic_op
);
559 if (!use_fast_copy_blit
&&
560 (src_tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
||
561 dst_tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
))
564 if (use_fast_copy_blit
) {
565 assert(logic_op
== GL_COPY
);
567 /* When two sequential fast copy blits have different source surfaces,
568 * but their destinations refer to the same destination surfaces and
569 * therefore destinations overlap it is imperative that a flush be
570 * inserted between the two blits.
572 * FIXME: Figure out a way to avoid flushing when not required.
574 brw_emit_mi_flush(brw
);
577 BR13
= br13_for_cpp(cpp
);
579 if (src_tr_mode
== INTEL_MIPTREE_TRMODE_YF
)
580 BR13
|= XY_FAST_SRC_TRMODE_YF
;
582 if (dst_tr_mode
== INTEL_MIPTREE_TRMODE_YF
)
583 BR13
|= XY_FAST_DST_TRMODE_YF
;
585 CMD
= xy_blit_cmd(src_tiling
, src_tr_mode
,
586 dst_tiling
, dst_tr_mode
,
587 cpp
, use_fast_copy_blit
);
590 /* For big formats (such as floating point), do the copy using 16 or
591 * 32bpp and multiply the coordinates.
600 assert(cpp
% 4 == 0);
608 if (!alignment_valid(brw
, dst_offset
, dst_tiling
))
610 if (!alignment_valid(brw
, src_offset
, src_tiling
))
613 /* Blit pitch must be dword-aligned. Otherwise, the hardware appears to drop
614 * the low bits. Offsets must be naturally aligned.
616 if (src_pitch
% 4 != 0 || src_offset
% cpp
!= 0 ||
617 dst_pitch
% 4 != 0 || dst_offset
% cpp
!= 0)
621 BR13
= br13_for_cpp(cpp
) | translate_raster_op(logic_op
) << 16;
623 CMD
= xy_blit_cmd(src_tiling
, src_tr_mode
,
624 dst_tiling
, dst_tr_mode
,
625 cpp
, use_fast_copy_blit
);
628 /* For tiled source and destination, pitch value should be specified
629 * as a number of Dwords.
631 if (dst_tiling
!= I915_TILING_NONE
)
634 if (src_tiling
!= I915_TILING_NONE
)
637 if (dst_y2
<= dst_y
|| dst_x2
<= dst_x
)
640 assert(dst_x
< dst_x2
);
641 assert(dst_y
< dst_y2
);
643 BEGIN_BATCH_BLT_TILED(length
, dst_y_tiled
, src_y_tiled
);
644 OUT_BATCH(CMD
| (length
- 2));
645 OUT_BATCH(BR13
| (uint16_t)dst_pitch
);
646 OUT_BATCH(SET_FIELD(dst_y
, BLT_Y
) | SET_FIELD(dst_x
, BLT_X
));
647 OUT_BATCH(SET_FIELD(dst_y2
, BLT_Y
) | SET_FIELD(dst_x2
, BLT_X
));
649 OUT_RELOC64(dst_buffer
,
650 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
653 OUT_RELOC(dst_buffer
,
654 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
657 OUT_BATCH(SET_FIELD(src_y
, BLT_Y
) | SET_FIELD(src_x
, BLT_X
));
658 OUT_BATCH((uint16_t)src_pitch
);
660 OUT_RELOC64(src_buffer
,
661 I915_GEM_DOMAIN_RENDER
, 0,
664 OUT_RELOC(src_buffer
,
665 I915_GEM_DOMAIN_RENDER
, 0,
669 ADVANCE_BATCH_TILED(dst_y_tiled
, src_y_tiled
);
671 brw_emit_mi_flush(brw
);
677 intelEmitImmediateColorExpandBlit(struct brw_context
*brw
,
679 GLubyte
*src_bits
, GLuint src_size
,
682 drm_intel_bo
*dst_buffer
,
685 GLshort x
, GLshort y
,
686 GLshort w
, GLshort h
,
689 int dwords
= ALIGN(src_size
, 8) / 4;
690 uint32_t opcode
, br13
, blit_cmd
;
692 if (dst_tiling
!= I915_TILING_NONE
) {
693 if (dst_offset
& 4095)
695 if (dst_tiling
== I915_TILING_Y
)
699 assert((logic_op
>= GL_CLEAR
) && (logic_op
<= (GL_CLEAR
+ 0x0f)));
700 assert(dst_pitch
> 0);
705 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
707 dst_buffer
, dst_pitch
, dst_offset
, x
, y
, w
, h
, src_size
, dwords
);
709 unsigned xy_setup_blt_length
= brw
->gen
>= 8 ? 10 : 8;
710 intel_batchbuffer_require_space(brw
, (xy_setup_blt_length
* 4) +
711 (3 * 4) + dwords
* 4, BLT_RING
);
713 opcode
= XY_SETUP_BLT_CMD
;
715 opcode
|= XY_BLT_WRITE_ALPHA
| XY_BLT_WRITE_RGB
;
716 if (dst_tiling
!= I915_TILING_NONE
) {
717 opcode
|= XY_DST_TILED
;
721 br13
= dst_pitch
| (translate_raster_op(logic_op
) << 16) | (1 << 29);
722 br13
|= br13_for_cpp(cpp
);
724 blit_cmd
= XY_TEXT_IMMEDIATE_BLIT_CMD
| XY_TEXT_BYTE_PACKED
; /* packing? */
725 if (dst_tiling
!= I915_TILING_NONE
)
726 blit_cmd
|= XY_DST_TILED
;
728 BEGIN_BATCH_BLT(xy_setup_blt_length
+ 3);
729 OUT_BATCH(opcode
| (xy_setup_blt_length
- 2));
731 OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
732 OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
734 OUT_RELOC64(dst_buffer
,
735 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
738 OUT_RELOC(dst_buffer
,
739 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
742 OUT_BATCH(0); /* bg */
743 OUT_BATCH(fg_color
); /* fg */
744 OUT_BATCH(0); /* pattern base addr */
748 OUT_BATCH(blit_cmd
| ((3 - 2) + dwords
));
749 OUT_BATCH(SET_FIELD(y
, BLT_Y
) | SET_FIELD(x
, BLT_X
));
750 OUT_BATCH(SET_FIELD(y
+ h
, BLT_Y
) | SET_FIELD(x
+ w
, BLT_X
));
753 intel_batchbuffer_data(brw
, src_bits
, dwords
* 4, BLT_RING
);
755 brw_emit_mi_flush(brw
);
760 /* We don't have a memmove-type blit like some other hardware, so we'll do a
761 * rectangular blit covering a large space, then emit 1-scanline blit at the
762 * end to cover the last if we need.
765 intel_emit_linear_blit(struct brw_context
*brw
,
766 drm_intel_bo
*dst_bo
,
767 unsigned int dst_offset
,
768 drm_intel_bo
*src_bo
,
769 unsigned int src_offset
,
772 struct gl_context
*ctx
= &brw
->ctx
;
773 GLuint pitch
, height
;
774 int16_t src_x
, dst_x
;
778 /* The pitch given to the GPU must be DWORD aligned, and
779 * we want width to match pitch. Max width is (1 << 15 - 1),
780 * rounding that down to the nearest DWORD is 1 << 15 - 4
782 pitch
= ROUND_DOWN_TO(MIN2(size
, (1 << 15) - 64), 4);
783 height
= (size
< pitch
|| pitch
== 0) ? 1 : size
/ pitch
;
785 src_x
= src_offset
% 64;
786 dst_x
= dst_offset
% 64;
787 pitch
= ALIGN(MIN2(size
, (1 << 15) - 64), 4);
788 assert(src_x
+ pitch
< 1 << 15);
789 assert(dst_x
+ pitch
< 1 << 15);
791 ok
= intelEmitCopyBlit(brw
, 1,
792 pitch
, src_bo
, src_offset
- src_x
, I915_TILING_NONE
,
793 INTEL_MIPTREE_TRMODE_NONE
,
794 pitch
, dst_bo
, dst_offset
- dst_x
, I915_TILING_NONE
,
795 INTEL_MIPTREE_TRMODE_NONE
,
796 src_x
, 0, /* src x/y */
797 dst_x
, 0, /* dst x/y */
798 MIN2(size
, pitch
), height
, /* w, h */
801 _mesa_problem(ctx
, "Failed to linear blit %dx%d\n",
802 MIN2(size
, pitch
), height
);
817 * Used to initialize the alpha value of an ARGB8888 miptree after copying
818 * into it from an XRGB8888 source.
820 * This is very common with glCopyTexImage2D(). Note that the coordinates are
821 * relative to the start of the miptree, not relative to a slice within the
825 intel_miptree_set_alpha_to_one(struct brw_context
*brw
,
826 struct intel_mipmap_tree
*mt
,
827 int x
, int y
, int width
, int height
)
831 drm_intel_bo
*aper_array
[2];
836 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
837 __func__
, mt
->bo
, pitch
, x
, y
, width
, height
);
839 BR13
= br13_for_cpp(cpp
) | 0xf0 << 16;
840 CMD
= XY_COLOR_BLT_CMD
;
841 CMD
|= XY_BLT_WRITE_ALPHA
;
843 if (mt
->tiling
!= I915_TILING_NONE
) {
849 /* do space check before going any further */
850 aper_array
[0] = brw
->batch
.bo
;
851 aper_array
[1] = mt
->bo
;
853 if (drm_intel_bufmgr_check_aperture_space(aper_array
,
854 ARRAY_SIZE(aper_array
)) != 0) {
855 intel_batchbuffer_flush(brw
);
858 unsigned length
= brw
->gen
>= 8 ? 7 : 6;
859 bool dst_y_tiled
= mt
->tiling
== I915_TILING_Y
;
861 /* We need to split the blit into chunks that each fit within the blitter's
862 * restrictions. We can't use a chunk size of 32768 because we need to
863 * ensure that src_tile_x + chunk_size fits. We choose 16384 because it's
864 * a nice round power of two, big enough that performance won't suffer, and
865 * small enough to guarantee everything fits.
867 const uint32_t max_chunk_size
= 16384;
869 for (uint32_t chunk_x
= 0; chunk_x
< width
; chunk_x
+= max_chunk_size
) {
870 for (uint32_t chunk_y
= 0; chunk_y
< height
; chunk_y
+= max_chunk_size
) {
871 const uint32_t chunk_w
= MIN2(max_chunk_size
, width
- chunk_x
);
872 const uint32_t chunk_h
= MIN2(max_chunk_size
, height
- chunk_y
);
874 uint32_t offset
, tile_x
, tile_y
;
875 get_blit_intratile_offset_el(brw
, mt
,
876 x
+ chunk_x
, y
+ chunk_y
,
877 &offset
, &tile_x
, &tile_y
);
879 BEGIN_BATCH_BLT_TILED(length
, dst_y_tiled
, false);
880 OUT_BATCH(CMD
| (length
- 2));
882 OUT_BATCH(SET_FIELD(y
+ chunk_y
, BLT_Y
) |
883 SET_FIELD(x
+ chunk_x
, BLT_X
));
884 OUT_BATCH(SET_FIELD(y
+ chunk_y
+ chunk_h
, BLT_Y
) |
885 SET_FIELD(x
+ chunk_x
+ chunk_w
, BLT_X
));
888 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
892 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
895 OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
896 ADVANCE_BATCH_TILED(dst_y_tiled
, false);
900 brw_emit_mi_flush(brw
);