2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "main/mtypes.h"
27 #include "main/blit.h"
28 #include "main/context.h"
29 #include "main/enums.h"
30 #include "main/fbobject.h"
32 #include "brw_context.h"
33 #include "brw_defines.h"
34 #include "intel_blit.h"
35 #include "intel_buffers.h"
36 #include "intel_fbo.h"
37 #include "intel_batchbuffer.h"
38 #include "intel_mipmap_tree.h"
40 #define FILE_DEBUG_FLAG DEBUG_BLIT
43 intel_miptree_set_alpha_to_one(struct brw_context
*brw
,
44 struct intel_mipmap_tree
*mt
,
45 int x
, int y
, int width
, int height
);
47 static GLuint
translate_raster_op(enum gl_logicop_mode logicop
)
49 return logicop
| (logicop
<< 4);
67 unreachable("not reached");
72 * Emits the packet for switching the blitter from X to Y tiled or back.
74 * This has to be called in a single BEGIN_BATCH_BLT_TILED() /
75 * ADVANCE_BATCH_TILED(). This is because BCS_SWCTRL is saved and restored as
76 * part of the power context, not a render context, and if the batchbuffer was
77 * to get flushed between setting and blitting, or blitting and restoring, our
78 * tiling state would leak into other unsuspecting applications (like the X
82 set_blitter_tiling(struct brw_context
*brw
,
83 bool dst_y_tiled
, bool src_y_tiled
,
86 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
87 const unsigned n_dwords
= devinfo
->gen
>= 8 ? 5 : 4;
88 assert(devinfo
->gen
>= 6);
90 /* Idle the blitter before we update how tiling is interpreted. */
91 OUT_BATCH(MI_FLUSH_DW
| (n_dwords
- 2));
98 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
99 OUT_BATCH(BCS_SWCTRL
);
100 OUT_BATCH((BCS_SWCTRL_DST_Y
| BCS_SWCTRL_SRC_Y
) << 16 |
101 (dst_y_tiled
? BCS_SWCTRL_DST_Y
: 0) |
102 (src_y_tiled
? BCS_SWCTRL_SRC_Y
: 0));
105 #define SET_BLITTER_TILING(...) __map = set_blitter_tiling(__VA_ARGS__, __map)
107 #define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled) \
108 unsigned set_tiling_batch_size = 0; \
109 if (dst_y_tiled || src_y_tiled) { \
110 if (devinfo->gen >= 8) \
111 set_tiling_batch_size = 16; \
113 set_tiling_batch_size = 14; \
115 BEGIN_BATCH_BLT(n + set_tiling_batch_size); \
116 if (dst_y_tiled || src_y_tiled) \
117 SET_BLITTER_TILING(brw, dst_y_tiled, src_y_tiled)
119 #define ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled) \
120 if (dst_y_tiled || src_y_tiled) \
121 SET_BLITTER_TILING(brw, false, false); \
125 blt_pitch(struct intel_mipmap_tree
*mt
)
127 int pitch
= mt
->surf
.row_pitch
;
128 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
)
134 intel_miptree_blit_compatible_formats(mesa_format src
, mesa_format dst
)
136 /* The BLT doesn't handle sRGB conversion */
137 assert(src
== _mesa_get_srgb_format_linear(src
));
138 assert(dst
== _mesa_get_srgb_format_linear(dst
));
140 /* No swizzle or format conversions possible, except... */
144 /* ...we can either discard the alpha channel when going from A->X,
145 * or we can fill the alpha channel with 0xff when going from X->A
147 if (src
== MESA_FORMAT_B8G8R8A8_UNORM
|| src
== MESA_FORMAT_B8G8R8X8_UNORM
)
148 return (dst
== MESA_FORMAT_B8G8R8A8_UNORM
||
149 dst
== MESA_FORMAT_B8G8R8X8_UNORM
);
151 if (src
== MESA_FORMAT_R8G8B8A8_UNORM
|| src
== MESA_FORMAT_R8G8B8X8_UNORM
)
152 return (dst
== MESA_FORMAT_R8G8B8A8_UNORM
||
153 dst
== MESA_FORMAT_R8G8B8X8_UNORM
);
155 /* We can also discard alpha when going from A2->X2 for 2 bit alpha,
156 * however we can't fill the alpha channel with two 1 bits when going
157 * from X2->A2, because intel_miptree_set_alpha_to_one() is not yet
158 * ready for this / can only handle 8 bit alpha.
160 if (src
== MESA_FORMAT_B10G10R10A2_UNORM
)
161 return (dst
== MESA_FORMAT_B10G10R10A2_UNORM
||
162 dst
== MESA_FORMAT_B10G10R10X2_UNORM
);
164 if (src
== MESA_FORMAT_R10G10B10A2_UNORM
)
165 return (dst
== MESA_FORMAT_R10G10B10A2_UNORM
||
166 dst
== MESA_FORMAT_R10G10B10X2_UNORM
);
172 get_blit_intratile_offset_el(const struct brw_context
*brw
,
173 struct intel_mipmap_tree
*mt
,
174 uint32_t total_x_offset_el
,
175 uint32_t total_y_offset_el
,
176 uint32_t *base_address_offset
,
177 uint32_t *x_offset_el
,
178 uint32_t *y_offset_el
)
180 isl_tiling_get_intratile_offset_el(mt
->surf
.tiling
,
181 mt
->cpp
* 8, mt
->surf
.row_pitch
,
182 total_x_offset_el
, total_y_offset_el
,
184 x_offset_el
, y_offset_el
);
185 if (mt
->surf
.tiling
== ISL_TILING_LINEAR
) {
186 /* From the Broadwell PRM docs for XY_SRC_COPY_BLT::SourceBaseAddress:
188 * "Base address of the destination surface: X=0, Y=0. Lower 32bits
189 * of the 48bit addressing. When Src Tiling is enabled (Bit_15
190 * enabled), this address must be 4KB-aligned. When Tiling is not
191 * enabled, this address should be CL (64byte) aligned."
193 * The offsets we get from ISL in the tiled case are already aligned.
194 * In the linear case, we need to do some of our own aligning.
196 uint32_t delta
= *base_address_offset
& 63;
197 assert(delta
% mt
->cpp
== 0);
198 *base_address_offset
-= delta
;
199 *x_offset_el
+= delta
/ mt
->cpp
;
201 assert(*base_address_offset
% 4096 == 0);
206 alignment_valid(struct brw_context
*brw
, unsigned offset
,
207 enum isl_tiling tiling
)
209 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
211 /* Tiled buffers must be page-aligned (4K). */
212 if (tiling
!= ISL_TILING_LINEAR
)
213 return (offset
& 4095) == 0;
215 /* On Gen8+, linear buffers must be cacheline-aligned. */
216 if (devinfo
->gen
>= 8)
217 return (offset
& 63) == 0;
223 xy_blit_cmd(enum isl_tiling src_tiling
, enum isl_tiling dst_tiling
,
232 CMD
= XY_SRC_COPY_BLT_CMD
;
235 CMD
= XY_SRC_COPY_BLT_CMD
| XY_BLT_WRITE_ALPHA
| XY_BLT_WRITE_RGB
;
238 unreachable("not reached");
241 if (dst_tiling
!= ISL_TILING_LINEAR
)
244 if (src_tiling
!= ISL_TILING_LINEAR
)
253 emit_copy_blit(struct brw_context
*brw
,
256 struct brw_bo
*src_buffer
,
258 enum isl_tiling src_tiling
,
260 struct brw_bo
*dst_buffer
,
262 enum isl_tiling dst_tiling
,
263 GLshort src_x
, GLshort src_y
,
264 GLshort dst_x
, GLshort dst_y
,
265 GLshort w
, GLshort h
,
266 enum gl_logicop_mode logic_op
)
268 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
270 int dst_y2
= dst_y
+ h
;
271 int dst_x2
= dst_x
+ w
;
272 bool dst_y_tiled
= dst_tiling
== ISL_TILING_Y0
;
273 bool src_y_tiled
= src_tiling
== ISL_TILING_Y0
;
274 uint32_t src_tile_w
, src_tile_h
;
275 uint32_t dst_tile_w
, dst_tile_h
;
277 if ((dst_y_tiled
|| src_y_tiled
) && devinfo
->gen
< 6)
280 const unsigned bo_sizes
= dst_buffer
->size
+ src_buffer
->size
;
282 /* do space check before going any further */
283 if (!brw_batch_has_aperture_space(brw
, bo_sizes
))
284 intel_batchbuffer_flush(brw
);
286 if (!brw_batch_has_aperture_space(brw
, bo_sizes
))
289 unsigned length
= devinfo
->gen
>= 8 ? 10 : 8;
291 intel_batchbuffer_require_space(brw
, length
* 4);
292 DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
294 src_buffer
, src_pitch
, src_offset
, src_x
, src_y
,
295 dst_buffer
, dst_pitch
, dst_offset
, dst_x
, dst_y
, w
, h
);
297 intel_get_tile_dims(src_tiling
, cpp
, &src_tile_w
, &src_tile_h
);
298 intel_get_tile_dims(dst_tiling
, cpp
, &dst_tile_w
, &dst_tile_h
);
300 /* For Tiled surfaces, the pitch has to be a multiple of the Tile width
301 * (X direction width of the Tile). This is ensured while allocating the
304 assert(src_tiling
== ISL_TILING_LINEAR
|| (src_pitch
% src_tile_w
) == 0);
305 assert(dst_tiling
== ISL_TILING_LINEAR
|| (dst_pitch
% dst_tile_w
) == 0);
307 /* For big formats (such as floating point), do the copy using 16 or
308 * 32bpp and multiply the coordinates.
317 assert(cpp
% 4 == 0);
325 if (!alignment_valid(brw
, dst_offset
, dst_tiling
))
327 if (!alignment_valid(brw
, src_offset
, src_tiling
))
330 /* Blit pitch must be dword-aligned. Otherwise, the hardware appears to drop
331 * the low bits. Offsets must be naturally aligned.
333 if (src_pitch
% 4 != 0 || src_offset
% cpp
!= 0 ||
334 dst_pitch
% 4 != 0 || dst_offset
% cpp
!= 0)
338 BR13
= br13_for_cpp(cpp
) | translate_raster_op(logic_op
) << 16;
340 CMD
= xy_blit_cmd(src_tiling
, dst_tiling
, cpp
);
342 /* For tiled source and destination, pitch value should be specified
343 * as a number of Dwords.
345 if (dst_tiling
!= ISL_TILING_LINEAR
)
348 if (src_tiling
!= ISL_TILING_LINEAR
)
351 if (dst_y2
<= dst_y
|| dst_x2
<= dst_x
)
354 assert(dst_x
< dst_x2
);
355 assert(dst_y
< dst_y2
);
357 BEGIN_BATCH_BLT_TILED(length
, dst_y_tiled
, src_y_tiled
);
358 OUT_BATCH(CMD
| (length
- 2));
359 OUT_BATCH(BR13
| (uint16_t)dst_pitch
);
360 OUT_BATCH(SET_FIELD(dst_y
, BLT_Y
) | SET_FIELD(dst_x
, BLT_X
));
361 OUT_BATCH(SET_FIELD(dst_y2
, BLT_Y
) | SET_FIELD(dst_x2
, BLT_X
));
362 if (devinfo
->gen
>= 8) {
363 OUT_RELOC64(dst_buffer
, RELOC_WRITE
, dst_offset
);
365 OUT_RELOC(dst_buffer
, RELOC_WRITE
, dst_offset
);
367 OUT_BATCH(SET_FIELD(src_y
, BLT_Y
) | SET_FIELD(src_x
, BLT_X
));
368 OUT_BATCH((uint16_t)src_pitch
);
369 if (devinfo
->gen
>= 8) {
370 OUT_RELOC64(src_buffer
, 0, src_offset
);
372 OUT_RELOC(src_buffer
, 0, src_offset
);
375 ADVANCE_BATCH_TILED(dst_y_tiled
, src_y_tiled
);
377 brw_emit_mi_flush(brw
);
383 emit_miptree_blit(struct brw_context
*brw
,
384 struct intel_mipmap_tree
*src_mt
,
385 uint32_t src_x
, uint32_t src_y
,
386 struct intel_mipmap_tree
*dst_mt
,
387 uint32_t dst_x
, uint32_t dst_y
,
388 uint32_t width
, uint32_t height
,
389 bool reverse
, enum gl_logicop_mode logicop
)
391 /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
392 * Data Size Limitations):
394 * The BLT engine is capable of transferring very large quantities of
395 * graphics data. Any graphics data read from and written to the
396 * destination is permitted to represent a number of pixels that
397 * occupies up to 65,536 scan lines and up to 32,768 bytes per scan line
398 * at the destination. The maximum number of pixels that may be
399 * represented per scan line’s worth of graphics data depends on the
402 * The blitter's pitch is a signed 16-bit integer, but measured in bytes
403 * for linear surfaces and DWords for tiled surfaces. So the maximum
404 * pitch is 32k linear and 128k tiled.
406 if (blt_pitch(src_mt
) >= 32768 || blt_pitch(dst_mt
) >= 32768) {
407 perf_debug("Falling back due to >= 32k/128k pitch\n");
411 /* We need to split the blit into chunks that each fit within the blitter's
412 * restrictions. We can't use a chunk size of 32768 because we need to
413 * ensure that src_tile_x + chunk_size fits. We choose 16384 because it's
414 * a nice round power of two, big enough that performance won't suffer, and
415 * small enough to guarantee everything fits.
417 const uint32_t max_chunk_size
= 16384;
419 for (uint32_t chunk_x
= 0; chunk_x
< width
; chunk_x
+= max_chunk_size
) {
420 for (uint32_t chunk_y
= 0; chunk_y
< height
; chunk_y
+= max_chunk_size
) {
421 const uint32_t chunk_w
= MIN2(max_chunk_size
, width
- chunk_x
);
422 const uint32_t chunk_h
= MIN2(max_chunk_size
, height
- chunk_y
);
424 uint32_t src_offset
, src_tile_x
, src_tile_y
;
425 get_blit_intratile_offset_el(brw
, src_mt
,
426 src_x
+ chunk_x
, src_y
+ chunk_y
,
427 &src_offset
, &src_tile_x
, &src_tile_y
);
429 uint32_t dst_offset
, dst_tile_x
, dst_tile_y
;
430 get_blit_intratile_offset_el(brw
, dst_mt
,
431 dst_x
+ chunk_x
, dst_y
+ chunk_y
,
432 &dst_offset
, &dst_tile_x
, &dst_tile_y
);
434 if (!emit_copy_blit(brw
,
436 reverse
? -src_mt
->surf
.row_pitch
:
437 src_mt
->surf
.row_pitch
,
438 src_mt
->bo
, src_mt
->offset
+ src_offset
,
440 dst_mt
->surf
.row_pitch
,
441 dst_mt
->bo
, dst_mt
->offset
+ dst_offset
,
443 src_tile_x
, src_tile_y
,
444 dst_tile_x
, dst_tile_y
,
447 /* If this is ever going to fail, it will fail on the first chunk */
448 assert(chunk_x
== 0 && chunk_y
== 0);
458 * Implements a rectangular block transfer (blit) of pixels between two
461 * Our blitter can operate on 1, 2, or 4-byte-per-pixel data, with generous,
462 * but limited, pitches and sizes allowed.
464 * The src/dst coordinates are relative to the given level/slice of the
467 * If @src_flip or @dst_flip is set, then the rectangle within that miptree
468 * will be inverted (including scanline order) when copying. This is common
469 * in GL when copying between window system and user-created
470 * renderbuffers/textures.
473 intel_miptree_blit(struct brw_context
*brw
,
474 struct intel_mipmap_tree
*src_mt
,
475 int src_level
, int src_slice
,
476 uint32_t src_x
, uint32_t src_y
, bool src_flip
,
477 struct intel_mipmap_tree
*dst_mt
,
478 int dst_level
, int dst_slice
,
479 uint32_t dst_x
, uint32_t dst_y
, bool dst_flip
,
480 uint32_t width
, uint32_t height
,
481 enum gl_logicop_mode logicop
)
483 /* The blitter doesn't understand multisampling at all. */
484 if (src_mt
->surf
.samples
> 1 || dst_mt
->surf
.samples
> 1)
487 /* No sRGB decode or encode is done by the hardware blitter, which is
488 * consistent with what we want in many callers (glCopyTexSubImage(),
489 * texture validation, etc.).
491 mesa_format src_format
= _mesa_get_srgb_format_linear(src_mt
->format
);
492 mesa_format dst_format
= _mesa_get_srgb_format_linear(dst_mt
->format
);
494 /* The blitter doesn't support doing any format conversions. We do also
495 * support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into
496 * the X channel don't matter), and XRGB8888 to ARGB8888 by setting the A
497 * channel to 1.0 at the end. Also trivially ARGB2101010 to XRGB2101010,
498 * but not XRGB2101010 to ARGB2101010 yet.
500 if (!intel_miptree_blit_compatible_formats(src_format
, dst_format
)) {
501 perf_debug("%s: Can't use hardware blitter from %s to %s, "
502 "falling back.\n", __func__
,
503 _mesa_get_format_name(src_format
),
504 _mesa_get_format_name(dst_format
));
508 /* The blitter has no idea about HiZ or fast color clears, so we need to
509 * resolve the miptrees before we do anything.
511 intel_miptree_access_raw(brw
, src_mt
, src_level
, src_slice
, false);
512 intel_miptree_access_raw(brw
, dst_mt
, dst_level
, dst_slice
, true);
515 const unsigned h0
= src_mt
->surf
.phys_level0_sa
.height
;
516 src_y
= minify(h0
, src_level
- src_mt
->first_level
) - src_y
- height
;
520 const unsigned h0
= dst_mt
->surf
.phys_level0_sa
.height
;
521 dst_y
= minify(h0
, dst_level
- dst_mt
->first_level
) - dst_y
- height
;
524 uint32_t src_image_x
, src_image_y
, dst_image_x
, dst_image_y
;
525 intel_miptree_get_image_offset(src_mt
, src_level
, src_slice
,
526 &src_image_x
, &src_image_y
);
527 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_slice
,
528 &dst_image_x
, &dst_image_y
);
529 src_x
+= src_image_x
;
530 src_y
+= src_image_y
;
531 dst_x
+= dst_image_x
;
532 dst_y
+= dst_image_y
;
534 if (!emit_miptree_blit(brw
, src_mt
, src_x
, src_y
,
535 dst_mt
, dst_x
, dst_y
, width
, height
,
536 src_flip
!= dst_flip
, logicop
)) {
540 /* XXX This could be done in a single pass using XY_FULL_MONO_PATTERN_BLT */
541 if (_mesa_get_format_bits(src_format
, GL_ALPHA_BITS
) == 0 &&
542 _mesa_get_format_bits(dst_format
, GL_ALPHA_BITS
) > 0) {
543 intel_miptree_set_alpha_to_one(brw
, dst_mt
,
552 intel_miptree_copy(struct brw_context
*brw
,
553 struct intel_mipmap_tree
*src_mt
,
554 int src_level
, int src_slice
,
555 uint32_t src_x
, uint32_t src_y
,
556 struct intel_mipmap_tree
*dst_mt
,
557 int dst_level
, int dst_slice
,
558 uint32_t dst_x
, uint32_t dst_y
,
559 uint32_t src_width
, uint32_t src_height
)
561 /* The blitter doesn't understand multisampling at all. */
562 if (src_mt
->surf
.samples
> 1 || dst_mt
->surf
.samples
> 1)
565 if (src_mt
->format
== MESA_FORMAT_S_UINT8
)
568 /* The blitter has no idea about HiZ or fast color clears, so we need to
569 * resolve the miptrees before we do anything.
571 intel_miptree_access_raw(brw
, src_mt
, src_level
, src_slice
, false);
572 intel_miptree_access_raw(brw
, dst_mt
, dst_level
, dst_slice
, true);
574 uint32_t src_image_x
, src_image_y
;
575 intel_miptree_get_image_offset(src_mt
, src_level
, src_slice
,
576 &src_image_x
, &src_image_y
);
578 if (_mesa_is_format_compressed(src_mt
->format
)) {
580 _mesa_get_format_block_size(src_mt
->format
, &bw
, &bh
);
582 /* Compressed textures need not have dimensions that are a multiple of
583 * the block size. Rectangles in compressed textures do need to be a
584 * multiple of the block size. The one exception is that the right and
585 * bottom edges may be at the right or bottom edge of the miplevel even
586 * if it's not aligned.
588 assert(src_x
% bw
== 0);
589 assert(src_y
% bh
== 0);
591 assert(src_width
% bw
== 0 ||
593 minify(src_mt
->surf
.logical_level0_px
.width
, src_level
));
594 assert(src_height
% bh
== 0 ||
595 src_y
+ src_height
==
596 minify(src_mt
->surf
.logical_level0_px
.height
, src_level
));
600 src_width
= DIV_ROUND_UP(src_width
, (int)bw
);
601 src_height
= DIV_ROUND_UP(src_height
, (int)bh
);
603 src_x
+= src_image_x
;
604 src_y
+= src_image_y
;
606 uint32_t dst_image_x
, dst_image_y
;
607 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_slice
,
608 &dst_image_x
, &dst_image_y
);
610 if (_mesa_is_format_compressed(dst_mt
->format
)) {
612 _mesa_get_format_block_size(dst_mt
->format
, &bw
, &bh
);
614 assert(dst_x
% bw
== 0);
615 assert(dst_y
% bh
== 0);
620 dst_x
+= dst_image_x
;
621 dst_y
+= dst_image_y
;
623 return emit_miptree_blit(brw
, src_mt
, src_x
, src_y
,
624 dst_mt
, dst_x
, dst_y
,
625 src_width
, src_height
, false, COLOR_LOGICOP_COPY
);
629 intelEmitImmediateColorExpandBlit(struct brw_context
*brw
,
631 GLubyte
*src_bits
, GLuint src_size
,
634 struct brw_bo
*dst_buffer
,
636 enum isl_tiling dst_tiling
,
637 GLshort x
, GLshort y
,
638 GLshort w
, GLshort h
,
639 enum gl_logicop_mode logic_op
)
641 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
642 int dwords
= ALIGN(src_size
, 8) / 4;
643 uint32_t opcode
, br13
, blit_cmd
;
645 if (dst_tiling
!= ISL_TILING_LINEAR
) {
646 if (dst_offset
& 4095)
648 if (dst_tiling
== ISL_TILING_Y0
)
652 assert((unsigned) logic_op
<= 0x0f);
653 assert(dst_pitch
> 0);
658 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
660 dst_buffer
, dst_pitch
, dst_offset
, x
, y
, w
, h
, src_size
, dwords
);
662 unsigned xy_setup_blt_length
= devinfo
->gen
>= 8 ? 10 : 8;
663 intel_batchbuffer_require_space(brw
, (xy_setup_blt_length
* 4) +
664 (3 * 4) + dwords
* 4);
666 opcode
= XY_SETUP_BLT_CMD
;
668 opcode
|= XY_BLT_WRITE_ALPHA
| XY_BLT_WRITE_RGB
;
669 if (dst_tiling
!= ISL_TILING_LINEAR
) {
670 opcode
|= XY_DST_TILED
;
674 br13
= dst_pitch
| (translate_raster_op(logic_op
) << 16) | (1 << 29);
675 br13
|= br13_for_cpp(cpp
);
677 blit_cmd
= XY_TEXT_IMMEDIATE_BLIT_CMD
| XY_TEXT_BYTE_PACKED
; /* packing? */
678 if (dst_tiling
!= ISL_TILING_LINEAR
)
679 blit_cmd
|= XY_DST_TILED
;
681 BEGIN_BATCH_BLT(xy_setup_blt_length
+ 3);
682 OUT_BATCH(opcode
| (xy_setup_blt_length
- 2));
684 OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
685 OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
686 if (devinfo
->gen
>= 8) {
687 OUT_RELOC64(dst_buffer
, RELOC_WRITE
, dst_offset
);
689 OUT_RELOC(dst_buffer
, RELOC_WRITE
, dst_offset
);
691 OUT_BATCH(0); /* bg */
692 OUT_BATCH(fg_color
); /* fg */
693 OUT_BATCH(0); /* pattern base addr */
694 if (devinfo
->gen
>= 8)
697 OUT_BATCH(blit_cmd
| ((3 - 2) + dwords
));
698 OUT_BATCH(SET_FIELD(y
, BLT_Y
) | SET_FIELD(x
, BLT_X
));
699 OUT_BATCH(SET_FIELD(y
+ h
, BLT_Y
) | SET_FIELD(x
+ w
, BLT_X
));
702 intel_batchbuffer_data(brw
, src_bits
, dwords
* 4);
704 brw_emit_mi_flush(brw
);
710 * Used to initialize the alpha value of an ARGB8888 miptree after copying
711 * into it from an XRGB8888 source.
713 * This is very common with glCopyTexImage2D(). Note that the coordinates are
714 * relative to the start of the miptree, not relative to a slice within the
718 intel_miptree_set_alpha_to_one(struct brw_context
*brw
,
719 struct intel_mipmap_tree
*mt
,
720 int x
, int y
, int width
, int height
)
722 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
726 pitch
= mt
->surf
.row_pitch
;
729 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
730 __func__
, mt
->bo
, pitch
, x
, y
, width
, height
);
732 /* Note: Currently only handles 8 bit alpha channel. Extension to < 8 Bit
733 * alpha channel would be likely possible via ROP code 0xfa instead of 0xf0
734 * and writing a suitable bit-mask instead of 0xffffffff.
736 BR13
= br13_for_cpp(cpp
) | 0xf0 << 16;
737 CMD
= XY_COLOR_BLT_CMD
;
738 CMD
|= XY_BLT_WRITE_ALPHA
;
740 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
) {
746 /* do space check before going any further */
747 if (!brw_batch_has_aperture_space(brw
, mt
->bo
->size
))
748 intel_batchbuffer_flush(brw
);
750 unsigned length
= devinfo
->gen
>= 8 ? 7 : 6;
751 const bool dst_y_tiled
= mt
->surf
.tiling
== ISL_TILING_Y0
;
753 /* We need to split the blit into chunks that each fit within the blitter's
754 * restrictions. We can't use a chunk size of 32768 because we need to
755 * ensure that src_tile_x + chunk_size fits. We choose 16384 because it's
756 * a nice round power of two, big enough that performance won't suffer, and
757 * small enough to guarantee everything fits.
759 const uint32_t max_chunk_size
= 16384;
761 for (uint32_t chunk_x
= 0; chunk_x
< width
; chunk_x
+= max_chunk_size
) {
762 for (uint32_t chunk_y
= 0; chunk_y
< height
; chunk_y
+= max_chunk_size
) {
763 const uint32_t chunk_w
= MIN2(max_chunk_size
, width
- chunk_x
);
764 const uint32_t chunk_h
= MIN2(max_chunk_size
, height
- chunk_y
);
766 uint32_t offset
, tile_x
, tile_y
;
767 get_blit_intratile_offset_el(brw
, mt
,
768 x
+ chunk_x
, y
+ chunk_y
,
769 &offset
, &tile_x
, &tile_y
);
771 BEGIN_BATCH_BLT_TILED(length
, dst_y_tiled
, false);
772 OUT_BATCH(CMD
| (length
- 2));
774 OUT_BATCH(SET_FIELD(y
+ chunk_y
, BLT_Y
) |
775 SET_FIELD(x
+ chunk_x
, BLT_X
));
776 OUT_BATCH(SET_FIELD(y
+ chunk_y
+ chunk_h
, BLT_Y
) |
777 SET_FIELD(x
+ chunk_x
+ chunk_w
, BLT_X
));
778 if (devinfo
->gen
>= 8) {
779 OUT_RELOC64(mt
->bo
, RELOC_WRITE
, mt
->offset
+ offset
);
781 OUT_RELOC(mt
->bo
, RELOC_WRITE
, mt
->offset
+ offset
);
783 OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
784 ADVANCE_BATCH_TILED(dst_y_tiled
, false);
788 brw_emit_mi_flush(brw
);