src/mesa/drivers/dri/i965/intel_blit.c

   1 /*
   2  * Copyright 2003 VMware, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include "main/mtypes.h"
  27 #include "main/blit.h"
  28 #include "main/context.h"
  29 #include "main/enums.h"
  30 #include "main/fbobject.h"
  31
  32 #include "brw_context.h"
  33 #include "brw_defines.h"
  34 #include "intel_blit.h"
  35 #include "intel_buffers.h"
  36 #include "intel_fbo.h"
  37 #include "intel_reg.h"
  38 #include "intel_batchbuffer.h"
  39 #include "intel_mipmap_tree.h"
  40
  41 #define FILE_DEBUG_FLAG DEBUG_BLIT
  42
  43 #define SET_TILING_XY_FAST_COPY_BLT(tiling, tr_mode, type)           \
  44 ({                                                                   \
  45    switch (tiling) {                                                 \
  46    case I915_TILING_X:                                               \
  47       CMD |= type ## _TILED_X;                                       \
  48       break;                                                         \
  49    case I915_TILING_Y:                                               \
  50       if (tr_mode == INTEL_MIPTREE_TRMODE_YS)                        \
  51          CMD |= type ## _TILED_64K;                                  \
  52       else                                                           \
  53          CMD |= type ## _TILED_Y;                                    \
  54       break;                                                         \
  55    default:                                                          \
  56       unreachable("not reached");                                    \
  57    }                                                                 \
  58 })
  59
  60 static void
  61 intel_miptree_set_alpha_to_one(struct brw_context *brw,
  62                                struct intel_mipmap_tree *mt,
  63                                int x, int y, int width, int height);
  64
  65 static GLuint translate_raster_op(GLenum logicop)
  66 {
  67    switch(logicop) {
  68    case GL_CLEAR: return 0x00;
  69    case GL_AND: return 0x88;
  70    case GL_AND_REVERSE: return 0x44;
  71    case GL_COPY: return 0xCC;
  72    case GL_AND_INVERTED: return 0x22;
  73    case GL_NOOP: return 0xAA;
  74    case GL_XOR: return 0x66;
  75    case GL_OR: return 0xEE;
  76    case GL_NOR: return 0x11;
  77    case GL_EQUIV: return 0x99;
  78    case GL_INVERT: return 0x55;
  79    case GL_OR_REVERSE: return 0xDD;
  80    case GL_COPY_INVERTED: return 0x33;
  81    case GL_OR_INVERTED: return 0xBB;
  82    case GL_NAND: return 0x77;
  83    case GL_SET: return 0xFF;
  84    default: return 0;
  85    }
  86 }
  87
  88 static uint32_t
  89 br13_for_cpp(int cpp)
  90 {
  91    switch (cpp) {
  92    case 16:
  93       return BR13_32323232;
  94    case 8:
  95       return BR13_16161616;
  96    case 4:
  97       return BR13_8888;
  98    case 2:
  99       return BR13_565;
 100    case 1:
 101       return BR13_8;
 102    default:
 103       unreachable("not reached");
 104    }
 105 }
 106
 107 /**
 108  * Emits the packet for switching the blitter from X to Y tiled or back.
 109  *
 110  * This has to be called in a single BEGIN_BATCH_BLT_TILED() /
 111  * ADVANCE_BATCH_TILED().  This is because BCS_SWCTRL is saved and restored as
 112  * part of the power context, not a render context, and if the batchbuffer was
 113  * to get flushed between setting and blitting, or blitting and restoring, our
 114  * tiling state would leak into other unsuspecting applications (like the X
 115  * server).
 116  */
 117 static uint32_t *
 118 set_blitter_tiling(struct brw_context *brw,
 119                    bool dst_y_tiled, bool src_y_tiled,
 120                    uint32_t *__map)
 121 {
 122    assert(brw->gen >= 6);
 123
 124    /* Idle the blitter before we update how tiling is interpreted. */
 125    OUT_BATCH(MI_FLUSH_DW);
 126    OUT_BATCH(0);
 127    OUT_BATCH(0);
 128    OUT_BATCH(0);
 129
 130    OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
 131    OUT_BATCH(BCS_SWCTRL);
 132    OUT_BATCH((BCS_SWCTRL_DST_Y | BCS_SWCTRL_SRC_Y) << 16 |
 133              (dst_y_tiled ? BCS_SWCTRL_DST_Y : 0) |
 134              (src_y_tiled ? BCS_SWCTRL_SRC_Y : 0));
 135    return __map;
 136 }
 137 #define SET_BLITTER_TILING(...) __map = set_blitter_tiling(__VA_ARGS__, __map)
 138
 139 #define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled)              \
 140       BEGIN_BATCH_BLT(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0));     \
 141       if (dst_y_tiled || src_y_tiled)                                   \
 142          SET_BLITTER_TILING(brw, dst_y_tiled, src_y_tiled)
 143
 144 #define ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled)                   \
 145       if (dst_y_tiled || src_y_tiled)                                   \
 146          SET_BLITTER_TILING(brw, false, false);                         \
 147       ADVANCE_BATCH()
 148
 149 static int
 150 blt_pitch(struct intel_mipmap_tree *mt)
 151 {
 152    int pitch = mt->pitch;
 153    if (mt->tiling)
 154       pitch /= 4;
 155    return pitch;
 156 }
 157
 158 bool
 159 intel_miptree_blit_compatible_formats(mesa_format src, mesa_format dst)
 160 {
 161    /* The BLT doesn't handle sRGB conversion */
 162    assert(src == _mesa_get_srgb_format_linear(src));
 163    assert(dst == _mesa_get_srgb_format_linear(dst));
 164
 165    /* No swizzle or format conversions possible, except... */
 166    if (src == dst)
 167       return true;
 168
 169    /* ...we can either discard the alpha channel when going from A->X,
 170     * or we can fill the alpha channel with 0xff when going from X->A
 171     */
 172    if (src == MESA_FORMAT_B8G8R8A8_UNORM || src == MESA_FORMAT_B8G8R8X8_UNORM)
 173       return (dst == MESA_FORMAT_B8G8R8A8_UNORM ||
 174               dst == MESA_FORMAT_B8G8R8X8_UNORM);
 175
 176    if (src == MESA_FORMAT_R8G8B8A8_UNORM || src == MESA_FORMAT_R8G8B8X8_UNORM)
 177       return (dst == MESA_FORMAT_R8G8B8A8_UNORM ||
 178               dst == MESA_FORMAT_R8G8B8X8_UNORM);
 179
 180    return false;
 181 }
 182
 183 /**
 184  * Implements a rectangular block transfer (blit) of pixels between two
 185  * miptrees.
 186  *
 187  * Our blitter can operate on 1, 2, or 4-byte-per-pixel data, with generous,
 188  * but limited, pitches and sizes allowed.
 189  *
 190  * The src/dst coordinates are relative to the given level/slice of the
 191  * miptree.
 192  *
 193  * If @src_flip or @dst_flip is set, then the rectangle within that miptree
 194  * will be inverted (including scanline order) when copying.  This is common
 195  * in GL when copying between window system and user-created
 196  * renderbuffers/textures.
 197  */
 198 bool
 199 intel_miptree_blit(struct brw_context *brw,
 200                    struct intel_mipmap_tree *src_mt,
 201                    int src_level, int src_slice,
 202                    uint32_t src_x, uint32_t src_y, bool src_flip,
 203                    struct intel_mipmap_tree *dst_mt,
 204                    int dst_level, int dst_slice,
 205                    uint32_t dst_x, uint32_t dst_y, bool dst_flip,
 206                    uint32_t width, uint32_t height,
 207                    GLenum logicop)
 208 {
 209    /* The blitter doesn't understand multisampling at all. */
 210    if (src_mt->num_samples > 0 || dst_mt->num_samples > 0)
 211       return false;
 212
 213    /* No sRGB decode or encode is done by the hardware blitter, which is
 214     * consistent with what we want in many callers (glCopyTexSubImage(),
 215     * texture validation, etc.).
 216     */
 217    mesa_format src_format = _mesa_get_srgb_format_linear(src_mt->format);
 218    mesa_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format);
 219
 220    /* The blitter doesn't support doing any format conversions.  We do also
 221     * support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into
 222     * the X channel don't matter), and XRGB8888 to ARGB8888 by setting the A
 223     * channel to 1.0 at the end.
 224     */
 225    if (!intel_miptree_blit_compatible_formats(src_format, dst_format)) {
 226       perf_debug("%s: Can't use hardware blitter from %s to %s, "
 227                  "falling back.\n", __func__,
 228                  _mesa_get_format_name(src_format),
 229                  _mesa_get_format_name(dst_format));
 230       return false;
 231    }
 232
 233    /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
 234     * Data Size Limitations):
 235     *
 236     *    The BLT engine is capable of transferring very large quantities of
 237     *    graphics data. Any graphics data read from and written to the
 238     *    destination is permitted to represent a number of pixels that
 239     *    occupies up to 65,536 scan lines and up to 32,768 bytes per scan line
 240     *    at the destination. The maximum number of pixels that may be
 241     *    represented per scan line’s worth of graphics data depends on the
 242     *    color depth.
 243     *
 244     * Furthermore, intelEmitCopyBlit (which is called below) uses a signed
 245     * 16-bit integer to represent buffer pitch, so it can only handle buffer
 246     * pitches < 32k. However, the pitch is measured in bytes for linear buffers
 247     * and dwords for tiled buffers.
 248     *
 249     * As a result of these two limitations, we can only use the blitter to do
 250     * this copy when the miptree's pitch is less than 32k linear or 128k tiled.
 251     */
 252    if (blt_pitch(src_mt) >= 32768 || blt_pitch(dst_mt) >= 32768) {
 253       perf_debug("Falling back due to >= 32k/128k pitch\n");
 254       return false;
 255    }
 256
 257    /* The blitter has no idea about HiZ or fast color clears, so we need to
 258     * resolve the miptrees before we do anything.
 259     */
 260    intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_slice);
 261    intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_slice);
 262    intel_miptree_resolve_color(brw, src_mt, 0);
 263    intel_miptree_resolve_color(brw, dst_mt, 0);
 264
 265    if (src_flip)
 266       src_y = minify(src_mt->physical_height0, src_level - src_mt->first_level) - src_y - height;
 267
 268    if (dst_flip)
 269       dst_y = minify(dst_mt->physical_height0, dst_level - dst_mt->first_level) - dst_y - height;
 270
 271    uint32_t src_image_x, src_image_y, dst_image_x, dst_image_y;
 272    intel_miptree_get_image_offset(src_mt, src_level, src_slice,
 273                                   &src_image_x, &src_image_y);
 274    intel_miptree_get_image_offset(dst_mt, dst_level, dst_slice,
 275                                   &dst_image_x, &dst_image_y);
 276    src_x += src_image_x;
 277    src_y += src_image_y;
 278    dst_x += dst_image_x;
 279    dst_y += dst_image_y;
 280
 281    /* The blitter interprets the 16-bit destination x/y as a signed 16-bit
 282     * value. The values we're working with are unsigned, so make sure we don't
 283     * overflow.
 284     */
 285    if (src_x >= 32768 || src_y >= 32768 || dst_x >= 32768 || dst_y >= 32768) {
 286       perf_debug("Falling back due to >=32k offset [src(%d, %d) dst(%d, %d)]\n",
 287                  src_x, src_y, dst_x, dst_y);
 288       return false;
 289    }
 290
 291    if (!intelEmitCopyBlit(brw,
 292                           src_mt->cpp,
 293                           src_flip == dst_flip ? src_mt->pitch : -src_mt->pitch,
 294                           src_mt->bo, src_mt->offset,
 295                           src_mt->tiling,
 296                           src_mt->tr_mode,
 297                           dst_mt->pitch,
 298                           dst_mt->bo, dst_mt->offset,
 299                           dst_mt->tiling,
 300                           dst_mt->tr_mode,
 301                           src_x, src_y,
 302                           dst_x, dst_y,
 303                           width, height,
 304                           logicop)) {
 305       return false;
 306    }
 307
 308    /* XXX This could be done in a single pass using XY_FULL_MONO_PATTERN_BLT */
 309    if (_mesa_get_format_bits(src_format, GL_ALPHA_BITS) == 0 &&
 310        _mesa_get_format_bits(dst_format, GL_ALPHA_BITS) > 0) {
 311       intel_miptree_set_alpha_to_one(brw, dst_mt,
 312                                      dst_x, dst_y,
 313                                      width, height);
 314    }
 315
 316    return true;
 317 }
 318
 319 static bool
 320 alignment_valid(struct brw_context *brw, unsigned offset, uint32_t tiling)
 321 {
 322    /* Tiled buffers must be page-aligned (4K). */
 323    if (tiling != I915_TILING_NONE)
 324       return (offset & 4095) == 0;
 325
 326    /* On Gen8+, linear buffers must be cacheline-aligned. */
 327    if (brw->gen >= 8)
 328       return (offset & 63) == 0;
 329
 330    return true;
 331 }
 332
 333 static bool
 334 can_fast_copy_blit(struct brw_context *brw,
 335                    drm_intel_bo *src_buffer,
 336                    int16_t src_x, int16_t src_y,
 337                    uintptr_t src_offset, uint32_t src_pitch,
 338                    uint32_t src_tiling, uint32_t src_tr_mode,
 339                    drm_intel_bo *dst_buffer,
 340                    int16_t dst_x, int16_t dst_y,
 341                    uintptr_t dst_offset, uint32_t dst_pitch,
 342                    uint32_t dst_tiling, uint32_t dst_tr_mode,
 343                    int16_t w, int16_t h, uint32_t cpp,
 344                    GLenum logic_op)
 345 {
 346    const bool dst_tiling_none = dst_tiling == I915_TILING_NONE;
 347    const bool src_tiling_none = src_tiling == I915_TILING_NONE;
 348
 349    if (brw->gen < 9)
 350       return false;
 351
 352    /* Enable fast copy blit only if the surfaces are Yf/Ys tiled.
 353     * FIXME: Based on performance data, remove this condition later to
 354     * enable for all types of surfaces.
 355     */
 356    if (src_tr_mode == INTEL_MIPTREE_TRMODE_NONE &&
 357        dst_tr_mode == INTEL_MIPTREE_TRMODE_NONE)
 358       return false;
 359
 360    if (logic_op != GL_COPY)
 361       return false;
 362
 363    /* The start pixel for Fast Copy blit should be on an OWord boundary. */
 364    if ((dst_x * cpp | src_x * cpp) & 15)
 365       return false;
 366
 367    /* For all surface types buffers must be cacheline-aligned. */
 368    if ((dst_offset | src_offset) & 63)
 369       return false;
 370
 371    /* Color depths which are not power of 2 or greater than 128 bits are
 372     * not supported.
 373     */
 374    if (!_mesa_is_pow_two(cpp) || cpp > 16)
 375       return false;
 376
 377    /* For Fast Copy Blits the pitch cannot be a negative number. So, bit 15
 378     * of the destination pitch must be zero.
 379     */
 380    if ((src_pitch >> 15 & 1) != 0 || (dst_pitch >> 15 & 1) != 0)
 381       return false;
 382
 383    /* For Linear surfaces, the pitch has to be an OWord (16byte) multiple. */
 384    if ((src_tiling_none && src_pitch % 16 != 0) ||
 385        (dst_tiling_none && dst_pitch % 16 != 0))
 386       return false;
 387
 388    return true;
 389 }
 390
 391 static uint32_t
 392 xy_blit_cmd(uint32_t src_tiling, uint32_t src_tr_mode,
 393             uint32_t dst_tiling, uint32_t dst_tr_mode,
 394             uint32_t cpp, bool use_fast_copy_blit)
 395 {
 396    uint32_t CMD = 0;
 397
 398    if (use_fast_copy_blit) {
 399       CMD = XY_FAST_COPY_BLT_CMD;
 400
 401       if (dst_tiling != I915_TILING_NONE)
 402          SET_TILING_XY_FAST_COPY_BLT(dst_tiling, dst_tr_mode, XY_FAST_DST);
 403
 404       if (src_tiling != I915_TILING_NONE)
 405          SET_TILING_XY_FAST_COPY_BLT(src_tiling, src_tr_mode, XY_FAST_SRC);
 406    } else {
 407       assert(cpp <= 4);
 408       switch (cpp) {
 409       case 1:
 410       case 2:
 411          CMD = XY_SRC_COPY_BLT_CMD;
 412          break;
 413       case 4:
 414          CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 415          break;
 416       default:
 417          unreachable("not reached");
 418       }
 419
 420       if (dst_tiling != I915_TILING_NONE)
 421          CMD |= XY_DST_TILED;
 422
 423       if (src_tiling != I915_TILING_NONE)
 424          CMD |= XY_SRC_TILED;
 425    }
 426    return CMD;
 427 }
 428
 429 /* Copy BitBlt
 430  */
 431 bool
 432 intelEmitCopyBlit(struct brw_context *brw,
 433                   GLuint cpp,
 434                   GLshort src_pitch,
 435                   drm_intel_bo *src_buffer,
 436                   GLuint src_offset,
 437                   uint32_t src_tiling,
 438                   uint32_t src_tr_mode,
 439                   GLshort dst_pitch,
 440                   drm_intel_bo *dst_buffer,
 441                   GLuint dst_offset,
 442                   uint32_t dst_tiling,
 443                   uint32_t dst_tr_mode,
 444                   GLshort src_x, GLshort src_y,
 445                   GLshort dst_x, GLshort dst_y,
 446                   GLshort w, GLshort h,
 447                   GLenum logic_op)
 448 {
 449    GLuint CMD, BR13, pass = 0;
 450    int dst_y2 = dst_y + h;
 451    int dst_x2 = dst_x + w;
 452    drm_intel_bo *aper_array[3];
 453    bool dst_y_tiled = dst_tiling == I915_TILING_Y;
 454    bool src_y_tiled = src_tiling == I915_TILING_Y;
 455    bool use_fast_copy_blit = false;
 456    uint32_t src_tile_w, src_tile_h;
 457    uint32_t dst_tile_w, dst_tile_h;
 458
 459    if ((dst_y_tiled || src_y_tiled) && brw->gen < 6)
 460       return false;
 461
 462    /* do space check before going any further */
 463    do {
 464        aper_array[0] = brw->batch.bo;
 465        aper_array[1] = dst_buffer;
 466        aper_array[2] = src_buffer;
 467
 468        if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
 469            intel_batchbuffer_flush(brw);
 470            pass++;
 471        } else
 472            break;
 473    } while (pass < 2);
 474
 475    if (pass >= 2)
 476       return false;
 477
 478    unsigned length = brw->gen >= 8 ? 10 : 8;
 479
 480    intel_batchbuffer_require_space(brw, length * 4, BLT_RING);
 481    DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
 482        __func__,
 483        src_buffer, src_pitch, src_offset, src_x, src_y,
 484        dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
 485
 486    intel_get_tile_dims(src_tiling, src_tr_mode, cpp, &src_tile_w, &src_tile_h);
 487    intel_get_tile_dims(dst_tiling, dst_tr_mode, cpp, &dst_tile_w, &dst_tile_h);
 488
 489    /* For Tiled surfaces, the pitch has to be a multiple of the Tile width
 490     * (X direction width of the Tile). This is ensured while allocating the
 491     * buffer object.
 492     */
 493    assert(src_tiling == I915_TILING_NONE || (src_pitch % src_tile_w) == 0);
 494    assert(dst_tiling == I915_TILING_NONE || (dst_pitch % dst_tile_w) == 0);
 495
 496    use_fast_copy_blit = can_fast_copy_blit(brw,
 497                                            src_buffer,
 498                                            src_x, src_y,
 499                                            src_offset, src_pitch,
 500                                            src_tiling, src_tr_mode,
 501                                            dst_buffer,
 502                                            dst_x, dst_y,
 503                                            dst_offset, dst_pitch,
 504                                            dst_tiling, dst_tr_mode,
 505                                            w, h, cpp, logic_op);
 506    if (!use_fast_copy_blit &&
 507        (src_tr_mode != INTEL_MIPTREE_TRMODE_NONE ||
 508         dst_tr_mode != INTEL_MIPTREE_TRMODE_NONE))
 509       return false;
 510
 511    if (use_fast_copy_blit) {
 512       assert(logic_op == GL_COPY);
 513
 514       /* When two sequential fast copy blits have different source surfaces,
 515        * but their destinations refer to the same destination surfaces and
 516        * therefore destinations overlap it is imperative that a flush be
 517        * inserted between the two blits.
 518        *
 519        * FIXME: Figure out a way to avoid flushing when not required.
 520        */
 521       brw_emit_mi_flush(brw);
 522
 523       assert(cpp <= 16);
 524       BR13 = br13_for_cpp(cpp);
 525
 526       if (src_tr_mode == INTEL_MIPTREE_TRMODE_YF)
 527          BR13 |= XY_FAST_SRC_TRMODE_YF;
 528
 529       if (dst_tr_mode == INTEL_MIPTREE_TRMODE_YF)
 530          BR13 |= XY_FAST_DST_TRMODE_YF;
 531
 532       CMD = xy_blit_cmd(src_tiling, src_tr_mode,
 533                         dst_tiling, dst_tr_mode,
 534                         cpp, use_fast_copy_blit);
 535
 536    } else {
 537       /* For big formats (such as floating point), do the copy using 16 or
 538        * 32bpp and multiply the coordinates.
 539        */
 540       if (cpp > 4) {
 541          if (cpp % 4 == 2) {
 542             dst_x *= cpp / 2;
 543             dst_x2 *= cpp / 2;
 544             src_x *= cpp / 2;
 545             cpp = 2;
 546          } else {
 547             assert(cpp % 4 == 0);
 548             dst_x *= cpp / 4;
 549             dst_x2 *= cpp / 4;
 550             src_x *= cpp / 4;
 551             cpp = 4;
 552          }
 553       }
 554
 555       if (!alignment_valid(brw, dst_offset, dst_tiling))
 556          return false;
 557       if (!alignment_valid(brw, src_offset, src_tiling))
 558          return false;
 559
 560       /* Blit pitch must be dword-aligned.  Otherwise, the hardware appears to drop
 561        * the low bits.  Offsets must be naturally aligned.
 562        */
 563       if (src_pitch % 4 != 0 || src_offset % cpp != 0 ||
 564           dst_pitch % 4 != 0 || dst_offset % cpp != 0)
 565          return false;
 566
 567       assert(cpp <= 4);
 568       BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16;
 569
 570       CMD = xy_blit_cmd(src_tiling, src_tr_mode,
 571                         dst_tiling, dst_tr_mode,
 572                         cpp, use_fast_copy_blit);
 573    }
 574
 575    /* For tiled source and destination, pitch value should be specified
 576     * as a number of Dwords.
 577     */
 578    if (dst_tiling != I915_TILING_NONE)
 579       dst_pitch /= 4;
 580
 581    if (src_tiling != I915_TILING_NONE)
 582       src_pitch /= 4;
 583
 584    if (dst_y2 <= dst_y || dst_x2 <= dst_x)
 585       return true;
 586
 587    assert(dst_x < dst_x2);
 588    assert(dst_y < dst_y2);
 589    assert(src_offset + (src_y + h - 1) * abs(src_pitch) +
 590           (w * cpp) <= src_buffer->size);
 591    assert(dst_offset + (dst_y + h - 1) * abs(dst_pitch) +
 592           (w * cpp) <= dst_buffer->size);
 593
 594    BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, src_y_tiled);
 595    OUT_BATCH(CMD | (length - 2));
 596    OUT_BATCH(BR13 | (uint16_t)dst_pitch);
 597    OUT_BATCH(SET_FIELD(dst_y, BLT_Y) | SET_FIELD(dst_x, BLT_X));
 598    OUT_BATCH(SET_FIELD(dst_y2, BLT_Y) | SET_FIELD(dst_x2, BLT_X));
 599    if (brw->gen >= 8) {
 600       OUT_RELOC64(dst_buffer,
 601                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 602                   dst_offset);
 603    } else {
 604       OUT_RELOC(dst_buffer,
 605                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 606                 dst_offset);
 607    }
 608    OUT_BATCH(SET_FIELD(src_y, BLT_Y) | SET_FIELD(src_x, BLT_X));
 609    OUT_BATCH((uint16_t)src_pitch);
 610    if (brw->gen >= 8) {
 611       OUT_RELOC64(src_buffer,
 612                   I915_GEM_DOMAIN_RENDER, 0,
 613                   src_offset);
 614    } else {
 615       OUT_RELOC(src_buffer,
 616                 I915_GEM_DOMAIN_RENDER, 0,
 617                 src_offset);
 618    }
 619
 620    ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled);
 621
 622    brw_emit_mi_flush(brw);
 623
 624    return true;
 625 }
 626
 627 bool
 628 intelEmitImmediateColorExpandBlit(struct brw_context *brw,
 629                                   GLuint cpp,
 630                                   GLubyte *src_bits, GLuint src_size,
 631                                   GLuint fg_color,
 632                                   GLshort dst_pitch,
 633                                   drm_intel_bo *dst_buffer,
 634                                   GLuint dst_offset,
 635                                   uint32_t dst_tiling,
 636                                   GLshort x, GLshort y,
 637                                   GLshort w, GLshort h,
 638                                   GLenum logic_op)
 639 {
 640    int dwords = ALIGN(src_size, 8) / 4;
 641    uint32_t opcode, br13, blit_cmd;
 642
 643    if (dst_tiling != I915_TILING_NONE) {
 644       if (dst_offset & 4095)
 645          return false;
 646       if (dst_tiling == I915_TILING_Y)
 647          return false;
 648    }
 649
 650    assert((logic_op >= GL_CLEAR) && (logic_op <= (GL_CLEAR + 0x0f)));
 651    assert(dst_pitch > 0);
 652
 653    if (w < 0 || h < 0)
 654       return true;
 655
 656    DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
 657        __func__,
 658        dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
 659
 660    unsigned xy_setup_blt_length = brw->gen >= 8 ? 10 : 8;
 661    intel_batchbuffer_require_space(brw, (xy_setup_blt_length * 4) +
 662                                         (3 * 4) + dwords * 4, BLT_RING);
 663
 664    opcode = XY_SETUP_BLT_CMD;
 665    if (cpp == 4)
 666       opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 667    if (dst_tiling != I915_TILING_NONE) {
 668       opcode |= XY_DST_TILED;
 669       dst_pitch /= 4;
 670    }
 671
 672    br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
 673    br13 |= br13_for_cpp(cpp);
 674
 675    blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
 676    if (dst_tiling != I915_TILING_NONE)
 677       blit_cmd |= XY_DST_TILED;
 678
 679    BEGIN_BATCH_BLT(xy_setup_blt_length + 3);
 680    OUT_BATCH(opcode | (xy_setup_blt_length - 2));
 681    OUT_BATCH(br13);
 682    OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
 683    OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
 684    if (brw->gen >= 8) {
 685       OUT_RELOC64(dst_buffer,
 686                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 687                   dst_offset);
 688    } else {
 689       OUT_RELOC(dst_buffer,
 690                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 691                 dst_offset);
 692    }
 693    OUT_BATCH(0); /* bg */
 694    OUT_BATCH(fg_color); /* fg */
 695    OUT_BATCH(0); /* pattern base addr */
 696    if (brw->gen >= 8)
 697       OUT_BATCH(0);
 698
 699    OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
 700    OUT_BATCH(SET_FIELD(y, BLT_Y) | SET_FIELD(x, BLT_X));
 701    OUT_BATCH(SET_FIELD(y + h, BLT_Y) | SET_FIELD(x + w, BLT_X));
 702    ADVANCE_BATCH();
 703
 704    intel_batchbuffer_data(brw, src_bits, dwords * 4, BLT_RING);
 705
 706    brw_emit_mi_flush(brw);
 707
 708    return true;
 709 }
 710
 711 /* We don't have a memmove-type blit like some other hardware, so we'll do a
 712  * rectangular blit covering a large space, then emit 1-scanline blit at the
 713  * end to cover the last if we need.
 714  */
 715 void
 716 intel_emit_linear_blit(struct brw_context *brw,
 717                        drm_intel_bo *dst_bo,
 718                        unsigned int dst_offset,
 719                        drm_intel_bo *src_bo,
 720                        unsigned int src_offset,
 721                        unsigned int size)
 722 {
 723    struct gl_context *ctx = &brw->ctx;
 724    GLuint pitch, height;
 725    int16_t src_x, dst_x;
 726    bool ok;
 727
 728    do {
 729       /* The pitch given to the GPU must be DWORD aligned, and
 730        * we want width to match pitch. Max width is (1 << 15 - 1),
 731        * rounding that down to the nearest DWORD is 1 << 15 - 4
 732        */
 733       pitch = ROUND_DOWN_TO(MIN2(size, (1 << 15) - 64), 4);
 734       height = (size < pitch || pitch == 0) ? 1 : size / pitch;
 735
 736       src_x = src_offset % 64;
 737       dst_x = dst_offset % 64;
 738       pitch = ALIGN(MIN2(size, (1 << 15) - 64), 4);
 739       assert(src_x + pitch < 1 << 15);
 740       assert(dst_x + pitch < 1 << 15);
 741
 742       ok = intelEmitCopyBlit(brw, 1,
 743                              pitch, src_bo, src_offset - src_x, I915_TILING_NONE,
 744                              INTEL_MIPTREE_TRMODE_NONE,
 745                              pitch, dst_bo, dst_offset - dst_x, I915_TILING_NONE,
 746                              INTEL_MIPTREE_TRMODE_NONE,
 747                              src_x, 0, /* src x/y */
 748                              dst_x, 0, /* dst x/y */
 749                              MIN2(size, pitch), height, /* w, h */
 750                              GL_COPY);
 751       if (!ok) {
 752          _mesa_problem(ctx, "Failed to linear blit %dx%d\n",
 753                        MIN2(size, pitch), height);
 754          return;
 755       }
 756
 757       pitch *= height;
 758       if (size <= pitch)
 759          return;
 760
 761       src_offset += pitch;
 762       dst_offset += pitch;
 763       size -= pitch;
 764    } while (1);
 765 }
 766
 767 /**
 768  * Used to initialize the alpha value of an ARGB8888 miptree after copying
 769  * into it from an XRGB8888 source.
 770  *
 771  * This is very common with glCopyTexImage2D().  Note that the coordinates are
 772  * relative to the start of the miptree, not relative to a slice within the
 773  * miptree.
 774  */
 775 static void
 776 intel_miptree_set_alpha_to_one(struct brw_context *brw,
 777                               struct intel_mipmap_tree *mt,
 778                               int x, int y, int width, int height)
 779 {
 780    uint32_t BR13, CMD;
 781    int pitch, cpp;
 782    drm_intel_bo *aper_array[2];
 783
 784    pitch = mt->pitch;
 785    cpp = mt->cpp;
 786
 787    DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
 788        __func__, mt->bo, pitch, x, y, width, height);
 789
 790    BR13 = br13_for_cpp(cpp) | 0xf0 << 16;
 791    CMD = XY_COLOR_BLT_CMD;
 792    CMD |= XY_BLT_WRITE_ALPHA;
 793
 794    if (mt->tiling != I915_TILING_NONE) {
 795       CMD |= XY_DST_TILED;
 796       pitch /= 4;
 797    }
 798    BR13 |= pitch;
 799
 800    /* do space check before going any further */
 801    aper_array[0] = brw->batch.bo;
 802    aper_array[1] = mt->bo;
 803
 804    if (drm_intel_bufmgr_check_aperture_space(aper_array,
 805                                              ARRAY_SIZE(aper_array)) != 0) {
 806       intel_batchbuffer_flush(brw);
 807    }
 808
 809    unsigned length = brw->gen >= 8 ? 7 : 6;
 810    bool dst_y_tiled = mt->tiling == I915_TILING_Y;
 811
 812    BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, false);
 813    OUT_BATCH(CMD | (length - 2));
 814    OUT_BATCH(BR13);
 815    OUT_BATCH(SET_FIELD(y, BLT_Y) | SET_FIELD(x, BLT_X));
 816    OUT_BATCH(SET_FIELD(y + height, BLT_Y) | SET_FIELD(x + width, BLT_X));
 817    if (brw->gen >= 8) {
 818       OUT_RELOC64(mt->bo,
 819                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 820                   0);
 821    } else {
 822       OUT_RELOC(mt->bo,
 823                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 824                 0);
 825    }
 826    OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
 827    ADVANCE_BATCH_TILED(dst_y_tiled, false);
 828
 829    brw_emit_mi_flush(brw);
 830 }