src/mesa/drivers/dri/i965/intel_blit.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29 #include "main/mtypes.h"
  30 #include "main/context.h"
  31 #include "main/enums.h"
  32 #include "main/colormac.h"
  33 #include "main/fbobject.h"
  34
  35 #include "brw_context.h"
  36 #include "intel_blit.h"
  37 #include "intel_buffers.h"
  38 #include "intel_fbo.h"
  39 #include "intel_reg.h"
  40 #include "intel_regions.h"
  41 #include "intel_batchbuffer.h"
  42 #include "intel_mipmap_tree.h"
  43
  44 #define FILE_DEBUG_FLAG DEBUG_BLIT
  45
  46 static void
  47 intel_miptree_set_alpha_to_one(struct brw_context *brw,
  48                                struct intel_mipmap_tree *mt,
  49                                int x, int y, int width, int height);
  50
  51 static GLuint translate_raster_op(GLenum logicop)
  52 {
  53    switch(logicop) {
  54    case GL_CLEAR: return 0x00;
  55    case GL_AND: return 0x88;
  56    case GL_AND_REVERSE: return 0x44;
  57    case GL_COPY: return 0xCC;
  58    case GL_AND_INVERTED: return 0x22;
  59    case GL_NOOP: return 0xAA;
  60    case GL_XOR: return 0x66;
  61    case GL_OR: return 0xEE;
  62    case GL_NOR: return 0x11;
  63    case GL_EQUIV: return 0x99;
  64    case GL_INVERT: return 0x55;
  65    case GL_OR_REVERSE: return 0xDD;
  66    case GL_COPY_INVERTED: return 0x33;
  67    case GL_OR_INVERTED: return 0xBB;
  68    case GL_NAND: return 0x77;
  69    case GL_SET: return 0xFF;
  70    default: return 0;
  71    }
  72 }
  73
  74 static uint32_t
  75 br13_for_cpp(int cpp)
  76 {
  77    switch (cpp) {
  78    case 4:
  79       return BR13_8888;
  80       break;
  81    case 2:
  82       return BR13_565;
  83       break;
  84    case 1:
  85       return BR13_8;
  86       break;
  87    default:
  88       assert(0);
  89       return 0;
  90    }
  91 }
  92
  93 /**
  94  * Emits the packet for switching the blitter from X to Y tiled or back.
  95  *
  96  * This has to be called in a single BEGIN_BATCH_BLT_TILED() /
  97  * ADVANCE_BATCH_TILED().  This is because BCS_SWCTRL is saved and restored as
  98  * part of the power context, not a render context, and if the batchbuffer was
  99  * to get flushed between setting and blitting, or blitting and restoring, our
 100  * tiling state would leak into other unsuspecting applications (like the X
 101  * server).
 102  */
 103 static void
 104 set_blitter_tiling(struct brw_context *brw,
 105                    bool dst_y_tiled, bool src_y_tiled)
 106 {
 107    struct intel_context *intel = &brw->intel;
 108    assert(intel->gen >= 6);
 109
 110    /* Idle the blitter before we update how tiling is interpreted. */
 111    OUT_BATCH(MI_FLUSH_DW);
 112    OUT_BATCH(0);
 113    OUT_BATCH(0);
 114    OUT_BATCH(0);
 115
 116    OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
 117    OUT_BATCH(BCS_SWCTRL);
 118    OUT_BATCH((BCS_SWCTRL_DST_Y | BCS_SWCTRL_SRC_Y) << 16 |
 119              (dst_y_tiled ? BCS_SWCTRL_DST_Y : 0) |
 120              (src_y_tiled ? BCS_SWCTRL_SRC_Y : 0));
 121 }
 122
 123 #define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled) do {         \
 124       BEGIN_BATCH_BLT(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0));     \
 125       if (dst_y_tiled || src_y_tiled)                                   \
 126          set_blitter_tiling(brw, dst_y_tiled, src_y_tiled);             \
 127    } while (0)
 128
 129 #define ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled) do {              \
 130       if (dst_y_tiled || src_y_tiled)                                   \
 131          set_blitter_tiling(brw, false, false);                         \
 132       ADVANCE_BATCH();                                                  \
 133    } while (0)
 134
 135 /**
 136  * Implements a rectangular block transfer (blit) of pixels between two
 137  * miptrees.
 138  *
 139  * Our blitter can operate on 1, 2, or 4-byte-per-pixel data, with generous,
 140  * but limited, pitches and sizes allowed.
 141  *
 142  * The src/dst coordinates are relative to the given level/slice of the
 143  * miptree.
 144  *
 145  * If @src_flip or @dst_flip is set, then the rectangle within that miptree
 146  * will be inverted (including scanline order) when copying.  This is common
 147  * in GL when copying between window system and user-created
 148  * renderbuffers/textures.
 149  */
 150 bool
 151 intel_miptree_blit(struct brw_context *brw,
 152                    struct intel_mipmap_tree *src_mt,
 153                    int src_level, int src_slice,
 154                    uint32_t src_x, uint32_t src_y, bool src_flip,
 155                    struct intel_mipmap_tree *dst_mt,
 156                    int dst_level, int dst_slice,
 157                    uint32_t dst_x, uint32_t dst_y, bool dst_flip,
 158                    uint32_t width, uint32_t height,
 159                    GLenum logicop)
 160 {
 161    /* No sRGB decode or encode is done by the hardware blitter, which is
 162     * consistent with what we want in the callers (glCopyTexSubImage(),
 163     * glBlitFramebuffer(), texture validation, etc.).
 164     */
 165    gl_format src_format = _mesa_get_srgb_format_linear(src_mt->format);
 166    gl_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format);
 167
 168    /* The blitter doesn't support doing any format conversions.  We do also
 169     * support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into
 170     * the X channel don't matter), and XRGB8888 to ARGB8888 by setting the A
 171     * channel to 1.0 at the end.
 172     */
 173    if (src_format != dst_format &&
 174       ((src_format != MESA_FORMAT_ARGB8888 &&
 175         src_format != MESA_FORMAT_XRGB8888) ||
 176        (dst_format != MESA_FORMAT_ARGB8888 &&
 177         dst_format != MESA_FORMAT_XRGB8888))) {
 178       perf_debug("%s: Can't use hardware blitter from %s to %s, "
 179                  "falling back.\n", __FUNCTION__,
 180                  _mesa_get_format_name(src_format),
 181                  _mesa_get_format_name(dst_format));
 182       return false;
 183    }
 184
 185    /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
 186     * Data Size Limitations):
 187     *
 188     *    The BLT engine is capable of transferring very large quantities of
 189     *    graphics data. Any graphics data read from and written to the
 190     *    destination is permitted to represent a number of pixels that
 191     *    occupies up to 65,536 scan lines and up to 32,768 bytes per scan line
 192     *    at the destination. The maximum number of pixels that may be
 193     *    represented per scan line’s worth of graphics data depends on the
 194     *    color depth.
 195     *
 196     * Furthermore, intelEmitCopyBlit (which is called below) uses a signed
 197     * 16-bit integer to represent buffer pitch, so it can only handle buffer
 198     * pitches < 32k.
 199     *
 200     * As a result of these two limitations, we can only use the blitter to do
 201     * this copy when the region's pitch is less than 32k.
 202     */
 203    if (src_mt->region->pitch > 32768 ||
 204        dst_mt->region->pitch > 32768) {
 205       perf_debug("Falling back due to >32k pitch\n");
 206       return false;
 207    }
 208
 209    /* The blitter has no idea about HiZ or fast color clears, so we need to
 210     * resolve the miptrees before we do anything.
 211     */
 212    intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_slice);
 213    intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_slice);
 214    intel_miptree_resolve_color(brw, src_mt);
 215    intel_miptree_resolve_color(brw, dst_mt);
 216
 217    if (src_flip)
 218       src_y = src_mt->level[src_level].height - src_y - height;
 219
 220    if (dst_flip)
 221       dst_y = dst_mt->level[dst_level].height - dst_y - height;
 222
 223    int src_pitch = src_mt->region->pitch;
 224    if (src_flip != dst_flip)
 225       src_pitch = -src_pitch;
 226
 227    uint32_t src_image_x, src_image_y;
 228    intel_miptree_get_image_offset(src_mt, src_level, src_slice,
 229                                   &src_image_x, &src_image_y);
 230    src_x += src_image_x;
 231    src_y += src_image_y;
 232
 233    uint32_t dst_image_x, dst_image_y;
 234    intel_miptree_get_image_offset(dst_mt, dst_level, dst_slice,
 235                                   &dst_image_x, &dst_image_y);
 236    dst_x += dst_image_x;
 237    dst_y += dst_image_y;
 238
 239    if (!intelEmitCopyBlit(brw,
 240                           src_mt->cpp,
 241                           src_pitch,
 242                           src_mt->region->bo, src_mt->offset,
 243                           src_mt->region->tiling,
 244                           dst_mt->region->pitch,
 245                           dst_mt->region->bo, dst_mt->offset,
 246                           dst_mt->region->tiling,
 247                           src_x, src_y,
 248                           dst_x, dst_y,
 249                           width, height,
 250                           logicop)) {
 251       return false;
 252    }
 253
 254    if (src_mt->format == MESA_FORMAT_XRGB8888 &&
 255        dst_mt->format == MESA_FORMAT_ARGB8888) {
 256       intel_miptree_set_alpha_to_one(brw, dst_mt,
 257                                      dst_x, dst_y,
 258                                      width, height);
 259    }
 260
 261    return true;
 262 }
 263
 264 /* Copy BitBlt
 265  */
 266 bool
 267 intelEmitCopyBlit(struct brw_context *brw,
 268                   GLuint cpp,
 269                   GLshort src_pitch,
 270                   drm_intel_bo *src_buffer,
 271                   GLuint src_offset,
 272                   uint32_t src_tiling,
 273                   GLshort dst_pitch,
 274                   drm_intel_bo *dst_buffer,
 275                   GLuint dst_offset,
 276                   uint32_t dst_tiling,
 277                   GLshort src_x, GLshort src_y,
 278                   GLshort dst_x, GLshort dst_y,
 279                   GLshort w, GLshort h,
 280                   GLenum logic_op)
 281 {
 282    struct intel_context *intel = &brw->intel;
 283    GLuint CMD, BR13, pass = 0;
 284    int dst_y2 = dst_y + h;
 285    int dst_x2 = dst_x + w;
 286    drm_intel_bo *aper_array[3];
 287    bool dst_y_tiled = dst_tiling == I915_TILING_Y;
 288    bool src_y_tiled = src_tiling == I915_TILING_Y;
 289    BATCH_LOCALS;
 290
 291    if (dst_tiling != I915_TILING_NONE) {
 292       if (dst_offset & 4095)
 293          return false;
 294    }
 295    if (src_tiling != I915_TILING_NONE) {
 296       if (src_offset & 4095)
 297          return false;
 298    }
 299    if ((dst_y_tiled || src_y_tiled) && intel->gen < 6)
 300       return false;
 301
 302    /* do space check before going any further */
 303    do {
 304        aper_array[0] = brw->batch.bo;
 305        aper_array[1] = dst_buffer;
 306        aper_array[2] = src_buffer;
 307
 308        if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
 309            intel_batchbuffer_flush(brw);
 310            pass++;
 311        } else
 312            break;
 313    } while (pass < 2);
 314
 315    if (pass >= 2)
 316       return false;
 317
 318    intel_batchbuffer_require_space(brw, 8 * 4, true);
 319    DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
 320        __FUNCTION__,
 321        src_buffer, src_pitch, src_offset, src_x, src_y,
 322        dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
 323
 324    /* Blit pitch must be dword-aligned.  Otherwise, the hardware appears to drop
 325     * the low bits.
 326     */
 327    if (src_pitch % 4 != 0 || dst_pitch % 4 != 0)
 328       return false;
 329
 330    /* For big formats (such as floating point), do the copy using 16 or 32bpp
 331     * and multiply the coordinates.
 332     */
 333    if (cpp > 4) {
 334       if (cpp % 4 == 2) {
 335          dst_x *= cpp / 2;
 336          dst_x2 *= cpp / 2;
 337          src_x *= cpp / 2;
 338          cpp = 2;
 339       } else {
 340          assert(cpp % 4 == 0);
 341          dst_x *= cpp / 4;
 342          dst_x2 *= cpp / 4;
 343          src_x *= cpp / 4;
 344          cpp = 4;
 345       }
 346    }
 347
 348    BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16;
 349
 350    switch (cpp) {
 351    case 1:
 352    case 2:
 353       CMD = XY_SRC_COPY_BLT_CMD;
 354       break;
 355    case 4:
 356       CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 357       break;
 358    default:
 359       return false;
 360    }
 361
 362    if (dst_tiling != I915_TILING_NONE) {
 363       CMD |= XY_DST_TILED;
 364       dst_pitch /= 4;
 365    }
 366    if (src_tiling != I915_TILING_NONE) {
 367       CMD |= XY_SRC_TILED;
 368       src_pitch /= 4;
 369    }
 370
 371    if (dst_y2 <= dst_y || dst_x2 <= dst_x) {
 372       return true;
 373    }
 374
 375    assert(dst_x < dst_x2);
 376    assert(dst_y < dst_y2);
 377
 378    BEGIN_BATCH_BLT_TILED(8, dst_y_tiled, src_y_tiled);
 379
 380    OUT_BATCH(CMD | (8 - 2));
 381    OUT_BATCH(BR13 | (uint16_t)dst_pitch);
 382    OUT_BATCH((dst_y << 16) | dst_x);
 383    OUT_BATCH((dst_y2 << 16) | dst_x2);
 384    OUT_RELOC_FENCED(dst_buffer,
 385                     I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 386                     dst_offset);
 387    OUT_BATCH((src_y << 16) | src_x);
 388    OUT_BATCH((uint16_t)src_pitch);
 389    OUT_RELOC_FENCED(src_buffer,
 390                     I915_GEM_DOMAIN_RENDER, 0,
 391                     src_offset);
 392
 393    ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled);
 394
 395    intel_batchbuffer_emit_mi_flush(brw);
 396
 397    return true;
 398 }
 399
 400 bool
 401 intelEmitImmediateColorExpandBlit(struct brw_context *brw,
 402                                   GLuint cpp,
 403                                   GLubyte *src_bits, GLuint src_size,
 404                                   GLuint fg_color,
 405                                   GLshort dst_pitch,
 406                                   drm_intel_bo *dst_buffer,
 407                                   GLuint dst_offset,
 408                                   uint32_t dst_tiling,
 409                                   GLshort x, GLshort y,
 410                                   GLshort w, GLshort h,
 411                                   GLenum logic_op)
 412 {
 413    int dwords = ALIGN(src_size, 8) / 4;
 414    uint32_t opcode, br13, blit_cmd;
 415
 416    if (dst_tiling != I915_TILING_NONE) {
 417       if (dst_offset & 4095)
 418          return false;
 419       if (dst_tiling == I915_TILING_Y)
 420          return false;
 421    }
 422
 423    assert( logic_op - GL_CLEAR >= 0 );
 424    assert( logic_op - GL_CLEAR < 0x10 );
 425    assert(dst_pitch > 0);
 426
 427    if (w < 0 || h < 0)
 428       return true;
 429
 430    DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
 431        __FUNCTION__,
 432        dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
 433
 434    intel_batchbuffer_require_space(brw, (8 * 4) + (3 * 4) + dwords * 4, true);
 435
 436    opcode = XY_SETUP_BLT_CMD;
 437    if (cpp == 4)
 438       opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 439    if (dst_tiling != I915_TILING_NONE) {
 440       opcode |= XY_DST_TILED;
 441       dst_pitch /= 4;
 442    }
 443
 444    br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
 445    br13 |= br13_for_cpp(cpp);
 446
 447    blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
 448    if (dst_tiling != I915_TILING_NONE)
 449       blit_cmd |= XY_DST_TILED;
 450
 451    BEGIN_BATCH_BLT(8 + 3);
 452    OUT_BATCH(opcode | (8 - 2));
 453    OUT_BATCH(br13);
 454    OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
 455    OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
 456    OUT_RELOC_FENCED(dst_buffer,
 457                     I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 458                     dst_offset);
 459    OUT_BATCH(0); /* bg */
 460    OUT_BATCH(fg_color); /* fg */
 461    OUT_BATCH(0); /* pattern base addr */
 462
 463    OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
 464    OUT_BATCH((y << 16) | x);
 465    OUT_BATCH(((y + h) << 16) | (x + w));
 466    ADVANCE_BATCH();
 467
 468    intel_batchbuffer_data(brw, src_bits, dwords * 4, true);
 469
 470    intel_batchbuffer_emit_mi_flush(brw);
 471
 472    return true;
 473 }
 474
 475 /* We don't have a memmove-type blit like some other hardware, so we'll do a
 476  * rectangular blit covering a large space, then emit 1-scanline blit at the
 477  * end to cover the last if we need.
 478  */
 479 void
 480 intel_emit_linear_blit(struct brw_context *brw,
 481                        drm_intel_bo *dst_bo,
 482                        unsigned int dst_offset,
 483                        drm_intel_bo *src_bo,
 484                        unsigned int src_offset,
 485                        unsigned int size)
 486 {
 487    struct intel_context *intel = &brw->intel;
 488    struct gl_context *ctx = &intel->ctx;
 489    GLuint pitch, height;
 490    bool ok;
 491
 492    /* The pitch given to the GPU must be DWORD aligned, and
 493     * we want width to match pitch. Max width is (1 << 15 - 1),
 494     * rounding that down to the nearest DWORD is 1 << 15 - 4
 495     */
 496    pitch = ROUND_DOWN_TO(MIN2(size, (1 << 15) - 1), 4);
 497    height = (pitch == 0) ? 1 : size / pitch;
 498    ok = intelEmitCopyBlit(brw, 1,
 499                           pitch, src_bo, src_offset, I915_TILING_NONE,
 500                           pitch, dst_bo, dst_offset, I915_TILING_NONE,
 501                           0, 0, /* src x/y */
 502                           0, 0, /* dst x/y */
 503                           pitch, height, /* w, h */
 504                           GL_COPY);
 505    if (!ok)
 506       _mesa_problem(ctx, "Failed to linear blit %dx%d\n", pitch, height);
 507
 508    src_offset += pitch * height;
 509    dst_offset += pitch * height;
 510    size -= pitch * height;
 511    assert (size < (1 << 15));
 512    pitch = ALIGN(size, 4);
 513    if (size != 0) {
 514       ok = intelEmitCopyBlit(brw, 1,
 515                              pitch, src_bo, src_offset, I915_TILING_NONE,
 516                              pitch, dst_bo, dst_offset, I915_TILING_NONE,
 517                              0, 0, /* src x/y */
 518                              0, 0, /* dst x/y */
 519                              size, 1, /* w, h */
 520                              GL_COPY);
 521       if (!ok)
 522          _mesa_problem(ctx, "Failed to linear blit %dx%d\n", size, 1);
 523    }
 524 }
 525
 526 /**
 527  * Used to initialize the alpha value of an ARGB8888 miptree after copying
 528  * into it from an XRGB8888 source.
 529  *
 530  * This is very common with glCopyTexImage2D().  Note that the coordinates are
 531  * relative to the start of the miptree, not relative to a slice within the
 532  * miptree.
 533  */
 534 static void
 535 intel_miptree_set_alpha_to_one(struct brw_context *brw,
 536                               struct intel_mipmap_tree *mt,
 537                               int x, int y, int width, int height)
 538 {
 539    struct intel_region *region = mt->region;
 540    uint32_t BR13, CMD;
 541    int pitch, cpp;
 542    drm_intel_bo *aper_array[2];
 543    BATCH_LOCALS;
 544
 545    pitch = region->pitch;
 546    cpp = region->cpp;
 547
 548    DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
 549        __FUNCTION__, region->bo, pitch, x, y, width, height);
 550
 551    BR13 = br13_for_cpp(cpp) | 0xf0 << 16;
 552    CMD = XY_COLOR_BLT_CMD;
 553    CMD |= XY_BLT_WRITE_ALPHA;
 554
 555    if (region->tiling != I915_TILING_NONE) {
 556       CMD |= XY_DST_TILED;
 557       pitch /= 4;
 558    }
 559    BR13 |= pitch;
 560
 561    /* do space check before going any further */
 562    aper_array[0] = brw->batch.bo;
 563    aper_array[1] = region->bo;
 564
 565    if (drm_intel_bufmgr_check_aperture_space(aper_array,
 566                                              ARRAY_SIZE(aper_array)) != 0) {
 567       intel_batchbuffer_flush(brw);
 568    }
 569
 570    bool dst_y_tiled = region->tiling == I915_TILING_Y;
 571
 572    BEGIN_BATCH_BLT_TILED(6, dst_y_tiled, false);
 573    OUT_BATCH(CMD | (6 - 2));
 574    OUT_BATCH(BR13);
 575    OUT_BATCH((y << 16) | x);
 576    OUT_BATCH(((y + height) << 16) | (x + width));
 577    OUT_RELOC_FENCED(region->bo,
 578                     I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 579                     0);
 580    OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
 581    ADVANCE_BATCH_TILED(dst_y_tiled, false);
 582
 583    intel_batchbuffer_emit_mi_flush(brw);
 584 }