src/mesa/drivers/dri/i965/intel_blit.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 VMware, Inc.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29 #include "main/mtypes.h"
  30 #include "main/context.h"
  31 #include "main/enums.h"
  32 #include "main/colormac.h"
  33 #include "main/fbobject.h"
  34
  35 #include "brw_context.h"
  36 #include "brw_defines.h"
  37 #include "intel_blit.h"
  38 #include "intel_buffers.h"
  39 #include "intel_fbo.h"
  40 #include "intel_reg.h"
  41 #include "intel_regions.h"
  42 #include "intel_batchbuffer.h"
  43 #include "intel_mipmap_tree.h"
  44
  45 #define FILE_DEBUG_FLAG DEBUG_BLIT
  46
  47 static void
  48 intel_miptree_set_alpha_to_one(struct brw_context *brw,
  49                                struct intel_mipmap_tree *mt,
  50                                int x, int y, int width, int height);
  51
  52 static GLuint translate_raster_op(GLenum logicop)
  53 {
  54    switch(logicop) {
  55    case GL_CLEAR: return 0x00;
  56    case GL_AND: return 0x88;
  57    case GL_AND_REVERSE: return 0x44;
  58    case GL_COPY: return 0xCC;
  59    case GL_AND_INVERTED: return 0x22;
  60    case GL_NOOP: return 0xAA;
  61    case GL_XOR: return 0x66;
  62    case GL_OR: return 0xEE;
  63    case GL_NOR: return 0x11;
  64    case GL_EQUIV: return 0x99;
  65    case GL_INVERT: return 0x55;
  66    case GL_OR_REVERSE: return 0xDD;
  67    case GL_COPY_INVERTED: return 0x33;
  68    case GL_OR_INVERTED: return 0xBB;
  69    case GL_NAND: return 0x77;
  70    case GL_SET: return 0xFF;
  71    default: return 0;
  72    }
  73 }
  74
  75 static uint32_t
  76 br13_for_cpp(int cpp)
  77 {
  78    switch (cpp) {
  79    case 4:
  80       return BR13_8888;
  81       break;
  82    case 2:
  83       return BR13_565;
  84       break;
  85    case 1:
  86       return BR13_8;
  87       break;
  88    default:
  89       assert(0);
  90       return 0;
  91    }
  92 }
  93
  94 /**
  95  * Emits the packet for switching the blitter from X to Y tiled or back.
  96  *
  97  * This has to be called in a single BEGIN_BATCH_BLT_TILED() /
  98  * ADVANCE_BATCH_TILED().  This is because BCS_SWCTRL is saved and restored as
  99  * part of the power context, not a render context, and if the batchbuffer was
 100  * to get flushed between setting and blitting, or blitting and restoring, our
 101  * tiling state would leak into other unsuspecting applications (like the X
 102  * server).
 103  */
 104 static void
 105 set_blitter_tiling(struct brw_context *brw,
 106                    bool dst_y_tiled, bool src_y_tiled)
 107 {
 108    assert(brw->gen >= 6);
 109
 110    /* Idle the blitter before we update how tiling is interpreted. */
 111    OUT_BATCH(MI_FLUSH_DW);
 112    OUT_BATCH(0);
 113    OUT_BATCH(0);
 114    OUT_BATCH(0);
 115
 116    OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
 117    OUT_BATCH(BCS_SWCTRL);
 118    OUT_BATCH((BCS_SWCTRL_DST_Y | BCS_SWCTRL_SRC_Y) << 16 |
 119              (dst_y_tiled ? BCS_SWCTRL_DST_Y : 0) |
 120              (src_y_tiled ? BCS_SWCTRL_SRC_Y : 0));
 121 }
 122
 123 #define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled) do {         \
 124       BEGIN_BATCH_BLT(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0));     \
 125       if (dst_y_tiled || src_y_tiled)                                   \
 126          set_blitter_tiling(brw, dst_y_tiled, src_y_tiled);             \
 127    } while (0)
 128
 129 #define ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled) do {              \
 130       if (dst_y_tiled || src_y_tiled)                                   \
 131          set_blitter_tiling(brw, false, false);                         \
 132       ADVANCE_BATCH();                                                  \
 133    } while (0)
 134
 135 /**
 136  * Implements a rectangular block transfer (blit) of pixels between two
 137  * miptrees.
 138  *
 139  * Our blitter can operate on 1, 2, or 4-byte-per-pixel data, with generous,
 140  * but limited, pitches and sizes allowed.
 141  *
 142  * The src/dst coordinates are relative to the given level/slice of the
 143  * miptree.
 144  *
 145  * If @src_flip or @dst_flip is set, then the rectangle within that miptree
 146  * will be inverted (including scanline order) when copying.  This is common
 147  * in GL when copying between window system and user-created
 148  * renderbuffers/textures.
 149  */
 150 bool
 151 intel_miptree_blit(struct brw_context *brw,
 152                    struct intel_mipmap_tree *src_mt,
 153                    int src_level, int src_slice,
 154                    uint32_t src_x, uint32_t src_y, bool src_flip,
 155                    struct intel_mipmap_tree *dst_mt,
 156                    int dst_level, int dst_slice,
 157                    uint32_t dst_x, uint32_t dst_y, bool dst_flip,
 158                    uint32_t width, uint32_t height,
 159                    GLenum logicop)
 160 {
 161    /* No sRGB decode or encode is done by the hardware blitter, which is
 162     * consistent with what we want in the callers (glCopyTexSubImage(),
 163     * glBlitFramebuffer(), texture validation, etc.).
 164     */
 165    mesa_format src_format = _mesa_get_srgb_format_linear(src_mt->format);
 166    mesa_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format);
 167
 168    /* The blitter doesn't support doing any format conversions.  We do also
 169     * support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into
 170     * the X channel don't matter), and XRGB8888 to ARGB8888 by setting the A
 171     * channel to 1.0 at the end.
 172     */
 173    if (src_format != dst_format &&
 174       ((src_format != MESA_FORMAT_B8G8R8A8_UNORM &&
 175         src_format != MESA_FORMAT_B8G8R8X8_UNORM) ||
 176        (dst_format != MESA_FORMAT_B8G8R8A8_UNORM &&
 177         dst_format != MESA_FORMAT_B8G8R8X8_UNORM))) {
 178       perf_debug("%s: Can't use hardware blitter from %s to %s, "
 179                  "falling back.\n", __FUNCTION__,
 180                  _mesa_get_format_name(src_format),
 181                  _mesa_get_format_name(dst_format));
 182       return false;
 183    }
 184
 185    /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
 186     * Data Size Limitations):
 187     *
 188     *    The BLT engine is capable of transferring very large quantities of
 189     *    graphics data. Any graphics data read from and written to the
 190     *    destination is permitted to represent a number of pixels that
 191     *    occupies up to 65,536 scan lines and up to 32,768 bytes per scan line
 192     *    at the destination. The maximum number of pixels that may be
 193     *    represented per scan line’s worth of graphics data depends on the
 194     *    color depth.
 195     *
 196     * Furthermore, intelEmitCopyBlit (which is called below) uses a signed
 197     * 16-bit integer to represent buffer pitch, so it can only handle buffer
 198     * pitches < 32k.
 199     *
 200     * As a result of these two limitations, we can only use the blitter to do
 201     * this copy when the region's pitch is less than 32k.
 202     */
 203    if (src_mt->region->pitch > 32768 ||
 204        dst_mt->region->pitch > 32768) {
 205       perf_debug("Falling back due to >32k pitch\n");
 206       return false;
 207    }
 208
 209    /* The blitter has no idea about HiZ or fast color clears, so we need to
 210     * resolve the miptrees before we do anything.
 211     */
 212    intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_slice);
 213    intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_slice);
 214    intel_miptree_resolve_color(brw, src_mt);
 215    intel_miptree_resolve_color(brw, dst_mt);
 216
 217    if (src_flip)
 218       src_y = minify(src_mt->physical_height0, src_level) - src_y - height;
 219
 220    if (dst_flip)
 221       dst_y = minify(dst_mt->physical_height0, dst_level) - dst_y - height;
 222
 223    int src_pitch = src_mt->region->pitch;
 224    if (src_flip != dst_flip)
 225       src_pitch = -src_pitch;
 226
 227    uint32_t src_image_x, src_image_y;
 228    intel_miptree_get_image_offset(src_mt, src_level, src_slice,
 229                                   &src_image_x, &src_image_y);
 230    src_x += src_image_x;
 231    src_y += src_image_y;
 232
 233    /* The blitter interprets the 16-bit src x/y as a signed 16-bit value,
 234     * where negative values are invalid.  The values we're working with are
 235     * unsigned, so make sure we don't overflow.
 236     */
 237    if (src_x >= 32768 || src_y >= 32768) {
 238       perf_debug("Falling back due to >=32k src offset (%d, %d)\n",
 239                  src_x, src_y);
 240       return false;
 241    }
 242
 243    uint32_t dst_image_x, dst_image_y;
 244    intel_miptree_get_image_offset(dst_mt, dst_level, dst_slice,
 245                                   &dst_image_x, &dst_image_y);
 246    dst_x += dst_image_x;
 247    dst_y += dst_image_y;
 248
 249    /* The blitter interprets the 16-bit destination x/y as a signed 16-bit
 250     * value.  The values we're working with are unsigned, so make sure we
 251     * don't overflow.
 252     */
 253    if (dst_x >= 32768 || dst_y >= 32768) {
 254       perf_debug("Falling back due to >=32k dst offset (%d, %d)\n",
 255                  dst_x, dst_y);
 256       return false;
 257    }
 258
 259    if (!intelEmitCopyBlit(brw,
 260                           src_mt->cpp,
 261                           src_pitch,
 262                           src_mt->region->bo, src_mt->offset,
 263                           src_mt->region->tiling,
 264                           dst_mt->region->pitch,
 265                           dst_mt->region->bo, dst_mt->offset,
 266                           dst_mt->region->tiling,
 267                           src_x, src_y,
 268                           dst_x, dst_y,
 269                           width, height,
 270                           logicop)) {
 271       return false;
 272    }
 273
 274    if (src_mt->format == MESA_FORMAT_B8G8R8X8_UNORM &&
 275        dst_mt->format == MESA_FORMAT_B8G8R8A8_UNORM) {
 276       intel_miptree_set_alpha_to_one(brw, dst_mt,
 277                                      dst_x, dst_y,
 278                                      width, height);
 279    }
 280
 281    return true;
 282 }
 283
 284 /* Copy BitBlt
 285  */
 286 bool
 287 intelEmitCopyBlit(struct brw_context *brw,
 288                   GLuint cpp,
 289                   GLshort src_pitch,
 290                   drm_intel_bo *src_buffer,
 291                   GLuint src_offset,
 292                   uint32_t src_tiling,
 293                   GLshort dst_pitch,
 294                   drm_intel_bo *dst_buffer,
 295                   GLuint dst_offset,
 296                   uint32_t dst_tiling,
 297                   GLshort src_x, GLshort src_y,
 298                   GLshort dst_x, GLshort dst_y,
 299                   GLshort w, GLshort h,
 300                   GLenum logic_op)
 301 {
 302    GLuint CMD, BR13, pass = 0;
 303    int dst_y2 = dst_y + h;
 304    int dst_x2 = dst_x + w;
 305    drm_intel_bo *aper_array[3];
 306    bool dst_y_tiled = dst_tiling == I915_TILING_Y;
 307    bool src_y_tiled = src_tiling == I915_TILING_Y;
 308
 309    if (dst_tiling != I915_TILING_NONE) {
 310       if (dst_offset & 4095)
 311          return false;
 312    }
 313    if (src_tiling != I915_TILING_NONE) {
 314       if (src_offset & 4095)
 315          return false;
 316    }
 317    if ((dst_y_tiled || src_y_tiled) && brw->gen < 6)
 318       return false;
 319
 320    /* do space check before going any further */
 321    do {
 322        aper_array[0] = brw->batch.bo;
 323        aper_array[1] = dst_buffer;
 324        aper_array[2] = src_buffer;
 325
 326        if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
 327            intel_batchbuffer_flush(brw);
 328            pass++;
 329        } else
 330            break;
 331    } while (pass < 2);
 332
 333    if (pass >= 2)
 334       return false;
 335
 336    intel_batchbuffer_require_space(brw, 8 * 4, BLT_RING);
 337    DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
 338        __FUNCTION__,
 339        src_buffer, src_pitch, src_offset, src_x, src_y,
 340        dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
 341
 342    /* Blit pitch must be dword-aligned.  Otherwise, the hardware appears to drop
 343     * the low bits.
 344     */
 345    if (src_pitch % 4 != 0 || dst_pitch % 4 != 0)
 346       return false;
 347
 348    /* For big formats (such as floating point), do the copy using 16 or 32bpp
 349     * and multiply the coordinates.
 350     */
 351    if (cpp > 4) {
 352       if (cpp % 4 == 2) {
 353          dst_x *= cpp / 2;
 354          dst_x2 *= cpp / 2;
 355          src_x *= cpp / 2;
 356          cpp = 2;
 357       } else {
 358          assert(cpp % 4 == 0);
 359          dst_x *= cpp / 4;
 360          dst_x2 *= cpp / 4;
 361          src_x *= cpp / 4;
 362          cpp = 4;
 363       }
 364    }
 365
 366    BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16;
 367
 368    switch (cpp) {
 369    case 1:
 370    case 2:
 371       CMD = XY_SRC_COPY_BLT_CMD;
 372       break;
 373    case 4:
 374       CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 375       break;
 376    default:
 377       return false;
 378    }
 379
 380    if (dst_tiling != I915_TILING_NONE) {
 381       CMD |= XY_DST_TILED;
 382       dst_pitch /= 4;
 383    }
 384    if (src_tiling != I915_TILING_NONE) {
 385       CMD |= XY_SRC_TILED;
 386       src_pitch /= 4;
 387    }
 388
 389    if (dst_y2 <= dst_y || dst_x2 <= dst_x) {
 390       return true;
 391    }
 392
 393    assert(dst_x < dst_x2);
 394    assert(dst_y < dst_y2);
 395    assert(src_offset + (src_y + h - 1) * abs(src_pitch) +
 396           (w * cpp) <= src_buffer->size);
 397    assert(dst_offset + (dst_y + h - 1) * abs(dst_pitch) +
 398           (w * cpp) <= dst_buffer->size);
 399
 400    unsigned length = brw->gen >= 8 ? 10 : 8;
 401
 402    BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, src_y_tiled);
 403    OUT_BATCH(CMD | (length - 2));
 404    OUT_BATCH(BR13 | (uint16_t)dst_pitch);
 405    OUT_BATCH(SET_FIELD(dst_y, BLT_Y) | SET_FIELD(dst_x, BLT_X));
 406    OUT_BATCH(SET_FIELD(dst_y2, BLT_Y) | SET_FIELD(dst_x2, BLT_X));
 407    if (brw->gen >= 8) {
 408       OUT_RELOC64(dst_buffer,
 409                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 410                   dst_offset);
 411    } else {
 412       OUT_RELOC(dst_buffer,
 413                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 414                 dst_offset);
 415    }
 416    OUT_BATCH(SET_FIELD(src_y, BLT_Y) | SET_FIELD(src_x, BLT_X));
 417    OUT_BATCH((uint16_t)src_pitch);
 418    if (brw->gen >= 8) {
 419       OUT_RELOC64(src_buffer,
 420                   I915_GEM_DOMAIN_RENDER, 0,
 421                   src_offset);
 422    } else {
 423       OUT_RELOC(src_buffer,
 424                 I915_GEM_DOMAIN_RENDER, 0,
 425                 src_offset);
 426    }
 427
 428    ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled);
 429
 430    intel_batchbuffer_emit_mi_flush(brw);
 431
 432    return true;
 433 }
 434
 435 bool
 436 intelEmitImmediateColorExpandBlit(struct brw_context *brw,
 437                                   GLuint cpp,
 438                                   GLubyte *src_bits, GLuint src_size,
 439                                   GLuint fg_color,
 440                                   GLshort dst_pitch,
 441                                   drm_intel_bo *dst_buffer,
 442                                   GLuint dst_offset,
 443                                   uint32_t dst_tiling,
 444                                   GLshort x, GLshort y,
 445                                   GLshort w, GLshort h,
 446                                   GLenum logic_op)
 447 {
 448    int dwords = ALIGN(src_size, 8) / 4;
 449    uint32_t opcode, br13, blit_cmd;
 450
 451    if (dst_tiling != I915_TILING_NONE) {
 452       if (dst_offset & 4095)
 453          return false;
 454       if (dst_tiling == I915_TILING_Y)
 455          return false;
 456    }
 457
 458    assert((logic_op >= GL_CLEAR) && (logic_op <= (GL_CLEAR + 0x0f)));
 459    assert(dst_pitch > 0);
 460
 461    if (w < 0 || h < 0)
 462       return true;
 463
 464    DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
 465        __FUNCTION__,
 466        dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
 467
 468    intel_batchbuffer_require_space(brw, (8 * 4) + (3 * 4) + dwords * 4, BLT_RING);
 469
 470    opcode = XY_SETUP_BLT_CMD;
 471    if (cpp == 4)
 472       opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
 473    if (dst_tiling != I915_TILING_NONE) {
 474       opcode |= XY_DST_TILED;
 475       dst_pitch /= 4;
 476    }
 477
 478    br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
 479    br13 |= br13_for_cpp(cpp);
 480
 481    blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
 482    if (dst_tiling != I915_TILING_NONE)
 483       blit_cmd |= XY_DST_TILED;
 484
 485    unsigned xy_setup_blt_length = brw->gen >= 8 ? 10 : 8;
 486
 487    BEGIN_BATCH_BLT(xy_setup_blt_length + 3);
 488    OUT_BATCH(opcode | (xy_setup_blt_length - 2));
 489    OUT_BATCH(br13);
 490    OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
 491    OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
 492    if (brw->gen >= 8) {
 493       OUT_RELOC64(dst_buffer,
 494                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 495                   dst_offset);
 496    } else {
 497       OUT_RELOC(dst_buffer,
 498                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 499                 dst_offset);
 500    }
 501    OUT_BATCH(0); /* bg */
 502    OUT_BATCH(fg_color); /* fg */
 503    OUT_BATCH(0); /* pattern base addr */
 504    if (brw->gen >= 8)
 505       OUT_BATCH(0);
 506
 507    OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
 508    OUT_BATCH(SET_FIELD(y, BLT_Y) | SET_FIELD(x, BLT_X));
 509    OUT_BATCH(SET_FIELD(y + h, BLT_Y) | SET_FIELD(x + w, BLT_X));
 510    ADVANCE_BATCH();
 511
 512    intel_batchbuffer_data(brw, src_bits, dwords * 4, BLT_RING);
 513
 514    intel_batchbuffer_emit_mi_flush(brw);
 515
 516    return true;
 517 }
 518
 519 /* We don't have a memmove-type blit like some other hardware, so we'll do a
 520  * rectangular blit covering a large space, then emit 1-scanline blit at the
 521  * end to cover the last if we need.
 522  */
 523 void
 524 intel_emit_linear_blit(struct brw_context *brw,
 525                        drm_intel_bo *dst_bo,
 526                        unsigned int dst_offset,
 527                        drm_intel_bo *src_bo,
 528                        unsigned int src_offset,
 529                        unsigned int size)
 530 {
 531    struct gl_context *ctx = &brw->ctx;
 532    GLuint pitch, height;
 533    bool ok;
 534
 535    /* The pitch given to the GPU must be DWORD aligned, and
 536     * we want width to match pitch. Max width is (1 << 15 - 1),
 537     * rounding that down to the nearest DWORD is 1 << 15 - 4
 538     */
 539    pitch = ROUND_DOWN_TO(MIN2(size, (1 << 15) - 1), 4);
 540    height = (pitch == 0) ? 1 : size / pitch;
 541    ok = intelEmitCopyBlit(brw, 1,
 542                           pitch, src_bo, src_offset, I915_TILING_NONE,
 543                           pitch, dst_bo, dst_offset, I915_TILING_NONE,
 544                           0, 0, /* src x/y */
 545                           0, 0, /* dst x/y */
 546                           pitch, height, /* w, h */
 547                           GL_COPY);
 548    if (!ok)
 549       _mesa_problem(ctx, "Failed to linear blit %dx%d\n", pitch, height);
 550
 551    src_offset += pitch * height;
 552    dst_offset += pitch * height;
 553    size -= pitch * height;
 554    assert (size < (1 << 15));
 555    pitch = ALIGN(size, 4);
 556    if (size != 0) {
 557       ok = intelEmitCopyBlit(brw, 1,
 558                              pitch, src_bo, src_offset, I915_TILING_NONE,
 559                              pitch, dst_bo, dst_offset, I915_TILING_NONE,
 560                              0, 0, /* src x/y */
 561                              0, 0, /* dst x/y */
 562                              size, 1, /* w, h */
 563                              GL_COPY);
 564       if (!ok)
 565          _mesa_problem(ctx, "Failed to linear blit %dx%d\n", size, 1);
 566    }
 567 }
 568
 569 /**
 570  * Used to initialize the alpha value of an ARGB8888 miptree after copying
 571  * into it from an XRGB8888 source.
 572  *
 573  * This is very common with glCopyTexImage2D().  Note that the coordinates are
 574  * relative to the start of the miptree, not relative to a slice within the
 575  * miptree.
 576  */
 577 static void
 578 intel_miptree_set_alpha_to_one(struct brw_context *brw,
 579                               struct intel_mipmap_tree *mt,
 580                               int x, int y, int width, int height)
 581 {
 582    struct intel_region *region = mt->region;
 583    uint32_t BR13, CMD;
 584    int pitch, cpp;
 585    drm_intel_bo *aper_array[2];
 586
 587    pitch = region->pitch;
 588    cpp = region->cpp;
 589
 590    DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
 591        __FUNCTION__, region->bo, pitch, x, y, width, height);
 592
 593    BR13 = br13_for_cpp(cpp) | 0xf0 << 16;
 594    CMD = XY_COLOR_BLT_CMD;
 595    CMD |= XY_BLT_WRITE_ALPHA;
 596
 597    if (region->tiling != I915_TILING_NONE) {
 598       CMD |= XY_DST_TILED;
 599       pitch /= 4;
 600    }
 601    BR13 |= pitch;
 602
 603    /* do space check before going any further */
 604    aper_array[0] = brw->batch.bo;
 605    aper_array[1] = region->bo;
 606
 607    if (drm_intel_bufmgr_check_aperture_space(aper_array,
 608                                              ARRAY_SIZE(aper_array)) != 0) {
 609       intel_batchbuffer_flush(brw);
 610    }
 611
 612    unsigned length = brw->gen >= 8 ? 7 : 6;
 613    bool dst_y_tiled = region->tiling == I915_TILING_Y;
 614
 615    BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, false);
 616    OUT_BATCH(CMD | (length - 2));
 617    OUT_BATCH(BR13);
 618    OUT_BATCH(SET_FIELD(y, BLT_Y) | SET_FIELD(x, BLT_X));
 619    OUT_BATCH(SET_FIELD(y + height, BLT_Y) | SET_FIELD(x + width, BLT_X));
 620    if (brw->gen >= 8) {
 621       OUT_RELOC64(region->bo,
 622                   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 623                   0);
 624    } else {
 625       OUT_RELOC(region->bo,
 626                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 627                 0);
 628    }
 629    OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
 630    ADVANCE_BATCH_TILED(dst_y_tiled, false);
 631
 632    intel_batchbuffer_emit_mi_flush(brw);
 633 }