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i965: Make intelEmitCopyBlit not truncate large strides.
[mesa.git] / src / mesa / drivers / dri / i965 / intel_blit.c
1 /*
2 * Copyright 2003 VMware, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "main/mtypes.h"
27 #include "main/blit.h"
28 #include "main/context.h"
29 #include "main/enums.h"
30 #include "main/fbobject.h"
31
32 #include "brw_context.h"
33 #include "brw_defines.h"
34 #include "intel_blit.h"
35 #include "intel_buffers.h"
36 #include "intel_fbo.h"
37 #include "intel_batchbuffer.h"
38 #include "intel_mipmap_tree.h"
39
40 #define FILE_DEBUG_FLAG DEBUG_BLIT
41
42 #define SET_TILING_XY_FAST_COPY_BLT(tiling, tr_mode, type) \
43 ({ \
44 switch (tiling) { \
45 case I915_TILING_X: \
46 CMD |= type ## _TILED_X; \
47 break; \
48 case I915_TILING_Y: \
49 if (tr_mode == INTEL_MIPTREE_TRMODE_YS) \
50 CMD |= type ## _TILED_64K; \
51 else \
52 CMD |= type ## _TILED_Y; \
53 break; \
54 default: \
55 unreachable("not reached"); \
56 } \
57 })
58
59 static void
60 intel_miptree_set_alpha_to_one(struct brw_context *brw,
61 struct intel_mipmap_tree *mt,
62 int x, int y, int width, int height);
63
64 static GLuint translate_raster_op(GLenum logicop)
65 {
66 switch(logicop) {
67 case GL_CLEAR: return 0x00;
68 case GL_AND: return 0x88;
69 case GL_AND_REVERSE: return 0x44;
70 case GL_COPY: return 0xCC;
71 case GL_AND_INVERTED: return 0x22;
72 case GL_NOOP: return 0xAA;
73 case GL_XOR: return 0x66;
74 case GL_OR: return 0xEE;
75 case GL_NOR: return 0x11;
76 case GL_EQUIV: return 0x99;
77 case GL_INVERT: return 0x55;
78 case GL_OR_REVERSE: return 0xDD;
79 case GL_COPY_INVERTED: return 0x33;
80 case GL_OR_INVERTED: return 0xBB;
81 case GL_NAND: return 0x77;
82 case GL_SET: return 0xFF;
83 default: return 0;
84 }
85 }
86
87 static uint32_t
88 br13_for_cpp(int cpp)
89 {
90 switch (cpp) {
91 case 16:
92 return BR13_32323232;
93 case 8:
94 return BR13_16161616;
95 case 4:
96 return BR13_8888;
97 case 2:
98 return BR13_565;
99 case 1:
100 return BR13_8;
101 default:
102 unreachable("not reached");
103 }
104 }
105
106 /**
107 * Emits the packet for switching the blitter from X to Y tiled or back.
108 *
109 * This has to be called in a single BEGIN_BATCH_BLT_TILED() /
110 * ADVANCE_BATCH_TILED(). This is because BCS_SWCTRL is saved and restored as
111 * part of the power context, not a render context, and if the batchbuffer was
112 * to get flushed between setting and blitting, or blitting and restoring, our
113 * tiling state would leak into other unsuspecting applications (like the X
114 * server).
115 */
116 static uint32_t *
117 set_blitter_tiling(struct brw_context *brw,
118 bool dst_y_tiled, bool src_y_tiled,
119 uint32_t *__map)
120 {
121 assert(brw->gen >= 6);
122
123 /* Idle the blitter before we update how tiling is interpreted. */
124 OUT_BATCH(MI_FLUSH_DW);
125 OUT_BATCH(0);
126 OUT_BATCH(0);
127 OUT_BATCH(0);
128
129 OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
130 OUT_BATCH(BCS_SWCTRL);
131 OUT_BATCH((BCS_SWCTRL_DST_Y | BCS_SWCTRL_SRC_Y) << 16 |
132 (dst_y_tiled ? BCS_SWCTRL_DST_Y : 0) |
133 (src_y_tiled ? BCS_SWCTRL_SRC_Y : 0));
134 return __map;
135 }
136 #define SET_BLITTER_TILING(...) __map = set_blitter_tiling(__VA_ARGS__, __map)
137
138 #define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled) \
139 BEGIN_BATCH_BLT(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0)); \
140 if (dst_y_tiled || src_y_tiled) \
141 SET_BLITTER_TILING(brw, dst_y_tiled, src_y_tiled)
142
143 #define ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled) \
144 if (dst_y_tiled || src_y_tiled) \
145 SET_BLITTER_TILING(brw, false, false); \
146 ADVANCE_BATCH()
147
148 static int
149 blt_pitch(struct intel_mipmap_tree *mt)
150 {
151 int pitch = mt->pitch;
152 if (mt->tiling)
153 pitch /= 4;
154 return pitch;
155 }
156
157 bool
158 intel_miptree_blit_compatible_formats(mesa_format src, mesa_format dst)
159 {
160 /* The BLT doesn't handle sRGB conversion */
161 assert(src == _mesa_get_srgb_format_linear(src));
162 assert(dst == _mesa_get_srgb_format_linear(dst));
163
164 /* No swizzle or format conversions possible, except... */
165 if (src == dst)
166 return true;
167
168 /* ...we can either discard the alpha channel when going from A->X,
169 * or we can fill the alpha channel with 0xff when going from X->A
170 */
171 if (src == MESA_FORMAT_B8G8R8A8_UNORM || src == MESA_FORMAT_B8G8R8X8_UNORM)
172 return (dst == MESA_FORMAT_B8G8R8A8_UNORM ||
173 dst == MESA_FORMAT_B8G8R8X8_UNORM);
174
175 if (src == MESA_FORMAT_R8G8B8A8_UNORM || src == MESA_FORMAT_R8G8B8X8_UNORM)
176 return (dst == MESA_FORMAT_R8G8B8A8_UNORM ||
177 dst == MESA_FORMAT_R8G8B8X8_UNORM);
178
179 return false;
180 }
181
182 static void
183 get_blit_intratile_offset_el(const struct brw_context *brw,
184 struct intel_mipmap_tree *mt,
185 uint32_t total_x_offset_el,
186 uint32_t total_y_offset_el,
187 uint32_t *base_address_offset,
188 uint32_t *x_offset_el,
189 uint32_t *y_offset_el)
190 {
191 enum isl_tiling tiling = intel_miptree_get_isl_tiling(mt);
192 isl_tiling_get_intratile_offset_el(&brw->isl_dev,
193 tiling, mt->cpp, mt->pitch,
194 total_x_offset_el, total_y_offset_el,
195 base_address_offset,
196 x_offset_el, y_offset_el);
197 if (tiling == ISL_TILING_LINEAR) {
198 /* From the Broadwell PRM docs for XY_SRC_COPY_BLT::SourceBaseAddress:
199 *
200 * "Base address of the destination surface: X=0, Y=0. Lower 32bits
201 * of the 48bit addressing. When Src Tiling is enabled (Bit_15
202 * enabled), this address must be 4KB-aligned. When Tiling is not
203 * enabled, this address should be CL (64byte) aligned."
204 *
205 * The offsets we get from ISL in the tiled case are already aligned.
206 * In the linear case, we need to do some of our own aligning.
207 */
208 assert(mt->pitch % 64 == 0);
209 uint32_t delta = *base_address_offset & 63;
210 assert(delta % mt->cpp == 0);
211 *base_address_offset -= delta;
212 *x_offset_el += delta / mt->cpp;
213 } else {
214 assert(*base_address_offset % 4096 == 0);
215 }
216 }
217
218 static bool
219 emit_miptree_blit(struct brw_context *brw,
220 struct intel_mipmap_tree *src_mt,
221 uint32_t src_x, uint32_t src_y,
222 struct intel_mipmap_tree *dst_mt,
223 uint32_t dst_x, uint32_t dst_y,
224 uint32_t width, uint32_t height,
225 bool reverse, GLenum logicop)
226 {
227 /* According to the Ivy Bridge PRM, Vol1 Part4, section 1.2.1.2 (Graphics
228 * Data Size Limitations):
229 *
230 * The BLT engine is capable of transferring very large quantities of
231 * graphics data. Any graphics data read from and written to the
232 * destination is permitted to represent a number of pixels that
233 * occupies up to 65,536 scan lines and up to 32,768 bytes per scan line
234 * at the destination. The maximum number of pixels that may be
235 * represented per scan line’s worth of graphics data depends on the
236 * color depth.
237 *
238 * The blitter's pitch is a signed 16-bit integer, but measured in bytes
239 * for linear surfaces and DWords for tiled surfaces. So the maximum
240 * pitch is 32k linear and 128k tiled.
241 */
242 if (blt_pitch(src_mt) >= 32768 || blt_pitch(dst_mt) >= 32768) {
243 perf_debug("Falling back due to >= 32k/128k pitch\n");
244 return false;
245 }
246
247 /* We need to split the blit into chunks that each fit within the blitter's
248 * restrictions. We can't use a chunk size of 32768 because we need to
249 * ensure that src_tile_x + chunk_size fits. We choose 16384 because it's
250 * a nice round power of two, big enough that performance won't suffer, and
251 * small enough to guarantee everything fits.
252 */
253 const uint32_t max_chunk_size = 16384;
254
255 for (uint32_t chunk_x = 0; chunk_x < width; chunk_x += max_chunk_size) {
256 for (uint32_t chunk_y = 0; chunk_y < height; chunk_y += max_chunk_size) {
257 const uint32_t chunk_w = MIN2(max_chunk_size, width - chunk_x);
258 const uint32_t chunk_h = MIN2(max_chunk_size, height - chunk_y);
259
260 uint32_t src_offset, src_tile_x, src_tile_y;
261 get_blit_intratile_offset_el(brw, src_mt,
262 src_x + chunk_x, src_y + chunk_y,
263 &src_offset, &src_tile_x, &src_tile_y);
264
265 uint32_t dst_offset, dst_tile_x, dst_tile_y;
266 get_blit_intratile_offset_el(brw, dst_mt,
267 dst_x + chunk_x, dst_y + chunk_y,
268 &dst_offset, &dst_tile_x, &dst_tile_y);
269
270 if (!intelEmitCopyBlit(brw,
271 src_mt->cpp,
272 reverse ? -src_mt->pitch : src_mt->pitch,
273 src_mt->bo, src_mt->offset + src_offset,
274 src_mt->tiling,
275 src_mt->tr_mode,
276 dst_mt->pitch,
277 dst_mt->bo, dst_mt->offset + dst_offset,
278 dst_mt->tiling,
279 dst_mt->tr_mode,
280 src_tile_x, src_tile_y,
281 dst_tile_x, dst_tile_y,
282 chunk_w, chunk_h,
283 logicop)) {
284 /* If this is ever going to fail, it will fail on the first chunk */
285 assert(chunk_x == 0 && chunk_y == 0);
286 return false;
287 }
288 }
289 }
290
291 return true;
292 }
293
294 /**
295 * Implements a rectangular block transfer (blit) of pixels between two
296 * miptrees.
297 *
298 * Our blitter can operate on 1, 2, or 4-byte-per-pixel data, with generous,
299 * but limited, pitches and sizes allowed.
300 *
301 * The src/dst coordinates are relative to the given level/slice of the
302 * miptree.
303 *
304 * If @src_flip or @dst_flip is set, then the rectangle within that miptree
305 * will be inverted (including scanline order) when copying. This is common
306 * in GL when copying between window system and user-created
307 * renderbuffers/textures.
308 */
309 bool
310 intel_miptree_blit(struct brw_context *brw,
311 struct intel_mipmap_tree *src_mt,
312 int src_level, int src_slice,
313 uint32_t src_x, uint32_t src_y, bool src_flip,
314 struct intel_mipmap_tree *dst_mt,
315 int dst_level, int dst_slice,
316 uint32_t dst_x, uint32_t dst_y, bool dst_flip,
317 uint32_t width, uint32_t height,
318 GLenum logicop)
319 {
320 /* The blitter doesn't understand multisampling at all. */
321 if (src_mt->num_samples > 0 || dst_mt->num_samples > 0)
322 return false;
323
324 /* No sRGB decode or encode is done by the hardware blitter, which is
325 * consistent with what we want in many callers (glCopyTexSubImage(),
326 * texture validation, etc.).
327 */
328 mesa_format src_format = _mesa_get_srgb_format_linear(src_mt->format);
329 mesa_format dst_format = _mesa_get_srgb_format_linear(dst_mt->format);
330
331 /* The blitter doesn't support doing any format conversions. We do also
332 * support blitting ARGB8888 to XRGB8888 (trivial, the values dropped into
333 * the X channel don't matter), and XRGB8888 to ARGB8888 by setting the A
334 * channel to 1.0 at the end.
335 */
336 if (!intel_miptree_blit_compatible_formats(src_format, dst_format)) {
337 perf_debug("%s: Can't use hardware blitter from %s to %s, "
338 "falling back.\n", __func__,
339 _mesa_get_format_name(src_format),
340 _mesa_get_format_name(dst_format));
341 return false;
342 }
343
344 /* The blitter has no idea about HiZ or fast color clears, so we need to
345 * resolve the miptrees before we do anything.
346 */
347 intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_slice);
348 intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_slice);
349 intel_miptree_resolve_color(brw, src_mt, src_level, src_slice, 1, 0);
350 intel_miptree_resolve_color(brw, dst_mt, dst_level, dst_slice, 1, 0);
351
352 if (src_flip)
353 src_y = minify(src_mt->physical_height0, src_level - src_mt->first_level) - src_y - height;
354
355 if (dst_flip)
356 dst_y = minify(dst_mt->physical_height0, dst_level - dst_mt->first_level) - dst_y - height;
357
358 uint32_t src_image_x, src_image_y, dst_image_x, dst_image_y;
359 intel_miptree_get_image_offset(src_mt, src_level, src_slice,
360 &src_image_x, &src_image_y);
361 intel_miptree_get_image_offset(dst_mt, dst_level, dst_slice,
362 &dst_image_x, &dst_image_y);
363 src_x += src_image_x;
364 src_y += src_image_y;
365 dst_x += dst_image_x;
366 dst_y += dst_image_y;
367
368 if (!emit_miptree_blit(brw, src_mt, src_x, src_y,
369 dst_mt, dst_x, dst_y, width, height,
370 src_flip != dst_flip, logicop)) {
371 return false;
372 }
373
374 /* XXX This could be done in a single pass using XY_FULL_MONO_PATTERN_BLT */
375 if (_mesa_get_format_bits(src_format, GL_ALPHA_BITS) == 0 &&
376 _mesa_get_format_bits(dst_format, GL_ALPHA_BITS) > 0) {
377 intel_miptree_set_alpha_to_one(brw, dst_mt,
378 dst_x, dst_y,
379 width, height);
380 }
381
382 return true;
383 }
384
385 bool
386 intel_miptree_copy(struct brw_context *brw,
387 struct intel_mipmap_tree *src_mt,
388 int src_level, int src_slice,
389 uint32_t src_x, uint32_t src_y,
390 struct intel_mipmap_tree *dst_mt,
391 int dst_level, int dst_slice,
392 uint32_t dst_x, uint32_t dst_y,
393 uint32_t src_width, uint32_t src_height)
394 {
395 /* The blitter doesn't understand multisampling at all. */
396 if (src_mt->num_samples > 0 || dst_mt->num_samples > 0)
397 return false;
398
399 if (src_mt->format == MESA_FORMAT_S_UINT8)
400 return false;
401
402 /* The blitter has no idea about HiZ or fast color clears, so we need to
403 * resolve the miptrees before we do anything.
404 */
405 intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_slice);
406 intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_slice);
407 intel_miptree_resolve_color(brw, src_mt, src_level, src_slice, 1, 0);
408 intel_miptree_resolve_color(brw, dst_mt, dst_level, dst_slice, 1, 0);
409
410 uint32_t src_image_x, src_image_y;
411 intel_miptree_get_image_offset(src_mt, src_level, src_slice,
412 &src_image_x, &src_image_y);
413
414 if (_mesa_is_format_compressed(src_mt->format)) {
415 GLuint bw, bh;
416 _mesa_get_format_block_size(src_mt->format, &bw, &bh);
417
418 /* Compressed textures need not have dimensions that are a multiple of
419 * the block size. Rectangles in compressed textures do need to be a
420 * multiple of the block size. The one exception is that the right and
421 * bottom edges may be at the right or bottom edge of the miplevel even
422 * if it's not aligned.
423 */
424 assert(src_x % bw == 0);
425 assert(src_y % bh == 0);
426 assert(src_width % bw == 0 ||
427 src_x + src_width == minify(src_mt->logical_width0, src_level));
428 assert(src_height % bh == 0 ||
429 src_y + src_height == minify(src_mt->logical_height0, src_level));
430
431 src_x /= (int)bw;
432 src_y /= (int)bh;
433 src_width /= (int)bw;
434 src_height /= (int)bh;
435 }
436 src_x += src_image_x;
437 src_y += src_image_y;
438
439 uint32_t dst_image_x, dst_image_y;
440 intel_miptree_get_image_offset(dst_mt, dst_level, dst_slice,
441 &dst_image_x, &dst_image_y);
442
443 if (_mesa_is_format_compressed(dst_mt->format)) {
444 GLuint bw, bh;
445 _mesa_get_format_block_size(dst_mt->format, &bw, &bh);
446
447 assert(dst_x % bw == 0);
448 assert(dst_y % bh == 0);
449
450 dst_x /= (int)bw;
451 dst_y /= (int)bh;
452 }
453 dst_x += dst_image_x;
454 dst_y += dst_image_y;
455
456 return emit_miptree_blit(brw, src_mt, src_x, src_y,
457 dst_mt, dst_x, dst_y,
458 src_width, src_height, false, GL_COPY);
459 }
460
461 static bool
462 alignment_valid(struct brw_context *brw, unsigned offset, uint32_t tiling)
463 {
464 /* Tiled buffers must be page-aligned (4K). */
465 if (tiling != I915_TILING_NONE)
466 return (offset & 4095) == 0;
467
468 /* On Gen8+, linear buffers must be cacheline-aligned. */
469 if (brw->gen >= 8)
470 return (offset & 63) == 0;
471
472 return true;
473 }
474
475 static bool
476 can_fast_copy_blit(struct brw_context *brw,
477 drm_intel_bo *src_buffer,
478 int16_t src_x, int16_t src_y,
479 uintptr_t src_offset, uint32_t src_pitch,
480 uint32_t src_tiling, uint32_t src_tr_mode,
481 drm_intel_bo *dst_buffer,
482 int16_t dst_x, int16_t dst_y,
483 uintptr_t dst_offset, uint32_t dst_pitch,
484 uint32_t dst_tiling, uint32_t dst_tr_mode,
485 int16_t w, int16_t h, uint32_t cpp,
486 GLenum logic_op)
487 {
488 const bool dst_tiling_none = dst_tiling == I915_TILING_NONE;
489 const bool src_tiling_none = src_tiling == I915_TILING_NONE;
490
491 if (brw->gen < 9)
492 return false;
493
494 /* Enable fast copy blit only if the surfaces are Yf/Ys tiled.
495 * FIXME: Based on performance data, remove this condition later to
496 * enable for all types of surfaces.
497 */
498 if (src_tr_mode == INTEL_MIPTREE_TRMODE_NONE &&
499 dst_tr_mode == INTEL_MIPTREE_TRMODE_NONE)
500 return false;
501
502 if (logic_op != GL_COPY)
503 return false;
504
505 /* The start pixel for Fast Copy blit should be on an OWord boundary. */
506 if ((dst_x * cpp | src_x * cpp) & 15)
507 return false;
508
509 /* For all surface types buffers must be cacheline-aligned. */
510 if ((dst_offset | src_offset) & 63)
511 return false;
512
513 /* Color depths which are not power of 2 or greater than 128 bits are
514 * not supported.
515 */
516 if (!_mesa_is_pow_two(cpp) || cpp > 16)
517 return false;
518
519 /* For Fast Copy Blits the pitch cannot be a negative number. So, bit 15
520 * of the destination pitch must be zero.
521 */
522 if ((src_pitch >> 15 & 1) != 0 || (dst_pitch >> 15 & 1) != 0)
523 return false;
524
525 /* For Linear surfaces, the pitch has to be an OWord (16byte) multiple. */
526 if ((src_tiling_none && src_pitch % 16 != 0) ||
527 (dst_tiling_none && dst_pitch % 16 != 0))
528 return false;
529
530 return true;
531 }
532
533 static uint32_t
534 xy_blit_cmd(uint32_t src_tiling, uint32_t src_tr_mode,
535 uint32_t dst_tiling, uint32_t dst_tr_mode,
536 uint32_t cpp, bool use_fast_copy_blit)
537 {
538 uint32_t CMD = 0;
539
540 if (use_fast_copy_blit) {
541 CMD = XY_FAST_COPY_BLT_CMD;
542
543 if (dst_tiling != I915_TILING_NONE)
544 SET_TILING_XY_FAST_COPY_BLT(dst_tiling, dst_tr_mode, XY_FAST_DST);
545
546 if (src_tiling != I915_TILING_NONE)
547 SET_TILING_XY_FAST_COPY_BLT(src_tiling, src_tr_mode, XY_FAST_SRC);
548 } else {
549 assert(cpp <= 4);
550 switch (cpp) {
551 case 1:
552 case 2:
553 CMD = XY_SRC_COPY_BLT_CMD;
554 break;
555 case 4:
556 CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
557 break;
558 default:
559 unreachable("not reached");
560 }
561
562 if (dst_tiling != I915_TILING_NONE)
563 CMD |= XY_DST_TILED;
564
565 if (src_tiling != I915_TILING_NONE)
566 CMD |= XY_SRC_TILED;
567 }
568 return CMD;
569 }
570
571 /* Copy BitBlt
572 */
573 bool
574 intelEmitCopyBlit(struct brw_context *brw,
575 GLuint cpp,
576 int32_t src_pitch,
577 drm_intel_bo *src_buffer,
578 GLuint src_offset,
579 uint32_t src_tiling,
580 uint32_t src_tr_mode,
581 int32_t dst_pitch,
582 drm_intel_bo *dst_buffer,
583 GLuint dst_offset,
584 uint32_t dst_tiling,
585 uint32_t dst_tr_mode,
586 GLshort src_x, GLshort src_y,
587 GLshort dst_x, GLshort dst_y,
588 GLshort w, GLshort h,
589 GLenum logic_op)
590 {
591 GLuint CMD, BR13, pass = 0;
592 int dst_y2 = dst_y + h;
593 int dst_x2 = dst_x + w;
594 drm_intel_bo *aper_array[3];
595 bool dst_y_tiled = dst_tiling == I915_TILING_Y;
596 bool src_y_tiled = src_tiling == I915_TILING_Y;
597 bool use_fast_copy_blit = false;
598 uint32_t src_tile_w, src_tile_h;
599 uint32_t dst_tile_w, dst_tile_h;
600
601 if ((dst_y_tiled || src_y_tiled) && brw->gen < 6)
602 return false;
603
604 /* do space check before going any further */
605 do {
606 aper_array[0] = brw->batch.bo;
607 aper_array[1] = dst_buffer;
608 aper_array[2] = src_buffer;
609
610 if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
611 intel_batchbuffer_flush(brw);
612 pass++;
613 } else
614 break;
615 } while (pass < 2);
616
617 if (pass >= 2)
618 return false;
619
620 unsigned length = brw->gen >= 8 ? 10 : 8;
621
622 intel_batchbuffer_require_space(brw, length * 4, BLT_RING);
623 DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
624 __func__,
625 src_buffer, src_pitch, src_offset, src_x, src_y,
626 dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
627
628 intel_get_tile_dims(src_tiling, src_tr_mode, cpp, &src_tile_w, &src_tile_h);
629 intel_get_tile_dims(dst_tiling, dst_tr_mode, cpp, &dst_tile_w, &dst_tile_h);
630
631 /* For Tiled surfaces, the pitch has to be a multiple of the Tile width
632 * (X direction width of the Tile). This is ensured while allocating the
633 * buffer object.
634 */
635 assert(src_tiling == I915_TILING_NONE || (src_pitch % src_tile_w) == 0);
636 assert(dst_tiling == I915_TILING_NONE || (dst_pitch % dst_tile_w) == 0);
637
638 use_fast_copy_blit = can_fast_copy_blit(brw,
639 src_buffer,
640 src_x, src_y,
641 src_offset, src_pitch,
642 src_tiling, src_tr_mode,
643 dst_buffer,
644 dst_x, dst_y,
645 dst_offset, dst_pitch,
646 dst_tiling, dst_tr_mode,
647 w, h, cpp, logic_op);
648 if (!use_fast_copy_blit &&
649 (src_tr_mode != INTEL_MIPTREE_TRMODE_NONE ||
650 dst_tr_mode != INTEL_MIPTREE_TRMODE_NONE))
651 return false;
652
653 if (use_fast_copy_blit) {
654 assert(logic_op == GL_COPY);
655
656 /* When two sequential fast copy blits have different source surfaces,
657 * but their destinations refer to the same destination surfaces and
658 * therefore destinations overlap it is imperative that a flush be
659 * inserted between the two blits.
660 *
661 * FIXME: Figure out a way to avoid flushing when not required.
662 */
663 brw_emit_mi_flush(brw);
664
665 assert(cpp <= 16);
666 BR13 = br13_for_cpp(cpp);
667
668 if (src_tr_mode == INTEL_MIPTREE_TRMODE_YF)
669 BR13 |= XY_FAST_SRC_TRMODE_YF;
670
671 if (dst_tr_mode == INTEL_MIPTREE_TRMODE_YF)
672 BR13 |= XY_FAST_DST_TRMODE_YF;
673
674 CMD = xy_blit_cmd(src_tiling, src_tr_mode,
675 dst_tiling, dst_tr_mode,
676 cpp, use_fast_copy_blit);
677
678 } else {
679 /* For big formats (such as floating point), do the copy using 16 or
680 * 32bpp and multiply the coordinates.
681 */
682 if (cpp > 4) {
683 if (cpp % 4 == 2) {
684 dst_x *= cpp / 2;
685 dst_x2 *= cpp / 2;
686 src_x *= cpp / 2;
687 cpp = 2;
688 } else {
689 assert(cpp % 4 == 0);
690 dst_x *= cpp / 4;
691 dst_x2 *= cpp / 4;
692 src_x *= cpp / 4;
693 cpp = 4;
694 }
695 }
696
697 if (!alignment_valid(brw, dst_offset, dst_tiling))
698 return false;
699 if (!alignment_valid(brw, src_offset, src_tiling))
700 return false;
701
702 /* Blit pitch must be dword-aligned. Otherwise, the hardware appears to drop
703 * the low bits. Offsets must be naturally aligned.
704 */
705 if (src_pitch % 4 != 0 || src_offset % cpp != 0 ||
706 dst_pitch % 4 != 0 || dst_offset % cpp != 0)
707 return false;
708
709 assert(cpp <= 4);
710 BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16;
711
712 CMD = xy_blit_cmd(src_tiling, src_tr_mode,
713 dst_tiling, dst_tr_mode,
714 cpp, use_fast_copy_blit);
715 }
716
717 /* For tiled source and destination, pitch value should be specified
718 * as a number of Dwords.
719 */
720 if (dst_tiling != I915_TILING_NONE)
721 dst_pitch /= 4;
722
723 if (src_tiling != I915_TILING_NONE)
724 src_pitch /= 4;
725
726 if (dst_y2 <= dst_y || dst_x2 <= dst_x)
727 return true;
728
729 assert(dst_x < dst_x2);
730 assert(dst_y < dst_y2);
731
732 BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, src_y_tiled);
733 OUT_BATCH(CMD | (length - 2));
734 OUT_BATCH(BR13 | (uint16_t)dst_pitch);
735 OUT_BATCH(SET_FIELD(dst_y, BLT_Y) | SET_FIELD(dst_x, BLT_X));
736 OUT_BATCH(SET_FIELD(dst_y2, BLT_Y) | SET_FIELD(dst_x2, BLT_X));
737 if (brw->gen >= 8) {
738 OUT_RELOC64(dst_buffer,
739 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
740 dst_offset);
741 } else {
742 OUT_RELOC(dst_buffer,
743 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
744 dst_offset);
745 }
746 OUT_BATCH(SET_FIELD(src_y, BLT_Y) | SET_FIELD(src_x, BLT_X));
747 OUT_BATCH((uint16_t)src_pitch);
748 if (brw->gen >= 8) {
749 OUT_RELOC64(src_buffer,
750 I915_GEM_DOMAIN_RENDER, 0,
751 src_offset);
752 } else {
753 OUT_RELOC(src_buffer,
754 I915_GEM_DOMAIN_RENDER, 0,
755 src_offset);
756 }
757
758 ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled);
759
760 brw_emit_mi_flush(brw);
761
762 return true;
763 }
764
765 bool
766 intelEmitImmediateColorExpandBlit(struct brw_context *brw,
767 GLuint cpp,
768 GLubyte *src_bits, GLuint src_size,
769 GLuint fg_color,
770 GLshort dst_pitch,
771 drm_intel_bo *dst_buffer,
772 GLuint dst_offset,
773 uint32_t dst_tiling,
774 GLshort x, GLshort y,
775 GLshort w, GLshort h,
776 GLenum logic_op)
777 {
778 int dwords = ALIGN(src_size, 8) / 4;
779 uint32_t opcode, br13, blit_cmd;
780
781 if (dst_tiling != I915_TILING_NONE) {
782 if (dst_offset & 4095)
783 return false;
784 if (dst_tiling == I915_TILING_Y)
785 return false;
786 }
787
788 assert((logic_op >= GL_CLEAR) && (logic_op <= (GL_CLEAR + 0x0f)));
789 assert(dst_pitch > 0);
790
791 if (w < 0 || h < 0)
792 return true;
793
794 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
795 __func__,
796 dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
797
798 unsigned xy_setup_blt_length = brw->gen >= 8 ? 10 : 8;
799 intel_batchbuffer_require_space(brw, (xy_setup_blt_length * 4) +
800 (3 * 4) + dwords * 4, BLT_RING);
801
802 opcode = XY_SETUP_BLT_CMD;
803 if (cpp == 4)
804 opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
805 if (dst_tiling != I915_TILING_NONE) {
806 opcode |= XY_DST_TILED;
807 dst_pitch /= 4;
808 }
809
810 br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
811 br13 |= br13_for_cpp(cpp);
812
813 blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
814 if (dst_tiling != I915_TILING_NONE)
815 blit_cmd |= XY_DST_TILED;
816
817 BEGIN_BATCH_BLT(xy_setup_blt_length + 3);
818 OUT_BATCH(opcode | (xy_setup_blt_length - 2));
819 OUT_BATCH(br13);
820 OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
821 OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
822 if (brw->gen >= 8) {
823 OUT_RELOC64(dst_buffer,
824 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
825 dst_offset);
826 } else {
827 OUT_RELOC(dst_buffer,
828 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
829 dst_offset);
830 }
831 OUT_BATCH(0); /* bg */
832 OUT_BATCH(fg_color); /* fg */
833 OUT_BATCH(0); /* pattern base addr */
834 if (brw->gen >= 8)
835 OUT_BATCH(0);
836
837 OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
838 OUT_BATCH(SET_FIELD(y, BLT_Y) | SET_FIELD(x, BLT_X));
839 OUT_BATCH(SET_FIELD(y + h, BLT_Y) | SET_FIELD(x + w, BLT_X));
840 ADVANCE_BATCH();
841
842 intel_batchbuffer_data(brw, src_bits, dwords * 4, BLT_RING);
843
844 brw_emit_mi_flush(brw);
845
846 return true;
847 }
848
849 /* We don't have a memmove-type blit like some other hardware, so we'll do a
850 * rectangular blit covering a large space, then emit 1-scanline blit at the
851 * end to cover the last if we need.
852 */
853 void
854 intel_emit_linear_blit(struct brw_context *brw,
855 drm_intel_bo *dst_bo,
856 unsigned int dst_offset,
857 drm_intel_bo *src_bo,
858 unsigned int src_offset,
859 unsigned int size)
860 {
861 struct gl_context *ctx = &brw->ctx;
862 GLuint pitch, height;
863 int16_t src_x, dst_x;
864 bool ok;
865
866 do {
867 /* The pitch given to the GPU must be DWORD aligned, and
868 * we want width to match pitch. Max width is (1 << 15 - 1),
869 * rounding that down to the nearest DWORD is 1 << 15 - 4
870 */
871 pitch = ROUND_DOWN_TO(MIN2(size, (1 << 15) - 64), 4);
872 height = (size < pitch || pitch == 0) ? 1 : size / pitch;
873
874 src_x = src_offset % 64;
875 dst_x = dst_offset % 64;
876 pitch = ALIGN(MIN2(size, (1 << 15) - 64), 4);
877 assert(src_x + pitch < 1 << 15);
878 assert(dst_x + pitch < 1 << 15);
879
880 ok = intelEmitCopyBlit(brw, 1,
881 pitch, src_bo, src_offset - src_x, I915_TILING_NONE,
882 INTEL_MIPTREE_TRMODE_NONE,
883 pitch, dst_bo, dst_offset - dst_x, I915_TILING_NONE,
884 INTEL_MIPTREE_TRMODE_NONE,
885 src_x, 0, /* src x/y */
886 dst_x, 0, /* dst x/y */
887 MIN2(size, pitch), height, /* w, h */
888 GL_COPY);
889 if (!ok) {
890 _mesa_problem(ctx, "Failed to linear blit %dx%d\n",
891 MIN2(size, pitch), height);
892 return;
893 }
894
895 pitch *= height;
896 if (size <= pitch)
897 return;
898
899 src_offset += pitch;
900 dst_offset += pitch;
901 size -= pitch;
902 } while (1);
903 }
904
905 /**
906 * Used to initialize the alpha value of an ARGB8888 miptree after copying
907 * into it from an XRGB8888 source.
908 *
909 * This is very common with glCopyTexImage2D(). Note that the coordinates are
910 * relative to the start of the miptree, not relative to a slice within the
911 * miptree.
912 */
913 static void
914 intel_miptree_set_alpha_to_one(struct brw_context *brw,
915 struct intel_mipmap_tree *mt,
916 int x, int y, int width, int height)
917 {
918 uint32_t BR13, CMD;
919 int pitch, cpp;
920 drm_intel_bo *aper_array[2];
921
922 pitch = mt->pitch;
923 cpp = mt->cpp;
924
925 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
926 __func__, mt->bo, pitch, x, y, width, height);
927
928 BR13 = br13_for_cpp(cpp) | 0xf0 << 16;
929 CMD = XY_COLOR_BLT_CMD;
930 CMD |= XY_BLT_WRITE_ALPHA;
931
932 if (mt->tiling != I915_TILING_NONE) {
933 CMD |= XY_DST_TILED;
934 pitch /= 4;
935 }
936 BR13 |= pitch;
937
938 /* do space check before going any further */
939 aper_array[0] = brw->batch.bo;
940 aper_array[1] = mt->bo;
941
942 if (drm_intel_bufmgr_check_aperture_space(aper_array,
943 ARRAY_SIZE(aper_array)) != 0) {
944 intel_batchbuffer_flush(brw);
945 }
946
947 unsigned length = brw->gen >= 8 ? 7 : 6;
948 bool dst_y_tiled = mt->tiling == I915_TILING_Y;
949
950 /* We need to split the blit into chunks that each fit within the blitter's
951 * restrictions. We can't use a chunk size of 32768 because we need to
952 * ensure that src_tile_x + chunk_size fits. We choose 16384 because it's
953 * a nice round power of two, big enough that performance won't suffer, and
954 * small enough to guarantee everything fits.
955 */
956 const uint32_t max_chunk_size = 16384;
957
958 for (uint32_t chunk_x = 0; chunk_x < width; chunk_x += max_chunk_size) {
959 for (uint32_t chunk_y = 0; chunk_y < height; chunk_y += max_chunk_size) {
960 const uint32_t chunk_w = MIN2(max_chunk_size, width - chunk_x);
961 const uint32_t chunk_h = MIN2(max_chunk_size, height - chunk_y);
962
963 uint32_t offset, tile_x, tile_y;
964 get_blit_intratile_offset_el(brw, mt,
965 x + chunk_x, y + chunk_y,
966 &offset, &tile_x, &tile_y);
967
968 BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, false);
969 OUT_BATCH(CMD | (length - 2));
970 OUT_BATCH(BR13);
971 OUT_BATCH(SET_FIELD(y + chunk_y, BLT_Y) |
972 SET_FIELD(x + chunk_x, BLT_X));
973 OUT_BATCH(SET_FIELD(y + chunk_y + chunk_h, BLT_Y) |
974 SET_FIELD(x + chunk_x + chunk_w, BLT_X));
975 if (brw->gen >= 8) {
976 OUT_RELOC64(mt->bo,
977 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
978 offset);
979 } else {
980 OUT_RELOC(mt->bo,
981 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
982 offset);
983 }
984 OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
985 ADVANCE_BATCH_TILED(dst_y_tiled, false);
986 }
987 }
988
989 brw_emit_mi_flush(brw);
990 }