src/mesa/drivers/dri/i965/intel_chipset.h

   1  /*
   2  * Copyright © 2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #define PCI_CHIP_IGD_GM                 0xA011
  29 #define PCI_CHIP_IGD_G                  0xA001
  30
  31 #define IS_IGDGM(devid) (devid == PCI_CHIP_IGD_GM)
  32 #define IS_IGDG(devid)  (devid == PCI_CHIP_IGD_G)
  33 #define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid))
  34
  35 #define PCI_CHIP_I965_G                 0x29A2
  36 #define PCI_CHIP_I965_Q                 0x2992
  37 #define PCI_CHIP_I965_G_1               0x2982
  38 #define PCI_CHIP_I946_GZ                0x2972
  39 #define PCI_CHIP_I965_GM                0x2A02
  40 #define PCI_CHIP_I965_GME               0x2A12
  41
  42 #define PCI_CHIP_GM45_GM                0x2A42
  43
  44 #define PCI_CHIP_IGD_E_G                0x2E02
  45 #define PCI_CHIP_Q45_G                  0x2E12
  46 #define PCI_CHIP_G45_G                  0x2E22
  47 #define PCI_CHIP_G41_G                  0x2E32
  48 #define PCI_CHIP_B43_G                  0x2E42
  49 #define PCI_CHIP_B43_G1                 0x2E92
  50
  51 #define PCI_CHIP_ILD_G                  0x0042
  52 #define PCI_CHIP_ILM_G                  0x0046
  53
  54 #define PCI_CHIP_SANDYBRIDGE_GT1        0x0102  /* Desktop */
  55 #define PCI_CHIP_SANDYBRIDGE_GT2        0x0112
  56 #define PCI_CHIP_SANDYBRIDGE_GT2_PLUS   0x0122
  57 #define PCI_CHIP_SANDYBRIDGE_M_GT1      0x0106  /* Mobile */
  58 #define PCI_CHIP_SANDYBRIDGE_M_GT2      0x0116
  59 #define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
  60 #define PCI_CHIP_SANDYBRIDGE_S          0x010A  /* Server */
  61
  62 #define PCI_CHIP_IVYBRIDGE_GT1          0x0152  /* Desktop */
  63 #define PCI_CHIP_IVYBRIDGE_GT2          0x0162
  64 #define PCI_CHIP_IVYBRIDGE_M_GT1        0x0156  /* Mobile */
  65 #define PCI_CHIP_IVYBRIDGE_M_GT2        0x0166
  66 #define PCI_CHIP_IVYBRIDGE_S_GT1        0x015a  /* Server */
  67 #define PCI_CHIP_IVYBRIDGE_S_GT2        0x016a
  68
  69 #define PCI_CHIP_BAYTRAIL_M_1           0x0F31
  70 #define PCI_CHIP_BAYTRAIL_M_2           0x0F32
  71 #define PCI_CHIP_BAYTRAIL_M_3           0x0F33
  72 #define PCI_CHIP_BAYTRAIL_M_4           0x0157
  73 #define PCI_CHIP_BAYTRAIL_D             0x0155
  74
  75 #define PCI_CHIP_HASWELL_GT1            0x0402 /* Desktop */
  76 #define PCI_CHIP_HASWELL_GT2            0x0412
  77 #define PCI_CHIP_HASWELL_GT3            0x0422
  78 #define PCI_CHIP_HASWELL_M_GT1          0x0406 /* Mobile */
  79 #define PCI_CHIP_HASWELL_M_GT2          0x0416
  80 #define PCI_CHIP_HASWELL_M_GT3          0x0426
  81 #define PCI_CHIP_HASWELL_S_GT1          0x040A /* Server */
  82 #define PCI_CHIP_HASWELL_S_GT2          0x041A
  83 #define PCI_CHIP_HASWELL_S_GT3          0x042A
  84 #define PCI_CHIP_HASWELL_B_GT1          0x040B /* Reserved */
  85 #define PCI_CHIP_HASWELL_B_GT2          0x041B
  86 #define PCI_CHIP_HASWELL_B_GT3          0x042B
  87 #define PCI_CHIP_HASWELL_E_GT1          0x040E /* Reserved */
  88 #define PCI_CHIP_HASWELL_E_GT2          0x041E
  89 #define PCI_CHIP_HASWELL_E_GT3          0x042E
  90 #define PCI_CHIP_HASWELL_SDV_GT1        0x0C02 /* Desktop */
  91 #define PCI_CHIP_HASWELL_SDV_GT2        0x0C12
  92 #define PCI_CHIP_HASWELL_SDV_GT3        0x0C22
  93 #define PCI_CHIP_HASWELL_SDV_M_GT1      0x0C06 /* Mobile */
  94 #define PCI_CHIP_HASWELL_SDV_M_GT2      0x0C16
  95 #define PCI_CHIP_HASWELL_SDV_M_GT3      0x0C26
  96 #define PCI_CHIP_HASWELL_SDV_S_GT1      0x0C0A /* Server */
  97 #define PCI_CHIP_HASWELL_SDV_S_GT2      0x0C1A
  98 #define PCI_CHIP_HASWELL_SDV_S_GT3      0x0C2A
  99 #define PCI_CHIP_HASWELL_SDV_B_GT1      0x0C0B /* Reserved */
 100 #define PCI_CHIP_HASWELL_SDV_B_GT2      0x0C1B
 101 #define PCI_CHIP_HASWELL_SDV_B_GT3      0x0C2B
 102 #define PCI_CHIP_HASWELL_SDV_E_GT1      0x0C0E /* Reserved */
 103 #define PCI_CHIP_HASWELL_SDV_E_GT2      0x0C1E
 104 #define PCI_CHIP_HASWELL_SDV_E_GT3      0x0C2E
 105 #define PCI_CHIP_HASWELL_ULT_GT1        0x0A02 /* Desktop */
 106 #define PCI_CHIP_HASWELL_ULT_GT2        0x0A12
 107 #define PCI_CHIP_HASWELL_ULT_GT3        0x0A22
 108 #define PCI_CHIP_HASWELL_ULT_M_GT1      0x0A06 /* Mobile */
 109 #define PCI_CHIP_HASWELL_ULT_M_GT2      0x0A16
 110 #define PCI_CHIP_HASWELL_ULT_M_GT3      0x0A26
 111 #define PCI_CHIP_HASWELL_ULT_S_GT1      0x0A0A /* Server */
 112 #define PCI_CHIP_HASWELL_ULT_S_GT2      0x0A1A
 113 #define PCI_CHIP_HASWELL_ULT_S_GT3      0x0A2A
 114 #define PCI_CHIP_HASWELL_ULT_B_GT1      0x0A0B /* Reserved */
 115 #define PCI_CHIP_HASWELL_ULT_B_GT2      0x0A1B
 116 #define PCI_CHIP_HASWELL_ULT_B_GT3      0x0A2B
 117 #define PCI_CHIP_HASWELL_ULT_E_GT1      0x0A0E /* Reserved */
 118 #define PCI_CHIP_HASWELL_ULT_E_GT2      0x0A1E
 119 #define PCI_CHIP_HASWELL_ULT_E_GT3      0x0A2E
 120 #define PCI_CHIP_HASWELL_CRW_GT1        0x0D02 /* Desktop */
 121 #define PCI_CHIP_HASWELL_CRW_GT2        0x0D12
 122 #define PCI_CHIP_HASWELL_CRW_GT3        0x0D22
 123 #define PCI_CHIP_HASWELL_CRW_M_GT1      0x0D06 /* Mobile */
 124 #define PCI_CHIP_HASWELL_CRW_M_GT2      0x0D16
 125 #define PCI_CHIP_HASWELL_CRW_M_GT3      0x0D26
 126 #define PCI_CHIP_HASWELL_CRW_S_GT1      0x0D0A /* Server */
 127 #define PCI_CHIP_HASWELL_CRW_S_GT2      0x0D1A
 128 #define PCI_CHIP_HASWELL_CRW_S_GT3      0x0D2A
 129 #define PCI_CHIP_HASWELL_CRW_B_GT1      0x0D0B /* Reserved */
 130 #define PCI_CHIP_HASWELL_CRW_B_GT2      0x0D1B
 131 #define PCI_CHIP_HASWELL_CRW_B_GT3      0x0D2B
 132 #define PCI_CHIP_HASWELL_CRW_E_GT1      0x0D0E /* Reserved */
 133 #define PCI_CHIP_HASWELL_CRW_E_GT2      0x0D1E
 134 #define PCI_CHIP_HASWELL_CRW_E_GT3      0x0D2E
 135
 136 #define IS_G45(devid)           (devid == PCI_CHIP_IGD_E_G || \
 137                                  devid == PCI_CHIP_Q45_G || \
 138                                  devid == PCI_CHIP_G45_G || \
 139                                  devid == PCI_CHIP_G41_G || \
 140                                  devid == PCI_CHIP_B43_G || \
 141                                  devid == PCI_CHIP_B43_G1)
 142 #define IS_GM45(devid)          (devid == PCI_CHIP_GM45_GM)
 143 #define IS_G4X(devid)           (IS_G45(devid) || IS_GM45(devid))
 144
 145 #define IS_ILD(devid)           (devid == PCI_CHIP_ILD_G)
 146 #define IS_ILM(devid)           (devid == PCI_CHIP_ILM_G)
 147 #define IS_GEN5(devid)          (IS_ILD(devid) || IS_ILM(devid))
 148
 149 #define IS_SNB_GT1(devid)       (devid == PCI_CHIP_SANDYBRIDGE_GT1 || \
 150                                  devid == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
 151                                  devid == PCI_CHIP_SANDYBRIDGE_S)
 152
 153 #define IS_SNB_GT2(devid)       (devid == PCI_CHIP_SANDYBRIDGE_GT2 || \
 154                                  devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
 155                                  devid == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
 156                                  devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS)
 157
 158 #define IS_GEN6(devid)          (IS_SNB_GT1(devid) || IS_SNB_GT2(devid))
 159
 160 #define IS_IVB_GT1(devid)       (devid == PCI_CHIP_IVYBRIDGE_GT1 || \
 161                                  devid == PCI_CHIP_IVYBRIDGE_M_GT1 || \
 162                                  devid == PCI_CHIP_IVYBRIDGE_S_GT1)
 163
 164 #define IS_IVB_GT2(devid)       (devid == PCI_CHIP_IVYBRIDGE_GT2 || \
 165                                  devid == PCI_CHIP_IVYBRIDGE_M_GT2 || \
 166                                  devid == PCI_CHIP_IVYBRIDGE_S_GT2)
 167
 168 #define IS_IVYBRIDGE(devid)     (IS_IVB_GT1(devid) || IS_IVB_GT2(devid))
 169
 170 #define IS_BAYTRAIL(devid)      (devid == PCI_CHIP_BAYTRAIL_M_1 || \
 171                                  devid == PCI_CHIP_BAYTRAIL_M_2 || \
 172                                  devid == PCI_CHIP_BAYTRAIL_M_3 || \
 173                                  devid == PCI_CHIP_BAYTRAIL_M_4 || \
 174                                  devid == PCI_CHIP_BAYTRAIL_D)
 175
 176 #define IS_GEN7(devid)          (IS_IVYBRIDGE(devid) || \
 177                                  IS_BAYTRAIL(devid) || \
 178                                  IS_HASWELL(devid))
 179
 180 #define IS_HSW_GT1(devid)       (devid == PCI_CHIP_HASWELL_GT1 || \
 181                                  devid == PCI_CHIP_HASWELL_M_GT1 || \
 182                                  devid == PCI_CHIP_HASWELL_S_GT1 || \
 183                                  devid == PCI_CHIP_HASWELL_B_GT1 || \
 184                                  devid == PCI_CHIP_HASWELL_E_GT1 || \
 185                                  devid == PCI_CHIP_HASWELL_SDV_GT1 || \
 186                                  devid == PCI_CHIP_HASWELL_SDV_M_GT1 || \
 187                                  devid == PCI_CHIP_HASWELL_SDV_S_GT1 || \
 188                                  devid == PCI_CHIP_HASWELL_SDV_B_GT1 || \
 189                                  devid == PCI_CHIP_HASWELL_SDV_E_GT1 || \
 190                                  devid == PCI_CHIP_HASWELL_ULT_GT1 || \
 191                                  devid == PCI_CHIP_HASWELL_ULT_M_GT1 || \
 192                                  devid == PCI_CHIP_HASWELL_ULT_S_GT1 || \
 193                                  devid == PCI_CHIP_HASWELL_ULT_B_GT1 || \
 194                                  devid == PCI_CHIP_HASWELL_ULT_E_GT1 || \
 195                                  devid == PCI_CHIP_HASWELL_CRW_GT1 || \
 196                                  devid == PCI_CHIP_HASWELL_CRW_M_GT1 || \
 197                                  devid == PCI_CHIP_HASWELL_CRW_S_GT1 || \
 198                                  devid == PCI_CHIP_HASWELL_CRW_B_GT1 || \
 199                                  devid == PCI_CHIP_HASWELL_CRW_E_GT1)
 200 #define IS_HSW_GT2(devid)       (devid == PCI_CHIP_HASWELL_GT2 || \
 201                                  devid == PCI_CHIP_HASWELL_M_GT2 || \
 202                                  devid == PCI_CHIP_HASWELL_S_GT2 || \
 203                                  devid == PCI_CHIP_HASWELL_B_GT2 || \
 204                                  devid == PCI_CHIP_HASWELL_E_GT2 || \
 205                                  devid == PCI_CHIP_HASWELL_SDV_GT2 || \
 206                                  devid == PCI_CHIP_HASWELL_SDV_M_GT2 || \
 207                                  devid == PCI_CHIP_HASWELL_SDV_S_GT2 || \
 208                                  devid == PCI_CHIP_HASWELL_SDV_B_GT2 || \
 209                                  devid == PCI_CHIP_HASWELL_SDV_E_GT2 || \
 210                                  devid == PCI_CHIP_HASWELL_ULT_GT2 || \
 211                                  devid == PCI_CHIP_HASWELL_ULT_M_GT2 || \
 212                                  devid == PCI_CHIP_HASWELL_ULT_S_GT2 || \
 213                                  devid == PCI_CHIP_HASWELL_ULT_B_GT2 || \
 214                                  devid == PCI_CHIP_HASWELL_ULT_E_GT2 || \
 215                                  devid == PCI_CHIP_HASWELL_CRW_GT2 || \
 216                                  devid == PCI_CHIP_HASWELL_CRW_M_GT2 || \
 217                                  devid == PCI_CHIP_HASWELL_CRW_S_GT2 || \
 218                                  devid == PCI_CHIP_HASWELL_CRW_B_GT2 || \
 219                                  devid == PCI_CHIP_HASWELL_CRW_E_GT2)
 220 #define IS_HSW_GT3(devid)       (devid == PCI_CHIP_HASWELL_GT3 || \
 221                                  devid == PCI_CHIP_HASWELL_M_GT3 || \
 222                                  devid == PCI_CHIP_HASWELL_S_GT3 || \
 223                                  devid == PCI_CHIP_HASWELL_B_GT3 || \
 224                                  devid == PCI_CHIP_HASWELL_E_GT3 || \
 225                                  devid == PCI_CHIP_HASWELL_SDV_GT3 || \
 226                                  devid == PCI_CHIP_HASWELL_SDV_M_GT3 || \
 227                                  devid == PCI_CHIP_HASWELL_SDV_S_GT3 || \
 228                                  devid == PCI_CHIP_HASWELL_SDV_B_GT3 || \
 229                                  devid == PCI_CHIP_HASWELL_SDV_E_GT3 || \
 230                                  devid == PCI_CHIP_HASWELL_ULT_GT3 || \
 231                                  devid == PCI_CHIP_HASWELL_ULT_M_GT3 || \
 232                                  devid == PCI_CHIP_HASWELL_ULT_S_GT3 || \
 233                                  devid == PCI_CHIP_HASWELL_ULT_B_GT3 || \
 234                                  devid == PCI_CHIP_HASWELL_ULT_E_GT3 || \
 235                                  devid == PCI_CHIP_HASWELL_CRW_GT3 || \
 236                                  devid == PCI_CHIP_HASWELL_CRW_M_GT3 || \
 237                                  devid == PCI_CHIP_HASWELL_CRW_S_GT3 || \
 238                                  devid == PCI_CHIP_HASWELL_CRW_B_GT3 || \
 239                                  devid == PCI_CHIP_HASWELL_CRW_E_GT3)
 240
 241 #define IS_HASWELL(devid)       (IS_HSW_GT1(devid) || \
 242                                  IS_HSW_GT2(devid) || \
 243                                  IS_HSW_GT3(devid))