src/mesa/drivers/dri/i965/intel_chipset.h

   1  /*
   2  * Copyright © 2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #pragma once
  29 #include <stdbool.h>
  30
  31 #define PCI_CHIP_IGD_GM                 0xA011
  32 #define PCI_CHIP_IGD_G                  0xA001
  33
  34 #define IS_IGDGM(devid) (devid == PCI_CHIP_IGD_GM)
  35 #define IS_IGDG(devid)  (devid == PCI_CHIP_IGD_G)
  36 #define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid))
  37
  38 #define PCI_CHIP_I965_G                 0x29A2
  39 #define PCI_CHIP_I965_Q                 0x2992
  40 #define PCI_CHIP_I965_G_1               0x2982
  41 #define PCI_CHIP_I946_GZ                0x2972
  42 #define PCI_CHIP_I965_GM                0x2A02
  43 #define PCI_CHIP_I965_GME               0x2A12
  44
  45 #define PCI_CHIP_GM45_GM                0x2A42
  46
  47 #define PCI_CHIP_IGD_E_G                0x2E02
  48 #define PCI_CHIP_Q45_G                  0x2E12
  49 #define PCI_CHIP_G45_G                  0x2E22
  50 #define PCI_CHIP_G41_G                  0x2E32
  51 #define PCI_CHIP_B43_G                  0x2E42
  52 #define PCI_CHIP_B43_G1                 0x2E92
  53
  54 #define PCI_CHIP_ILD_G                  0x0042
  55 #define PCI_CHIP_ILM_G                  0x0046
  56
  57 #define PCI_CHIP_SANDYBRIDGE_GT1        0x0102  /* Desktop */
  58 #define PCI_CHIP_SANDYBRIDGE_GT2        0x0112
  59 #define PCI_CHIP_SANDYBRIDGE_GT2_PLUS   0x0122
  60 #define PCI_CHIP_SANDYBRIDGE_M_GT1      0x0106  /* Mobile */
  61 #define PCI_CHIP_SANDYBRIDGE_M_GT2      0x0116
  62 #define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
  63 #define PCI_CHIP_SANDYBRIDGE_S          0x010A  /* Server */
  64
  65 #define PCI_CHIP_IVYBRIDGE_GT1          0x0152  /* Desktop */
  66 #define PCI_CHIP_IVYBRIDGE_GT2          0x0162
  67 #define PCI_CHIP_IVYBRIDGE_M_GT1        0x0156  /* Mobile */
  68 #define PCI_CHIP_IVYBRIDGE_M_GT2        0x0166
  69 #define PCI_CHIP_IVYBRIDGE_S_GT1        0x015a  /* Server */
  70 #define PCI_CHIP_IVYBRIDGE_S_GT2        0x016a
  71
  72 #define PCI_CHIP_BAYTRAIL_M_1           0x0F31
  73 #define PCI_CHIP_BAYTRAIL_M_2           0x0F32
  74 #define PCI_CHIP_BAYTRAIL_M_3           0x0F33
  75 #define PCI_CHIP_BAYTRAIL_M_4           0x0157
  76 #define PCI_CHIP_BAYTRAIL_D             0x0155
  77
  78 #define PCI_CHIP_HASWELL_GT1            0x0402 /* Desktop */
  79 #define PCI_CHIP_HASWELL_GT2            0x0412
  80 #define PCI_CHIP_HASWELL_GT3            0x0422
  81 #define PCI_CHIP_HASWELL_M_GT1          0x0406 /* Mobile */
  82 #define PCI_CHIP_HASWELL_M_GT2          0x0416
  83 #define PCI_CHIP_HASWELL_M_GT3          0x0426
  84 #define PCI_CHIP_HASWELL_S_GT1          0x040A /* Server */
  85 #define PCI_CHIP_HASWELL_S_GT2          0x041A
  86 #define PCI_CHIP_HASWELL_S_GT3          0x042A
  87 #define PCI_CHIP_HASWELL_B_GT1          0x040B /* Reserved */
  88 #define PCI_CHIP_HASWELL_B_GT2          0x041B
  89 #define PCI_CHIP_HASWELL_B_GT3          0x042B
  90 #define PCI_CHIP_HASWELL_E_GT1          0x040E /* Reserved */
  91 #define PCI_CHIP_HASWELL_E_GT2          0x041E
  92 #define PCI_CHIP_HASWELL_E_GT3          0x042E
  93 #define PCI_CHIP_HASWELL_SDV_GT1        0x0C02 /* Desktop */
  94 #define PCI_CHIP_HASWELL_SDV_GT2        0x0C12
  95 #define PCI_CHIP_HASWELL_SDV_GT3        0x0C22
  96 #define PCI_CHIP_HASWELL_SDV_M_GT1      0x0C06 /* Mobile */
  97 #define PCI_CHIP_HASWELL_SDV_M_GT2      0x0C16
  98 #define PCI_CHIP_HASWELL_SDV_M_GT3      0x0C26
  99 #define PCI_CHIP_HASWELL_SDV_S_GT1      0x0C0A /* Server */
 100 #define PCI_CHIP_HASWELL_SDV_S_GT2      0x0C1A
 101 #define PCI_CHIP_HASWELL_SDV_S_GT3      0x0C2A
 102 #define PCI_CHIP_HASWELL_SDV_B_GT1      0x0C0B /* Reserved */
 103 #define PCI_CHIP_HASWELL_SDV_B_GT2      0x0C1B
 104 #define PCI_CHIP_HASWELL_SDV_B_GT3      0x0C2B
 105 #define PCI_CHIP_HASWELL_SDV_E_GT1      0x0C0E /* Reserved */
 106 #define PCI_CHIP_HASWELL_SDV_E_GT2      0x0C1E
 107 #define PCI_CHIP_HASWELL_SDV_E_GT3      0x0C2E
 108 #define PCI_CHIP_HASWELL_ULT_GT1        0x0A02 /* Desktop */
 109 #define PCI_CHIP_HASWELL_ULT_GT2        0x0A12
 110 #define PCI_CHIP_HASWELL_ULT_GT3        0x0A22
 111 #define PCI_CHIP_HASWELL_ULT_M_GT1      0x0A06 /* Mobile */
 112 #define PCI_CHIP_HASWELL_ULT_M_GT2      0x0A16
 113 #define PCI_CHIP_HASWELL_ULT_M_GT3      0x0A26
 114 #define PCI_CHIP_HASWELL_ULT_S_GT1      0x0A0A /* Server */
 115 #define PCI_CHIP_HASWELL_ULT_S_GT2      0x0A1A
 116 #define PCI_CHIP_HASWELL_ULT_S_GT3      0x0A2A
 117 #define PCI_CHIP_HASWELL_ULT_B_GT1      0x0A0B /* Reserved */
 118 #define PCI_CHIP_HASWELL_ULT_B_GT2      0x0A1B
 119 #define PCI_CHIP_HASWELL_ULT_B_GT3      0x0A2B
 120 #define PCI_CHIP_HASWELL_ULT_E_GT1      0x0A0E /* Reserved */
 121 #define PCI_CHIP_HASWELL_ULT_E_GT2      0x0A1E
 122 #define PCI_CHIP_HASWELL_ULT_E_GT3      0x0A2E
 123 #define PCI_CHIP_HASWELL_CRW_GT1        0x0D02 /* Desktop */
 124 #define PCI_CHIP_HASWELL_CRW_GT2        0x0D12
 125 #define PCI_CHIP_HASWELL_CRW_GT3        0x0D22
 126 #define PCI_CHIP_HASWELL_CRW_M_GT1      0x0D06 /* Mobile */
 127 #define PCI_CHIP_HASWELL_CRW_M_GT2      0x0D16
 128 #define PCI_CHIP_HASWELL_CRW_M_GT3      0x0D26
 129 #define PCI_CHIP_HASWELL_CRW_S_GT1      0x0D0A /* Server */
 130 #define PCI_CHIP_HASWELL_CRW_S_GT2      0x0D1A
 131 #define PCI_CHIP_HASWELL_CRW_S_GT3      0x0D2A
 132 #define PCI_CHIP_HASWELL_CRW_B_GT1      0x0D0B /* Reserved */
 133 #define PCI_CHIP_HASWELL_CRW_B_GT2      0x0D1B
 134 #define PCI_CHIP_HASWELL_CRW_B_GT3      0x0D2B
 135 #define PCI_CHIP_HASWELL_CRW_E_GT1      0x0D0E /* Reserved */
 136 #define PCI_CHIP_HASWELL_CRW_E_GT2      0x0D1E
 137 #define PCI_CHIP_HASWELL_CRW_E_GT3      0x0D2E
 138
 139 #define IS_G45(devid)           (devid == PCI_CHIP_IGD_E_G || \
 140                                  devid == PCI_CHIP_Q45_G || \
 141                                  devid == PCI_CHIP_G45_G || \
 142                                  devid == PCI_CHIP_G41_G || \
 143                                  devid == PCI_CHIP_B43_G || \
 144                                  devid == PCI_CHIP_B43_G1)
 145 #define IS_GM45(devid)          (devid == PCI_CHIP_GM45_GM)
 146 #define IS_G4X(devid)           (IS_G45(devid) || IS_GM45(devid))
 147
 148 #define IS_ILD(devid)           (devid == PCI_CHIP_ILD_G)
 149 #define IS_ILM(devid)           (devid == PCI_CHIP_ILM_G)
 150 #define IS_GEN5(devid)          (IS_ILD(devid) || IS_ILM(devid))
 151
 152 #define IS_SNB_GT1(devid)       (devid == PCI_CHIP_SANDYBRIDGE_GT1 || \
 153                                  devid == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
 154                                  devid == PCI_CHIP_SANDYBRIDGE_S)
 155
 156 #define IS_SNB_GT2(devid)       (devid == PCI_CHIP_SANDYBRIDGE_GT2 || \
 157                                  devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
 158                                  devid == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
 159                                  devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS)
 160
 161 #define IS_GEN6(devid)          (IS_SNB_GT1(devid) || IS_SNB_GT2(devid))
 162
 163 #define IS_IVB_GT1(devid)       (devid == PCI_CHIP_IVYBRIDGE_GT1 || \
 164                                  devid == PCI_CHIP_IVYBRIDGE_M_GT1 || \
 165                                  devid == PCI_CHIP_IVYBRIDGE_S_GT1)
 166
 167 #define IS_IVB_GT2(devid)       (devid == PCI_CHIP_IVYBRIDGE_GT2 || \
 168                                  devid == PCI_CHIP_IVYBRIDGE_M_GT2 || \
 169                                  devid == PCI_CHIP_IVYBRIDGE_S_GT2)
 170
 171 #define IS_IVYBRIDGE(devid)     (IS_IVB_GT1(devid) || IS_IVB_GT2(devid))
 172
 173 #define IS_BAYTRAIL(devid)      (devid == PCI_CHIP_BAYTRAIL_M_1 || \
 174                                  devid == PCI_CHIP_BAYTRAIL_M_2 || \
 175                                  devid == PCI_CHIP_BAYTRAIL_M_3 || \
 176                                  devid == PCI_CHIP_BAYTRAIL_M_4 || \
 177                                  devid == PCI_CHIP_BAYTRAIL_D)
 178
 179 #define IS_GEN7(devid)          (IS_IVYBRIDGE(devid) || \
 180                                  IS_BAYTRAIL(devid) || \
 181                                  IS_HASWELL(devid))
 182
 183 #define IS_HSW_GT1(devid)       (devid == PCI_CHIP_HASWELL_GT1 || \
 184                                  devid == PCI_CHIP_HASWELL_M_GT1 || \
 185                                  devid == PCI_CHIP_HASWELL_S_GT1 || \
 186                                  devid == PCI_CHIP_HASWELL_B_GT1 || \
 187                                  devid == PCI_CHIP_HASWELL_E_GT1 || \
 188                                  devid == PCI_CHIP_HASWELL_SDV_GT1 || \
 189                                  devid == PCI_CHIP_HASWELL_SDV_M_GT1 || \
 190                                  devid == PCI_CHIP_HASWELL_SDV_S_GT1 || \
 191                                  devid == PCI_CHIP_HASWELL_SDV_B_GT1 || \
 192                                  devid == PCI_CHIP_HASWELL_SDV_E_GT1 || \
 193                                  devid == PCI_CHIP_HASWELL_ULT_GT1 || \
 194                                  devid == PCI_CHIP_HASWELL_ULT_M_GT1 || \
 195                                  devid == PCI_CHIP_HASWELL_ULT_S_GT1 || \
 196                                  devid == PCI_CHIP_HASWELL_ULT_B_GT1 || \
 197                                  devid == PCI_CHIP_HASWELL_ULT_E_GT1 || \
 198                                  devid == PCI_CHIP_HASWELL_CRW_GT1 || \
 199                                  devid == PCI_CHIP_HASWELL_CRW_M_GT1 || \
 200                                  devid == PCI_CHIP_HASWELL_CRW_S_GT1 || \
 201                                  devid == PCI_CHIP_HASWELL_CRW_B_GT1 || \
 202                                  devid == PCI_CHIP_HASWELL_CRW_E_GT1)
 203 #define IS_HSW_GT2(devid)       (devid == PCI_CHIP_HASWELL_GT2 || \
 204                                  devid == PCI_CHIP_HASWELL_M_GT2 || \
 205                                  devid == PCI_CHIP_HASWELL_S_GT2 || \
 206                                  devid == PCI_CHIP_HASWELL_B_GT2 || \
 207                                  devid == PCI_CHIP_HASWELL_E_GT2 || \
 208                                  devid == PCI_CHIP_HASWELL_SDV_GT2 || \
 209                                  devid == PCI_CHIP_HASWELL_SDV_M_GT2 || \
 210                                  devid == PCI_CHIP_HASWELL_SDV_S_GT2 || \
 211                                  devid == PCI_CHIP_HASWELL_SDV_B_GT2 || \
 212                                  devid == PCI_CHIP_HASWELL_SDV_E_GT2 || \
 213                                  devid == PCI_CHIP_HASWELL_ULT_GT2 || \
 214                                  devid == PCI_CHIP_HASWELL_ULT_M_GT2 || \
 215                                  devid == PCI_CHIP_HASWELL_ULT_S_GT2 || \
 216                                  devid == PCI_CHIP_HASWELL_ULT_B_GT2 || \
 217                                  devid == PCI_CHIP_HASWELL_ULT_E_GT2 || \
 218                                  devid == PCI_CHIP_HASWELL_CRW_GT2 || \
 219                                  devid == PCI_CHIP_HASWELL_CRW_M_GT2 || \
 220                                  devid == PCI_CHIP_HASWELL_CRW_S_GT2 || \
 221                                  devid == PCI_CHIP_HASWELL_CRW_B_GT2 || \
 222                                  devid == PCI_CHIP_HASWELL_CRW_E_GT2)
 223 #define IS_HSW_GT3(devid)       (devid == PCI_CHIP_HASWELL_GT3 || \
 224                                  devid == PCI_CHIP_HASWELL_M_GT3 || \
 225                                  devid == PCI_CHIP_HASWELL_S_GT3 || \
 226                                  devid == PCI_CHIP_HASWELL_B_GT3 || \
 227                                  devid == PCI_CHIP_HASWELL_E_GT3 || \
 228                                  devid == PCI_CHIP_HASWELL_SDV_GT3 || \
 229                                  devid == PCI_CHIP_HASWELL_SDV_M_GT3 || \
 230                                  devid == PCI_CHIP_HASWELL_SDV_S_GT3 || \
 231                                  devid == PCI_CHIP_HASWELL_SDV_B_GT3 || \
 232                                  devid == PCI_CHIP_HASWELL_SDV_E_GT3 || \
 233                                  devid == PCI_CHIP_HASWELL_ULT_GT3 || \
 234                                  devid == PCI_CHIP_HASWELL_ULT_M_GT3 || \
 235                                  devid == PCI_CHIP_HASWELL_ULT_S_GT3 || \
 236                                  devid == PCI_CHIP_HASWELL_ULT_B_GT3 || \
 237                                  devid == PCI_CHIP_HASWELL_ULT_E_GT3 || \
 238                                  devid == PCI_CHIP_HASWELL_CRW_GT3 || \
 239                                  devid == PCI_CHIP_HASWELL_CRW_M_GT3 || \
 240                                  devid == PCI_CHIP_HASWELL_CRW_S_GT3 || \
 241                                  devid == PCI_CHIP_HASWELL_CRW_B_GT3 || \
 242                                  devid == PCI_CHIP_HASWELL_CRW_E_GT3)
 243
 244 #define IS_HASWELL(devid)       (IS_HSW_GT1(devid) || \
 245                                  IS_HSW_GT2(devid) || \
 246                                  IS_HSW_GT3(devid))