src/mesa/drivers/dri/i965/intel_context.h

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #ifndef INTELCONTEXT_INC
  29 #define INTELCONTEXT_INC
  30
  31
  32 #include <stdbool.h>
  33 #include <string.h>
  34 #include "main/mtypes.h"
  35 #include "main/mm.h"
  36
  37 #ifdef __cplusplus
  38 extern "C" {
  39         /* Evil hack for using libdrm in a c++ compiler. */
  40         #define virtual virt
  41 #endif
  42
  43 #include "drm.h"
  44 #include "intel_bufmgr.h"
  45
  46 #include "intel_screen.h"
  47 #include "intel_tex_obj.h"
  48 #include "i915_drm.h"
  49
  50 #ifdef __cplusplus
  51         #undef virtual
  52 #endif
  53
  54 #include "tnl/t_vertex.h"
  55
  56 #define TAG(x) intel##x
  57 #include "tnl_dd/t_dd_vertex.h"
  58 #undef TAG
  59
  60 #define DV_PF_555  (1<<8)
  61 #define DV_PF_565  (2<<8)
  62 #define DV_PF_8888 (3<<8)
  63 #define DV_PF_4444 (8<<8)
  64 #define DV_PF_1555 (9<<8)
  65
  66 struct intel_region;
  67 struct intel_context;
  68
  69 typedef void (*intel_tri_func) (struct intel_context *, intelVertex *,
  70                                 intelVertex *, intelVertex *);
  71 typedef void (*intel_line_func) (struct intel_context *, intelVertex *,
  72                                  intelVertex *);
  73 typedef void (*intel_point_func) (struct intel_context *, intelVertex *);
  74
  75 /**
  76  * Bits for intel->Fallback field
  77  */
  78 /*@{*/
  79 #define INTEL_FALLBACK_DRAW_BUFFER       0x1
  80 #define INTEL_FALLBACK_READ_BUFFER       0x2
  81 #define INTEL_FALLBACK_DEPTH_BUFFER      0x4
  82 #define INTEL_FALLBACK_STENCIL_BUFFER    0x8
  83 #define INTEL_FALLBACK_USER              0x10
  84 #define INTEL_FALLBACK_RENDERMODE        0x20
  85 #define INTEL_FALLBACK_TEXTURE           0x40
  86 #define INTEL_FALLBACK_DRIVER            0x1000  /**< first for drivers */
  87 /*@}*/
  88
  89 extern void intelFallback(struct intel_context *intel, GLbitfield bit,
  90                           bool mode);
  91 #define FALLBACK( intel, bit, mode ) intelFallback( intel, bit, mode )
  92
  93
  94 #define INTEL_WRITE_PART  0x1
  95 #define INTEL_WRITE_FULL  0x2
  96 #define INTEL_READ        0x4
  97
  98 #define INTEL_MAX_FIXUP 64
  99
 100 #ifndef likely
 101 #ifdef __GNUC__
 102 #define likely(expr) (__builtin_expect(expr, 1))
 103 #define unlikely(expr) (__builtin_expect(expr, 0))
 104 #else
 105 #define likely(expr) (expr)
 106 #define unlikely(expr) (expr)
 107 #endif
 108 #endif
 109
 110 struct intel_sync_object {
 111    struct gl_sync_object Base;
 112
 113    /** Batch associated with this sync object */
 114    drm_intel_bo *bo;
 115 };
 116
 117 struct brw_context;
 118
 119 struct intel_batchbuffer {
 120    /** Current batchbuffer being queued up. */
 121    drm_intel_bo *bo;
 122    /** Last BO submitted to the hardware.  Used for glFinish(). */
 123    drm_intel_bo *last_bo;
 124    /** BO for post-sync nonzero writes for gen6 workaround. */
 125    drm_intel_bo *workaround_bo;
 126    bool need_workaround_flush;
 127
 128    struct cached_batch_item *cached_items;
 129
 130    uint16_t emit, total;
 131    uint16_t used, reserved_space;
 132    uint32_t *map;
 133    uint32_t *cpu_map;
 134 #define BATCH_SZ (8192*sizeof(uint32_t))
 135
 136    uint32_t state_batch_offset;
 137    bool is_blit;
 138    bool needs_sol_reset;
 139
 140    struct {
 141       uint16_t used;
 142       int reloc_count;
 143    } saved;
 144 };
 145
 146 /**
 147  * intel_context is derived from Mesa's context class: struct gl_context.
 148  */
 149 struct intel_context
 150 {
 151    struct gl_context ctx;  /**< base class, must be first field */
 152
 153    struct
 154    {
 155       void (*destroy) (struct intel_context * intel);
 156       void (*emit_state) (struct intel_context * intel);
 157       void (*finish_batch) (struct intel_context * intel);
 158       void (*new_batch) (struct intel_context * intel);
 159       void (*emit_invarient_state) (struct intel_context * intel);
 160       void (*update_texture_state) (struct intel_context * intel);
 161
 162       void (*render_start) (struct intel_context * intel);
 163       void (*render_prevalidate) (struct intel_context * intel);
 164       void (*set_draw_region) (struct intel_context * intel,
 165                                struct intel_region * draw_regions[],
 166                                struct intel_region * depth_region,
 167                                GLuint num_regions);
 168       void (*update_draw_buffer)(struct intel_context *intel);
 169
 170       void (*reduced_primitive_state) (struct intel_context * intel,
 171                                        GLenum rprim);
 172
 173       bool (*check_vertex_size) (struct intel_context * intel,
 174                                       GLuint expected);
 175       void (*invalidate_state) (struct intel_context *intel,
 176                                 GLuint new_state);
 177
 178       void (*assert_not_dirty) (struct intel_context *intel);
 179
 180       void (*debug_batch)(struct intel_context *intel);
 181       void (*annotate_aub)(struct intel_context *intel);
 182       bool (*render_target_supported)(struct intel_context *intel,
 183                                       struct gl_renderbuffer *rb);
 184
 185       /** Can HiZ be enabled on a depthbuffer of the given format? */
 186       bool (*is_hiz_depth_format)(struct intel_context *intel,
 187                                   gl_format format);
 188
 189       /**
 190        * Surface state operations (i965+ only)
 191        * \{
 192        */
 193       void (*update_texture_surface)(struct gl_context *ctx,
 194                                      unsigned unit,
 195                                      uint32_t *binding_table,
 196                                      unsigned surf_index);
 197       void (*update_renderbuffer_surface)(struct brw_context *brw,
 198                                           struct gl_renderbuffer *rb,
 199                                           bool layered,
 200                                           unsigned unit);
 201       void (*update_null_renderbuffer_surface)(struct brw_context *brw,
 202                                                unsigned unit);
 203       void (*create_constant_surface)(struct brw_context *brw,
 204                                       drm_intel_bo *bo,
 205                                       uint32_t offset,
 206                                       uint32_t size,
 207                                       uint32_t *out_offset,
 208                                       bool dword_pitch);
 209       /** \} */
 210
 211       /**
 212        * Send the appropriate state packets to configure depth, stencil, and
 213        * HiZ buffers (i965+ only)
 214        */
 215       void (*emit_depth_stencil_hiz)(struct brw_context *brw,
 216                                      struct intel_mipmap_tree *depth_mt,
 217                                      uint32_t depth_offset,
 218                                      uint32_t depthbuffer_format,
 219                                      uint32_t depth_surface_type,
 220                                      struct intel_mipmap_tree *stencil_mt,
 221                                      bool hiz, bool separate_stencil,
 222                                      uint32_t width, uint32_t height,
 223                                      uint32_t tile_x, uint32_t tile_y);
 224
 225    } vtbl;
 226
 227    GLbitfield Fallback;  /**< mask of INTEL_FALLBACK_x bits */
 228    GLuint NewGLState;
 229
 230    dri_bufmgr *bufmgr;
 231    unsigned int maxBatchSize;
 232
 233    /**
 234     * Generation number of the hardware: 2 is 8xx, 3 is 9xx pre-965, 4 is 965.
 235     */
 236    int gen;
 237    int gt;
 238    bool needs_ff_sync;
 239    bool is_haswell;
 240    bool is_baytrail;
 241    bool is_g4x;
 242    bool is_945;
 243    bool has_separate_stencil;
 244    bool must_use_separate_stencil;
 245    bool has_hiz;
 246    bool has_llc;
 247    bool has_swizzling;
 248
 249    int urb_size;
 250
 251    drm_intel_context *hw_ctx;
 252
 253    struct intel_batchbuffer batch;
 254
 255    drm_intel_bo *first_post_swapbuffers_batch;
 256    bool need_throttle;
 257    bool no_batch_wrap;
 258    bool tnl_pipeline_running; /**< Set while i915's _tnl_run_pipeline. */
 259
 260    /**
 261     * Set if we're either a debug context or the INTEL_DEBUG=perf environment
 262     * variable is set, this is the flag indicating to do expensive work that
 263     * might lead to a perf_debug() call.
 264     */
 265    bool perf_debug;
 266
 267    struct
 268    {
 269       GLuint id;
 270       uint32_t start_ptr; /**< for i8xx */
 271       uint32_t primitive;       /**< Current hardware primitive type */
 272       void (*flush) (struct intel_context *);
 273       drm_intel_bo *vb_bo;
 274       uint8_t *vb;
 275       unsigned int start_offset; /**< Byte offset of primitive sequence */
 276       unsigned int current_offset; /**< Byte offset of next vertex */
 277       unsigned int count;       /**< Number of vertices in current primitive */
 278    } prim;
 279
 280    struct {
 281       drm_intel_bo *bo;
 282       GLuint offset;
 283       uint32_t buffer_len;
 284       uint32_t buffer_offset;
 285       char buffer[4096];
 286    } upload;
 287
 288    uint32_t max_gtt_map_object_size;
 289
 290    GLuint stats_wm;
 291
 292    /* Offsets of fields within the current vertex:
 293     */
 294    GLuint coloroffset;
 295    GLuint specoffset;
 296    GLuint wpos_offset;
 297
 298    struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];
 299    GLuint vertex_attr_count;
 300
 301    bool hw_stencil;
 302    bool hw_stipple;
 303    bool no_rast;
 304    bool always_flush_batch;
 305    bool always_flush_cache;
 306    bool disable_throttling;
 307
 308    /* State for intelvb.c and inteltris.c.
 309     */
 310    GLuint RenderIndex;
 311    GLmatrix ViewportMatrix;
 312    GLenum render_primitive;
 313    GLenum reduced_primitive; /*< Only gen < 6 */
 314    GLuint vertex_size;
 315    GLubyte *verts;              /* points to tnl->clipspace.vertex_buf */
 316
 317    /* Fallback rasterization functions
 318     */
 319    intel_point_func draw_point;
 320    intel_line_func draw_line;
 321    intel_tri_func draw_tri;
 322
 323    /**
 324     * Set if rendering has occured to the drawable's front buffer.
 325     *
 326     * This is used in the DRI2 case to detect that glFlush should also copy
 327     * the contents of the fake front buffer to the real front buffer.
 328     */
 329    bool front_buffer_dirty;
 330
 331    /**
 332     * Track whether front-buffer rendering is currently enabled
 333     *
 334     * A separate flag is used to track this in order to support MRT more
 335     * easily.
 336     */
 337    bool is_front_buffer_rendering;
 338    /**
 339     * Track whether front-buffer is the current read target.
 340     *
 341     * This is closely associated with is_front_buffer_rendering, but may
 342     * be set separately.  The DRI2 fake front buffer must be referenced
 343     * either way.
 344     */
 345    bool is_front_buffer_reading;
 346
 347    bool use_early_z;
 348
 349    int driFd;
 350
 351    __DRIcontext *driContext;
 352    struct intel_screen *intelScreen;
 353    void (*saved_viewport)(struct gl_context * ctx,
 354                           GLint x, GLint y, GLsizei width, GLsizei height);
 355
 356    /**
 357     * Configuration cache
 358     */
 359    driOptionCache optionCache;
 360 };
 361
 362 #define SUBPIXEL_X 0.125
 363 #define SUBPIXEL_Y 0.125
 364
 365 /**
 366  * Align a value down to an alignment value
 367  *
 368  * If \c value is not already aligned to the requested alignment value, it
 369  * will be rounded down.
 370  *
 371  * \param value  Value to be rounded
 372  * \param alignment  Alignment value to be used.  This must be a power of two.
 373  *
 374  * \sa ALIGN()
 375  */
 376 #define ROUND_DOWN_TO(value, alignment) ((value) & ~(alignment - 1))
 377
 378 static INLINE uint32_t
 379 U_FIXED(float value, uint32_t frac_bits)
 380 {
 381    value *= (1 << frac_bits);
 382    return value < 0 ? 0 : value;
 383 }
 384
 385 static INLINE uint32_t
 386 S_FIXED(float value, uint32_t frac_bits)
 387 {
 388    return value * (1 << frac_bits);
 389 }
 390
 391 #define INTEL_FIREVERTICES(intel)               \
 392 do {                                            \
 393    if ((intel)->prim.flush)                     \
 394       (intel)->prim.flush(intel);               \
 395 } while (0)
 396
 397 /* ================================================================
 398  * From linux kernel i386 header files, copes with odd sizes better
 399  * than COPY_DWORDS would:
 400  * XXX Put this in src/mesa/main/imports.h ???
 401  */
 402 #if defined(i386) || defined(__i386__)
 403 static INLINE void * __memcpy(void * to, const void * from, size_t n)
 404 {
 405    int d0, d1, d2;
 406    __asm__ __volatile__(
 407       "rep ; movsl\n\t"
 408       "testb $2,%b4\n\t"
 409       "je 1f\n\t"
 410       "movsw\n"
 411       "1:\ttestb $1,%b4\n\t"
 412       "je 2f\n\t"
 413       "movsb\n"
 414       "2:"
 415       : "=&c" (d0), "=&D" (d1), "=&S" (d2)
 416       :"0" (n/4), "q" (n),"1" ((long) to),"2" ((long) from)
 417       : "memory");
 418    return (to);
 419 }
 420 #else
 421 #define __memcpy(a,b,c) memcpy(a,b,c)
 422 #endif
 423
 424
 425 /* ================================================================
 426  * Debugging:
 427  */
 428 extern int INTEL_DEBUG;
 429
 430 #define DEBUG_TEXTURE   0x1
 431 #define DEBUG_STATE     0x2
 432 #define DEBUG_IOCTL     0x4
 433 #define DEBUG_BLIT      0x8
 434 #define DEBUG_MIPTREE   0x10
 435 #define DEBUG_PERF      0x20
 436 #define DEBUG_BATCH     0x80
 437 #define DEBUG_PIXEL     0x100
 438 #define DEBUG_BUFMGR    0x200
 439 #define DEBUG_REGION    0x400
 440 #define DEBUG_FBO       0x800
 441 #define DEBUG_GS        0x1000
 442 #define DEBUG_SYNC      0x2000
 443 #define DEBUG_PRIMS     0x4000
 444 #define DEBUG_VERTS     0x8000
 445 #define DEBUG_DRI       0x10000
 446 #define DEBUG_SF        0x20000
 447 #define DEBUG_STATS     0x100000
 448 #define DEBUG_WM        0x400000
 449 #define DEBUG_URB       0x800000
 450 #define DEBUG_VS        0x1000000
 451 #define DEBUG_CLIP      0x2000000
 452 #define DEBUG_AUB       0x4000000
 453 #define DEBUG_SHADER_TIME 0x8000000
 454 #define DEBUG_BLORP     0x10000000
 455 #define DEBUG_NO16      0x20000000
 456
 457 #ifdef HAVE_ANDROID_PLATFORM
 458 #define LOG_TAG "INTEL-MESA"
 459 #include <cutils/log.h>
 460 #ifndef ALOGW
 461 #define ALOGW LOGW
 462 #endif
 463 #define dbg_printf(...) ALOGW(__VA_ARGS__)
 464 #else
 465 #define dbg_printf(...) printf(__VA_ARGS__)
 466 #endif /* HAVE_ANDROID_PLATFORM */
 467
 468 #define DBG(...) do {                                           \
 469         if (unlikely(INTEL_DEBUG & FILE_DEBUG_FLAG))            \
 470                 dbg_printf(__VA_ARGS__);                        \
 471 } while(0)
 472
 473 #define perf_debug(...) do {                                    \
 474    static GLuint msg_id = 0;                                    \
 475    if (unlikely(INTEL_DEBUG & DEBUG_PERF))                      \
 476       dbg_printf(__VA_ARGS__);                                  \
 477    if (intel->perf_debug)                                       \
 478       _mesa_gl_debug(&intel->ctx, &msg_id,                      \
 479                      MESA_DEBUG_TYPE_PERFORMANCE,               \
 480                      MESA_DEBUG_SEVERITY_MEDIUM,                \
 481                      __VA_ARGS__);                              \
 482 } while(0)
 483
 484 #define WARN_ONCE(cond, fmt...) do {                            \
 485    if (unlikely(cond)) {                                        \
 486       static bool _warned = false;                              \
 487       static GLuint msg_id = 0;                                 \
 488       if (!_warned) {                                           \
 489          fprintf(stderr, "WARNING: ");                          \
 490          fprintf(stderr, fmt);                                  \
 491          _warned = true;                                        \
 492                                                                 \
 493          _mesa_gl_debug(ctx, &msg_id,                           \
 494                         MESA_DEBUG_TYPE_OTHER,                  \
 495                         MESA_DEBUG_SEVERITY_HIGH, fmt);         \
 496       }                                                         \
 497    }                                                            \
 498 } while (0)
 499
 500 #define PCI_CHIP_845_G                  0x2562
 501 #define PCI_CHIP_I830_M                 0x3577
 502 #define PCI_CHIP_I855_GM                0x3582
 503 #define PCI_CHIP_I865_G                 0x2572
 504 #define PCI_CHIP_I915_G                 0x2582
 505 #define PCI_CHIP_I915_GM                0x2592
 506 #define PCI_CHIP_I945_G                 0x2772
 507 #define PCI_CHIP_I945_GM                0x27A2
 508 #define PCI_CHIP_I945_GME               0x27AE
 509 #define PCI_CHIP_G33_G                  0x29C2
 510 #define PCI_CHIP_Q35_G                  0x29B2
 511 #define PCI_CHIP_Q33_G                  0x29D2
 512
 513
 514 /* ================================================================
 515  * intel_context.c:
 516  */
 517
 518 extern bool intelInitContext(struct intel_context *intel,
 519                              int api,
 520                              unsigned major_version,
 521                              unsigned minor_version,
 522                              const struct gl_config * mesaVis,
 523                              __DRIcontext * driContextPriv,
 524                              void *sharedContextPrivate,
 525                              struct dd_function_table *functions,
 526                              unsigned *dri_ctx_error);
 527
 528 extern void intelFinish(struct gl_context * ctx);
 529 extern void intel_flush_rendering_to_batch(struct gl_context *ctx);
 530 extern void _intel_flush(struct gl_context * ctx, const char *file, int line);
 531
 532 #define intel_flush(ctx) _intel_flush(ctx, __FILE__, __LINE__)
 533
 534 extern void intelInitDriverFunctions(struct dd_function_table *functions);
 535
 536 void intel_init_syncobj_functions(struct dd_function_table *functions);
 537
 538
 539 /* ================================================================
 540  * intel_state.c:
 541  */
 542
 543 #define COMPAREFUNC_ALWAYS              0
 544 #define COMPAREFUNC_NEVER               0x1
 545 #define COMPAREFUNC_LESS                0x2
 546 #define COMPAREFUNC_EQUAL               0x3
 547 #define COMPAREFUNC_LEQUAL              0x4
 548 #define COMPAREFUNC_GREATER             0x5
 549 #define COMPAREFUNC_NOTEQUAL            0x6
 550 #define COMPAREFUNC_GEQUAL              0x7
 551
 552 #define STENCILOP_KEEP                  0
 553 #define STENCILOP_ZERO                  0x1
 554 #define STENCILOP_REPLACE               0x2
 555 #define STENCILOP_INCRSAT               0x3
 556 #define STENCILOP_DECRSAT               0x4
 557 #define STENCILOP_INCR                  0x5
 558 #define STENCILOP_DECR                  0x6
 559 #define STENCILOP_INVERT                0x7
 560
 561 #define LOGICOP_CLEAR                   0
 562 #define LOGICOP_NOR                     0x1
 563 #define LOGICOP_AND_INV                 0x2
 564 #define LOGICOP_COPY_INV                0x3
 565 #define LOGICOP_AND_RVRSE               0x4
 566 #define LOGICOP_INV                     0x5
 567 #define LOGICOP_XOR                     0x6
 568 #define LOGICOP_NAND                    0x7
 569 #define LOGICOP_AND                     0x8
 570 #define LOGICOP_EQUIV                   0x9
 571 #define LOGICOP_NOOP                    0xa
 572 #define LOGICOP_OR_INV                  0xb
 573 #define LOGICOP_COPY                    0xc
 574 #define LOGICOP_OR_RVRSE                0xd
 575 #define LOGICOP_OR                      0xe
 576 #define LOGICOP_SET                     0xf
 577
 578 #define BLENDFACT_ZERO                  0x01
 579 #define BLENDFACT_ONE                   0x02
 580 #define BLENDFACT_SRC_COLR              0x03
 581 #define BLENDFACT_INV_SRC_COLR          0x04
 582 #define BLENDFACT_SRC_ALPHA             0x05
 583 #define BLENDFACT_INV_SRC_ALPHA         0x06
 584 #define BLENDFACT_DST_ALPHA             0x07
 585 #define BLENDFACT_INV_DST_ALPHA         0x08
 586 #define BLENDFACT_DST_COLR              0x09
 587 #define BLENDFACT_INV_DST_COLR          0x0a
 588 #define BLENDFACT_SRC_ALPHA_SATURATE    0x0b
 589 #define BLENDFACT_CONST_COLOR           0x0c
 590 #define BLENDFACT_INV_CONST_COLOR       0x0d
 591 #define BLENDFACT_CONST_ALPHA           0x0e
 592 #define BLENDFACT_INV_CONST_ALPHA       0x0f
 593 #define BLENDFACT_MASK                  0x0f
 594
 595 enum {
 596    DRI_CONF_BO_REUSE_DISABLED,
 597    DRI_CONF_BO_REUSE_ALL
 598 };
 599
 600 extern int intel_translate_shadow_compare_func(GLenum func);
 601 extern int intel_translate_compare_func(GLenum func);
 602 extern int intel_translate_stencil_op(GLenum op);
 603 extern int intel_translate_blend_factor(GLenum factor);
 604 extern int intel_translate_logic_op(GLenum opcode);
 605
 606 void intel_update_renderbuffers(__DRIcontext *context,
 607                                 __DRIdrawable *drawable);
 608 void intel_prepare_render(struct intel_context *intel);
 609
 610 void
 611 intel_resolve_for_dri2_flush(struct intel_context *intel,
 612                              __DRIdrawable *drawable);
 613
 614 void i915_set_buf_info_for_region(uint32_t *state, struct intel_region *region,
 615                                   uint32_t buffer_id);
 616 void intel_init_texture_formats(struct gl_context *ctx);
 617
 618 /*======================================================================
 619  * Inline conversion functions.
 620  * These are better-typed than the macros used previously:
 621  */
 622 static INLINE struct intel_context *
 623 intel_context(struct gl_context * ctx)
 624 {
 625    return (struct intel_context *) ctx;
 626 }
 627
 628 static INLINE bool
 629 is_power_of_two(uint32_t value)
 630 {
 631    return (value & (value - 1)) == 0;
 632 }
 633
 634 #ifdef __cplusplus
 635 }
 636 #endif
 637
 638 #endif