i965: Move intel_context::batch to brw_context.
[mesa.git] / src / mesa / drivers / dri / i965 / intel_context.h
1 /**************************************************************************
2 *
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #ifndef INTELCONTEXT_INC
29 #define INTELCONTEXT_INC
30
31
32 #include <stdbool.h>
33 #include <string.h>
34 #include "main/mtypes.h"
35 #include "main/mm.h"
36
37 #ifdef __cplusplus
38 extern "C" {
39 /* Evil hack for using libdrm in a c++ compiler. */
40 #define virtual virt
41 #endif
42
43 #include "drm.h"
44 #include "intel_bufmgr.h"
45
46 #include "intel_screen.h"
47 #include "intel_tex_obj.h"
48 #include "i915_drm.h"
49
50 #ifdef __cplusplus
51 #undef virtual
52 #endif
53
54 #include "tnl/t_vertex.h"
55
56 struct intel_region;
57 struct intel_context;
58
59 #define INTEL_WRITE_PART 0x1
60 #define INTEL_WRITE_FULL 0x2
61 #define INTEL_READ 0x4
62
63 #ifndef likely
64 #ifdef __GNUC__
65 #define likely(expr) (__builtin_expect(expr, 1))
66 #define unlikely(expr) (__builtin_expect(expr, 0))
67 #else
68 #define likely(expr) (expr)
69 #define unlikely(expr) (expr)
70 #endif
71 #endif
72
73 struct intel_sync_object {
74 struct gl_sync_object Base;
75
76 /** Batch associated with this sync object */
77 drm_intel_bo *bo;
78 };
79
80 struct brw_context;
81
82 struct intel_batchbuffer {
83 /** Current batchbuffer being queued up. */
84 drm_intel_bo *bo;
85 /** Last BO submitted to the hardware. Used for glFinish(). */
86 drm_intel_bo *last_bo;
87 /** BO for post-sync nonzero writes for gen6 workaround. */
88 drm_intel_bo *workaround_bo;
89 bool need_workaround_flush;
90
91 struct cached_batch_item *cached_items;
92
93 uint16_t emit, total;
94 uint16_t used, reserved_space;
95 uint32_t *map;
96 uint32_t *cpu_map;
97 #define BATCH_SZ (8192*sizeof(uint32_t))
98
99 uint32_t state_batch_offset;
100 bool is_blit;
101 bool needs_sol_reset;
102
103 struct {
104 uint16_t used;
105 int reloc_count;
106 } saved;
107 };
108
109 /**
110 * intel_context is derived from Mesa's context class: struct gl_context.
111 */
112 struct intel_context
113 {
114 struct gl_context ctx; /**< base class, must be first field */
115
116 GLuint NewGLState;
117
118 /**
119 * Generation number of the hardware: 2 is 8xx, 3 is 9xx pre-965, 4 is 965.
120 */
121 int gen;
122 int gt;
123 bool is_haswell;
124 bool is_baytrail;
125 bool is_g4x;
126 bool has_separate_stencil;
127 bool must_use_separate_stencil;
128 bool has_hiz;
129 bool has_llc;
130 bool has_swizzling;
131
132 drm_intel_bo *first_post_swapbuffers_batch;
133 bool need_throttle;
134 bool no_batch_wrap;
135
136 /**
137 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
138 * variable is set, this is the flag indicating to do expensive work that
139 * might lead to a perf_debug() call.
140 */
141 bool perf_debug;
142
143 struct {
144 drm_intel_bo *bo;
145 GLuint offset;
146 uint32_t buffer_len;
147 uint32_t buffer_offset;
148 char buffer[4096];
149 } upload;
150
151 uint32_t max_gtt_map_object_size;
152
153 GLuint stats_wm;
154
155 int driFd;
156
157 __DRIcontext *driContext;
158 struct intel_screen *intelScreen;
159 };
160
161 /**
162 * Align a value down to an alignment value
163 *
164 * If \c value is not already aligned to the requested alignment value, it
165 * will be rounded down.
166 *
167 * \param value Value to be rounded
168 * \param alignment Alignment value to be used. This must be a power of two.
169 *
170 * \sa ALIGN()
171 */
172 #define ROUND_DOWN_TO(value, alignment) ((value) & ~(alignment - 1))
173
174 static INLINE uint32_t
175 U_FIXED(float value, uint32_t frac_bits)
176 {
177 value *= (1 << frac_bits);
178 return value < 0 ? 0 : value;
179 }
180
181 static INLINE uint32_t
182 S_FIXED(float value, uint32_t frac_bits)
183 {
184 return value * (1 << frac_bits);
185 }
186
187 /* ================================================================
188 * From linux kernel i386 header files, copes with odd sizes better
189 * than COPY_DWORDS would:
190 * XXX Put this in src/mesa/main/imports.h ???
191 */
192 #if defined(i386) || defined(__i386__)
193 static INLINE void * __memcpy(void * to, const void * from, size_t n)
194 {
195 int d0, d1, d2;
196 __asm__ __volatile__(
197 "rep ; movsl\n\t"
198 "testb $2,%b4\n\t"
199 "je 1f\n\t"
200 "movsw\n"
201 "1:\ttestb $1,%b4\n\t"
202 "je 2f\n\t"
203 "movsb\n"
204 "2:"
205 : "=&c" (d0), "=&D" (d1), "=&S" (d2)
206 :"0" (n/4), "q" (n),"1" ((long) to),"2" ((long) from)
207 : "memory");
208 return (to);
209 }
210 #else
211 #define __memcpy(a,b,c) memcpy(a,b,c)
212 #endif
213
214
215 /* ================================================================
216 * Debugging:
217 */
218 extern int INTEL_DEBUG;
219
220 #define DEBUG_TEXTURE 0x1
221 #define DEBUG_STATE 0x2
222 #define DEBUG_IOCTL 0x4
223 #define DEBUG_BLIT 0x8
224 #define DEBUG_MIPTREE 0x10
225 #define DEBUG_PERF 0x20
226 #define DEBUG_BATCH 0x80
227 #define DEBUG_PIXEL 0x100
228 #define DEBUG_BUFMGR 0x200
229 #define DEBUG_REGION 0x400
230 #define DEBUG_FBO 0x800
231 #define DEBUG_GS 0x1000
232 #define DEBUG_SYNC 0x2000
233 #define DEBUG_PRIMS 0x4000
234 #define DEBUG_VERTS 0x8000
235 #define DEBUG_DRI 0x10000
236 #define DEBUG_SF 0x20000
237 #define DEBUG_STATS 0x100000
238 #define DEBUG_WM 0x400000
239 #define DEBUG_URB 0x800000
240 #define DEBUG_VS 0x1000000
241 #define DEBUG_CLIP 0x2000000
242 #define DEBUG_AUB 0x4000000
243 #define DEBUG_SHADER_TIME 0x8000000
244 #define DEBUG_BLORP 0x10000000
245 #define DEBUG_NO16 0x20000000
246
247 #ifdef HAVE_ANDROID_PLATFORM
248 #define LOG_TAG "INTEL-MESA"
249 #include <cutils/log.h>
250 #ifndef ALOGW
251 #define ALOGW LOGW
252 #endif
253 #define dbg_printf(...) ALOGW(__VA_ARGS__)
254 #else
255 #define dbg_printf(...) printf(__VA_ARGS__)
256 #endif /* HAVE_ANDROID_PLATFORM */
257
258 #define DBG(...) do { \
259 if (unlikely(INTEL_DEBUG & FILE_DEBUG_FLAG)) \
260 dbg_printf(__VA_ARGS__); \
261 } while(0)
262
263 #define perf_debug(...) do { \
264 static GLuint msg_id = 0; \
265 if (unlikely(INTEL_DEBUG & DEBUG_PERF)) \
266 dbg_printf(__VA_ARGS__); \
267 if (intel->perf_debug) \
268 _mesa_gl_debug(&intel->ctx, &msg_id, \
269 MESA_DEBUG_TYPE_PERFORMANCE, \
270 MESA_DEBUG_SEVERITY_MEDIUM, \
271 __VA_ARGS__); \
272 } while(0)
273
274 #define WARN_ONCE(cond, fmt...) do { \
275 if (unlikely(cond)) { \
276 static bool _warned = false; \
277 static GLuint msg_id = 0; \
278 if (!_warned) { \
279 fprintf(stderr, "WARNING: "); \
280 fprintf(stderr, fmt); \
281 _warned = true; \
282 \
283 _mesa_gl_debug(ctx, &msg_id, \
284 MESA_DEBUG_TYPE_OTHER, \
285 MESA_DEBUG_SEVERITY_HIGH, fmt); \
286 } \
287 } \
288 } while (0)
289
290 /* ================================================================
291 * intel_context.c:
292 */
293
294 extern bool intelInitContext(struct brw_context *brw,
295 int api,
296 unsigned major_version,
297 unsigned minor_version,
298 const struct gl_config * mesaVis,
299 __DRIcontext * driContextPriv,
300 void *sharedContextPrivate,
301 struct dd_function_table *functions,
302 unsigned *dri_ctx_error);
303
304 extern void intelFinish(struct gl_context * ctx);
305 extern void _intel_flush(struct gl_context * ctx, const char *file, int line);
306
307 #define intel_flush(ctx) _intel_flush(ctx, __FILE__, __LINE__)
308
309 extern void intelInitDriverFunctions(struct dd_function_table *functions);
310
311 void intel_init_syncobj_functions(struct dd_function_table *functions);
312
313 enum {
314 DRI_CONF_BO_REUSE_DISABLED,
315 DRI_CONF_BO_REUSE_ALL
316 };
317
318 extern int intel_translate_shadow_compare_func(GLenum func);
319 extern int intel_translate_compare_func(GLenum func);
320 extern int intel_translate_stencil_op(GLenum op);
321 extern int intel_translate_logic_op(GLenum opcode);
322
323 void intel_update_renderbuffers(__DRIcontext *context,
324 __DRIdrawable *drawable);
325 void intel_prepare_render(struct brw_context *brw);
326
327 void
328 intel_resolve_for_dri2_flush(struct brw_context *brw,
329 __DRIdrawable *drawable);
330
331 extern void
332 intelInitExtensions(struct gl_context *ctx);
333 extern void
334 intelInitClearFuncs(struct dd_function_table *functions);
335
336 /*======================================================================
337 * Inline conversion functions.
338 * These are better-typed than the macros used previously:
339 */
340 static INLINE struct intel_context *
341 intel_context(struct gl_context * ctx)
342 {
343 return (struct intel_context *) ctx;
344 }
345
346 static INLINE bool
347 is_power_of_two(uint32_t value)
348 {
349 return (value & (value - 1)) == 0;
350 }
351
352 #ifdef __cplusplus
353 }
354 #endif
355
356 #endif