i965: Calculate thread_count in brw_alloc_stage_scratch
[mesa.git] / src / mesa / drivers / dri / i965 / intel_copy_image.c
1 /*
2 * Mesa 3-D graphics library
3 *
4 * Copyright (C) 2014 Intel Corporation All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Jason Ekstrand <jason.ekstrand@intel.com>
26 */
27
28 #include "brw_blorp.h"
29 #include "intel_fbo.h"
30 #include "intel_tex.h"
31 #include "intel_blit.h"
32 #include "intel_mipmap_tree.h"
33 #include "main/formats.h"
34 #include "main/teximage.h"
35 #include "drivers/common/meta.h"
36
37 static void
38 copy_miptrees(struct brw_context *brw,
39 struct intel_mipmap_tree *src_mt,
40 int src_x, int src_y, int src_z, unsigned src_level,
41 struct intel_mipmap_tree *dst_mt,
42 int dst_x, int dst_y, int dst_z, unsigned dst_level,
43 int src_width, int src_height)
44 {
45 const struct gen_device_info *devinfo = &brw->screen->devinfo;
46
47 if (devinfo->gen <= 5) {
48 /* On gen4-5, try BLT first.
49 *
50 * Gen4-5 have a single ring for both 3D and BLT operations, so there's
51 * no inter-ring synchronization issues like on Gen6+. It is apparently
52 * faster than using the 3D pipeline. Original Gen4 also has to rebase
53 * and copy miptree slices in order to render to unaligned locations.
54 */
55 if (intel_miptree_copy(brw, src_mt, src_level, src_z, src_x, src_y,
56 dst_mt, dst_level, dst_z, dst_x, dst_y,
57 src_width, src_height))
58 return;
59 }
60
61 brw_blorp_copy_miptrees(brw,
62 src_mt, src_level, src_z,
63 dst_mt, dst_level, dst_z,
64 src_x, src_y, dst_x, dst_y,
65 src_width, src_height);
66 }
67
68 static void
69 intel_copy_image_sub_data(struct gl_context *ctx,
70 struct gl_texture_image *src_image,
71 struct gl_renderbuffer *src_renderbuffer,
72 int src_x, int src_y, int src_z,
73 struct gl_texture_image *dst_image,
74 struct gl_renderbuffer *dst_renderbuffer,
75 int dst_x, int dst_y, int dst_z,
76 int src_width, int src_height)
77 {
78 struct brw_context *brw = brw_context(ctx);
79 struct intel_mipmap_tree *src_mt, *dst_mt;
80 unsigned src_level, dst_level;
81
82 if (src_image) {
83 src_mt = intel_texture_image(src_image)->mt;
84 src_level = src_image->Level + src_image->TexObject->MinLevel;
85
86 /* Cube maps actually have different images per face */
87 if (src_image->TexObject->Target == GL_TEXTURE_CUBE_MAP)
88 src_z = src_image->Face;
89
90 src_z += src_image->TexObject->MinLayer;
91 } else {
92 assert(src_renderbuffer);
93 src_mt = intel_renderbuffer(src_renderbuffer)->mt;
94 src_image = src_renderbuffer->TexImage;
95 src_level = 0;
96 }
97
98 if (dst_image) {
99 dst_mt = intel_texture_image(dst_image)->mt;
100
101 dst_level = dst_image->Level + dst_image->TexObject->MinLevel;
102
103 /* Cube maps actually have different images per face */
104 if (dst_image->TexObject->Target == GL_TEXTURE_CUBE_MAP)
105 dst_z = dst_image->Face;
106
107 dst_z += dst_image->TexObject->MinLayer;
108 } else {
109 assert(dst_renderbuffer);
110 dst_mt = intel_renderbuffer(dst_renderbuffer)->mt;
111 dst_image = dst_renderbuffer->TexImage;
112 dst_level = 0;
113 }
114
115 copy_miptrees(brw, src_mt, src_x, src_y, src_z, src_level,
116 dst_mt, dst_x, dst_y, dst_z, dst_level,
117 src_width, src_height);
118
119 /* CopyImage only works for equal formats, texture view equivalence
120 * classes, and a couple special cases for compressed textures.
121 *
122 * Notably, GL_DEPTH_STENCIL does not appear in any equivalence
123 * classes, so we know the formats must be the same, and thus both
124 * will either have stencil, or not. They can't be mismatched.
125 */
126 assert((src_mt->stencil_mt != NULL) == (dst_mt->stencil_mt != NULL));
127
128 if (dst_mt->stencil_mt) {
129 copy_miptrees(brw, src_mt->stencil_mt, src_x, src_y, src_z, src_level,
130 dst_mt->stencil_mt, dst_x, dst_y, dst_z, dst_level,
131 src_width, src_height);
132 }
133 }
134
135 void
136 intelInitCopyImageFuncs(struct dd_function_table *functions)
137 {
138 functions->CopyImageSubData = intel_copy_image_sub_data;
139 }