src/mesa/drivers/dri/i965/intel_extensions.c

   1 /*
   2  * Copyright 2003 VMware, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include "main/version.h"
  27
  28 #include "brw_context.h"
  29 #include "brw_defines.h"
  30 #include "intel_batchbuffer.h"
  31
  32 /**
  33  * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
  34  *
  35  * Some combinations of hardware and kernel versions allow this feature,
  36  * while others don't.  Instead of trying to enumerate every case, just
  37  * try and write a register and see if works.
  38  */
  39 static bool
  40 can_do_pipelined_register_writes(struct brw_context *brw)
  41 {
  42    /**
  43     * gen >= 8 specifically allows these writes. gen <= 6 also
  44     * doesn't block them.
  45     */
  46    if (brw->gen != 7)
  47       return true;
  48
  49    static int result = -1;
  50    if (result != -1)
  51       return result;
  52
  53    /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
  54     * statistics registers), and we already reset it to zero before using it.
  55     */
  56    const int reg = GEN7_SO_WRITE_OFFSET(0);
  57    const int expected_value = 0x1337d0d0;
  58    const int offset = 100;
  59
  60    /* The register we picked only exists on Gen7+. */
  61    assert(brw->gen == 7);
  62
  63    uint32_t *data;
  64    /* Set a value in a BO to a known quantity.  The workaround BO already
  65     * exists and doesn't contain anything important, so we may as well use it.
  66     */
  67    drm_intel_bo_map(brw->workaround_bo, true);
  68    data = brw->workaround_bo->virtual;
  69    data[offset] = 0xffffffff;
  70    drm_intel_bo_unmap(brw->workaround_bo);
  71
  72    /* Write the register. */
  73    BEGIN_BATCH(3);
  74    OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
  75    OUT_BATCH(reg);
  76    OUT_BATCH(expected_value);
  77    ADVANCE_BATCH();
  78
  79    brw_emit_mi_flush(brw);
  80
  81    /* Save the register's value back to the buffer. */
  82    BEGIN_BATCH(3);
  83    OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
  84    OUT_BATCH(reg);
  85    OUT_RELOC(brw->workaround_bo,
  86              I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
  87              offset * sizeof(uint32_t));
  88    ADVANCE_BATCH();
  89
  90    intel_batchbuffer_flush(brw);
  91
  92    /* Check whether the value got written. */
  93    drm_intel_bo_map(brw->workaround_bo, false);
  94    data = brw->workaround_bo->virtual;
  95    bool success = data[offset] == expected_value;
  96    drm_intel_bo_unmap(brw->workaround_bo);
  97
  98    result = success;
  99
 100    return success;
 101 }
 102
 103 static bool
 104 can_write_oacontrol(struct brw_context *brw)
 105 {
 106    if (brw->gen < 6 || brw->gen >= 8)
 107       return false;
 108
 109    static int result = -1;
 110    if (result != -1)
 111       return result;
 112
 113    /* Set "Select Context ID" to a particular address (which is likely not a
 114     * context), but leave all counting disabled.  This should be harmless.
 115     */
 116    const int expected_value = 0x31337000;
 117    const int offset = 110;
 118
 119    uint32_t *data;
 120    /* Set a value in a BO to a known quantity.  The workaround BO already
 121     * exists and doesn't contain anything important, so we may as well use it.
 122     */
 123    drm_intel_bo_map(brw->workaround_bo, true);
 124    data = brw->workaround_bo->virtual;
 125    data[offset] = 0xffffffff;
 126    drm_intel_bo_unmap(brw->workaround_bo);
 127
 128    /* Write OACONTROL. */
 129    BEGIN_BATCH(3);
 130    OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
 131    OUT_BATCH(OACONTROL);
 132    OUT_BATCH(expected_value);
 133    ADVANCE_BATCH();
 134
 135    brw_emit_mi_flush(brw);
 136
 137    /* Save the register's value back to the buffer. */
 138    BEGIN_BATCH(3);
 139    OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
 140    OUT_BATCH(OACONTROL);
 141    OUT_RELOC(brw->workaround_bo,
 142              I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 143              offset * sizeof(uint32_t));
 144    ADVANCE_BATCH();
 145
 146    brw_emit_mi_flush(brw);
 147
 148    /* Set OACONTROL back to zero (everything off). */
 149    BEGIN_BATCH(3);
 150    OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
 151    OUT_BATCH(OACONTROL);
 152    OUT_BATCH(0);
 153    ADVANCE_BATCH();
 154
 155    intel_batchbuffer_flush(brw);
 156
 157    /* Check whether the value got written. */
 158    drm_intel_bo_map(brw->workaround_bo, false);
 159    data = brw->workaround_bo->virtual;
 160    bool success = data[offset] == expected_value;
 161    drm_intel_bo_unmap(brw->workaround_bo);
 162
 163    result = success;
 164
 165    return success;
 166 }
 167
 168 /**
 169  * Initializes potential list of extensions if ctx == NULL, or actually enables
 170  * extensions for a context.
 171  */
 172 void
 173 intelInitExtensions(struct gl_context *ctx)
 174 {
 175    struct brw_context *brw = brw_context(ctx);
 176
 177    assert(brw->gen >= 4);
 178
 179    ctx->Extensions.ARB_arrays_of_arrays = true;
 180    ctx->Extensions.ARB_buffer_storage = true;
 181    ctx->Extensions.ARB_clear_texture = true;
 182    ctx->Extensions.ARB_clip_control = true;
 183    ctx->Extensions.ARB_copy_image = true;
 184    ctx->Extensions.ARB_depth_buffer_float = true;
 185    ctx->Extensions.ARB_depth_clamp = true;
 186    ctx->Extensions.ARB_depth_texture = true;
 187    ctx->Extensions.ARB_draw_elements_base_vertex = true;
 188    ctx->Extensions.ARB_draw_instanced = true;
 189    ctx->Extensions.ARB_ES2_compatibility = true;
 190    ctx->Extensions.ARB_explicit_attrib_location = true;
 191    ctx->Extensions.ARB_explicit_uniform_location = true;
 192    ctx->Extensions.ARB_fragment_coord_conventions = true;
 193    ctx->Extensions.ARB_fragment_program = true;
 194    ctx->Extensions.ARB_fragment_program_shadow = true;
 195    ctx->Extensions.ARB_fragment_shader = true;
 196    ctx->Extensions.ARB_framebuffer_object = true;
 197    ctx->Extensions.ARB_half_float_vertex = true;
 198    ctx->Extensions.ARB_instanced_arrays = true;
 199    ctx->Extensions.ARB_internalformat_query = true;
 200    ctx->Extensions.ARB_internalformat_query2 = true;
 201    ctx->Extensions.ARB_map_buffer_range = true;
 202    ctx->Extensions.ARB_occlusion_query = true;
 203    ctx->Extensions.ARB_occlusion_query2 = true;
 204    ctx->Extensions.ARB_pipeline_statistics_query = true;
 205    ctx->Extensions.ARB_point_sprite = true;
 206    ctx->Extensions.ARB_seamless_cube_map = true;
 207    ctx->Extensions.ARB_shader_bit_encoding = true;
 208    ctx->Extensions.ARB_shader_draw_parameters = true;
 209    ctx->Extensions.ARB_shader_texture_lod = true;
 210    ctx->Extensions.ARB_shading_language_packing = true;
 211    ctx->Extensions.ARB_shadow = true;
 212    ctx->Extensions.ARB_sync = true;
 213    ctx->Extensions.ARB_texture_border_clamp = true;
 214    ctx->Extensions.ARB_texture_compression_rgtc = true;
 215    ctx->Extensions.ARB_texture_cube_map = true;
 216    ctx->Extensions.ARB_texture_env_combine = true;
 217    ctx->Extensions.ARB_texture_env_crossbar = true;
 218    ctx->Extensions.ARB_texture_env_dot3 = true;
 219    ctx->Extensions.ARB_texture_float = true;
 220    ctx->Extensions.ARB_texture_mirror_clamp_to_edge = true;
 221    ctx->Extensions.ARB_texture_non_power_of_two = true;
 222    ctx->Extensions.ARB_texture_rg = true;
 223    ctx->Extensions.ARB_texture_rgb10_a2ui = true;
 224    ctx->Extensions.ARB_vertex_program = true;
 225    ctx->Extensions.ARB_vertex_shader = true;
 226    ctx->Extensions.ARB_vertex_type_2_10_10_10_rev = true;
 227    ctx->Extensions.ARB_vertex_type_10f_11f_11f_rev = true;
 228    ctx->Extensions.EXT_blend_color = true;
 229    ctx->Extensions.EXT_blend_equation_separate = true;
 230    ctx->Extensions.EXT_blend_func_separate = true;
 231    ctx->Extensions.EXT_blend_minmax = true;
 232    ctx->Extensions.EXT_draw_buffers2 = true;
 233    ctx->Extensions.EXT_framebuffer_sRGB = true;
 234    ctx->Extensions.EXT_gpu_program_parameters = true;
 235    ctx->Extensions.EXT_packed_float = true;
 236    ctx->Extensions.EXT_pixel_buffer_object = true;
 237    ctx->Extensions.EXT_point_parameters = true;
 238    ctx->Extensions.EXT_polygon_offset_clamp = true;
 239    ctx->Extensions.EXT_provoking_vertex = true;
 240    ctx->Extensions.EXT_stencil_two_side = true;
 241    ctx->Extensions.EXT_texture_array = true;
 242    ctx->Extensions.EXT_texture_env_dot3 = true;
 243    ctx->Extensions.EXT_texture_filter_anisotropic = true;
 244    ctx->Extensions.EXT_texture_integer = true;
 245    ctx->Extensions.EXT_texture_shared_exponent = true;
 246    ctx->Extensions.EXT_texture_snorm = true;
 247    ctx->Extensions.EXT_texture_sRGB = true;
 248    ctx->Extensions.EXT_texture_sRGB_decode = true;
 249    ctx->Extensions.EXT_texture_swizzle = true;
 250    ctx->Extensions.EXT_vertex_array_bgra = true;
 251    ctx->Extensions.KHR_robustness = true;
 252    ctx->Extensions.AMD_seamless_cubemap_per_texture = true;
 253    ctx->Extensions.APPLE_object_purgeable = true;
 254    ctx->Extensions.ATI_separate_stencil = true;
 255    ctx->Extensions.ATI_texture_env_combine3 = true;
 256    ctx->Extensions.MESA_pack_invert = true;
 257    ctx->Extensions.NV_conditional_render = true;
 258    ctx->Extensions.NV_primitive_restart = true;
 259    ctx->Extensions.NV_texture_barrier = true;
 260    ctx->Extensions.NV_texture_env_combine4 = true;
 261    ctx->Extensions.NV_texture_rectangle = true;
 262    ctx->Extensions.TDFX_texture_compression_FXT1 = true;
 263    ctx->Extensions.OES_compressed_ETC1_RGB8_texture = true;
 264    ctx->Extensions.OES_draw_texture = true;
 265    ctx->Extensions.OES_EGL_image = true;
 266    ctx->Extensions.OES_EGL_image_external = true;
 267    ctx->Extensions.OES_standard_derivatives = true;
 268    ctx->Extensions.OES_texture_float = true;
 269    ctx->Extensions.OES_texture_float_linear = true;
 270    ctx->Extensions.OES_texture_half_float = true;
 271    ctx->Extensions.OES_texture_half_float_linear = true;
 272
 273    if (brw->gen >= 8)
 274       ctx->Const.GLSLVersion = 440;
 275    else if (brw->gen >= 6)
 276       ctx->Const.GLSLVersion = 330;
 277    else
 278       ctx->Const.GLSLVersion = 120;
 279    _mesa_override_glsl_version(&ctx->Const);
 280
 281    ctx->Extensions.EXT_shader_integer_mix = ctx->Const.GLSLVersion >= 130;
 282    ctx->Extensions.MESA_shader_integer_functions = ctx->Const.GLSLVersion >= 130;
 283
 284    if ((brw->is_g4x || brw->gen >= 5) && brw->gen < 9)
 285       ctx->Extensions.MESA_shader_framebuffer_fetch_non_coherent = true;
 286
 287    if (brw->gen >= 5) {
 288       ctx->Extensions.ARB_texture_query_levels = ctx->Const.GLSLVersion >= 130;
 289       ctx->Extensions.ARB_texture_query_lod = true;
 290       ctx->Extensions.EXT_timer_query = true;
 291
 292       if (brw->gen == 5 || can_write_oacontrol(brw)) {
 293          ctx->Extensions.AMD_performance_monitor = true;
 294          ctx->Extensions.INTEL_performance_query = true;
 295       }
 296    }
 297
 298    if (brw->gen >= 6) {
 299       ctx->Extensions.ARB_blend_func_extended =
 300          !driQueryOptionb(&brw->optionCache, "disable_blend_func_extended");
 301       ctx->Extensions.ARB_conditional_render_inverted = true;
 302       ctx->Extensions.ARB_cull_distance = true;
 303       ctx->Extensions.ARB_draw_buffers_blend = true;
 304       ctx->Extensions.ARB_enhanced_layouts = true;
 305       ctx->Extensions.ARB_ES3_compatibility = true;
 306       ctx->Extensions.ARB_fragment_layer_viewport = true;
 307       ctx->Extensions.ARB_sample_shading = true;
 308       ctx->Extensions.ARB_shading_language_420pack = true;
 309       ctx->Extensions.ARB_texture_buffer_object = true;
 310       ctx->Extensions.ARB_texture_buffer_object_rgb32 = true;
 311       ctx->Extensions.ARB_texture_buffer_range = true;
 312       ctx->Extensions.ARB_texture_cube_map_array = true;
 313       ctx->Extensions.ARB_texture_gather = true;
 314       ctx->Extensions.ARB_texture_multisample = true;
 315       ctx->Extensions.ARB_uniform_buffer_object = true;
 316
 317       ctx->Extensions.AMD_vertex_shader_layer = true;
 318       ctx->Extensions.EXT_framebuffer_multisample = true;
 319       ctx->Extensions.EXT_framebuffer_multisample_blit_scaled = true;
 320       ctx->Extensions.EXT_transform_feedback = true;
 321       ctx->Extensions.OES_depth_texture_cube_map = true;
 322       ctx->Extensions.OES_sample_variables = true;
 323
 324       ctx->Extensions.ARB_timer_query = brw->intelScreen->hw_has_timestamp;
 325
 326       /* Only enable this in core profile because other parts of Mesa behave
 327        * slightly differently when the extension is enabled.
 328        */
 329       if (ctx->API == API_OPENGL_CORE) {
 330          ctx->Extensions.ARB_shader_subroutine = true;
 331          ctx->Extensions.ARB_viewport_array = true;
 332          ctx->Extensions.AMD_vertex_shader_viewport_index = true;
 333       }
 334    }
 335
 336    brw->predicate.supported = false;
 337    brw->can_do_pipelined_register_writes =
 338       can_do_pipelined_register_writes(brw);
 339
 340    if (brw->gen >= 7) {
 341       ctx->Extensions.ARB_conservative_depth = true;
 342       ctx->Extensions.ARB_derivative_control = true;
 343       ctx->Extensions.ARB_framebuffer_no_attachments = true;
 344       ctx->Extensions.ARB_gpu_shader5 = true;
 345       ctx->Extensions.ARB_shader_atomic_counters = true;
 346       ctx->Extensions.ARB_shader_clock = true;
 347       ctx->Extensions.ARB_shader_image_load_store = true;
 348       ctx->Extensions.ARB_shader_image_size = true;
 349       ctx->Extensions.ARB_shader_texture_image_samples = true;
 350       ctx->Extensions.ARB_tessellation_shader = true;
 351       ctx->Extensions.ARB_texture_compression_bptc = true;
 352       ctx->Extensions.ARB_texture_view = true;
 353       ctx->Extensions.ARB_shader_storage_buffer_object = true;
 354       ctx->Extensions.EXT_shader_samples_identical = true;
 355       ctx->Extensions.OES_texture_buffer = true;
 356
 357       if (brw->can_do_pipelined_register_writes) {
 358          ctx->Extensions.ARB_draw_indirect = true;
 359          ctx->Extensions.ARB_transform_feedback2 = true;
 360          ctx->Extensions.ARB_transform_feedback3 = true;
 361          ctx->Extensions.ARB_transform_feedback_instanced = true;
 362
 363          if ((brw->gen >= 8 || brw->intelScreen->cmd_parser_version >= 5) &&
 364              ctx->Const.MaxComputeWorkGroupSize[0] >= 1024) {
 365             ctx->Extensions.ARB_compute_shader = true;
 366             ctx->Extensions.ARB_ES3_1_compatibility = brw->gen >= 8;
 367          }
 368
 369          if (brw->intelScreen->cmd_parser_version >= 2)
 370             brw->predicate.supported = true;
 371       }
 372    }
 373
 374    if (brw->gen >= 8 || brw->is_haswell || brw->is_baytrail) {
 375       ctx->Extensions.ARB_robust_buffer_access_behavior = true;
 376    }
 377
 378    if (brw->intelScreen->has_mi_math_and_lrr) {
 379       ctx->Extensions.ARB_query_buffer_object = true;
 380    }
 381
 382    if (brw->gen >= 8 || brw->is_baytrail) {
 383       /* For now, we only enable OES_copy_image on platforms that support
 384        * ETC2 natively in hardware.  We would need more hacks to support it
 385        * elsewhere.
 386        */
 387       ctx->Extensions.OES_copy_image = true;
 388    }
 389
 390    if (brw->gen >= 8) {
 391       ctx->Extensions.ARB_shader_precision = true;
 392       ctx->Extensions.ARB_stencil_texturing = true;
 393       ctx->Extensions.ARB_texture_stencil8 = true;
 394       ctx->Extensions.ARB_gpu_shader_fp64 = true;
 395       ctx->Extensions.ARB_vertex_attrib_64bit = true;
 396       ctx->Extensions.OES_shader_io_blocks = true;
 397    }
 398
 399    if (brw->gen >= 9) {
 400       ctx->Extensions.KHR_texture_compression_astc_ldr = true;
 401       ctx->Extensions.KHR_texture_compression_astc_sliced_3d = true;
 402       ctx->Extensions.ARB_shader_stencil_export = true;
 403    }
 404
 405    if (ctx->API == API_OPENGL_CORE)
 406       ctx->Extensions.ARB_base_instance = true;
 407    if (ctx->API != API_OPENGL_CORE)
 408       ctx->Extensions.ARB_color_buffer_float = true;
 409
 410    if (ctx->Mesa_DXTn || driQueryOptionb(&brw->optionCache, "force_s3tc_enable"))
 411       ctx->Extensions.EXT_texture_compression_s3tc = true;
 412
 413    ctx->Extensions.ANGLE_texture_compression_dxt = true;
 414 }