src/mesa/drivers/dri/i965/intel_extensions.c

   1 /*
   2  * Copyright 2003 VMware, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  20  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include "main/version.h"
  27
  28 #include "brw_context.h"
  29 #include "intel_batchbuffer.h"
  30 #include "intel_reg.h"
  31 #include "utils.h"
  32
  33 /**
  34  * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
  35  *
  36  * Some combinations of hardware and kernel versions allow this feature,
  37  * while others don't.  Instead of trying to enumerate every case, just
  38  * try and write a register and see if works.
  39  */
  40 static bool
  41 can_do_pipelined_register_writes(struct brw_context *brw)
  42 {
  43    /* Supposedly, Broadwell just works. */
  44    if (brw->gen >= 8)
  45       return true;
  46
  47    static int result = -1;
  48    if (result != -1)
  49       return result;
  50
  51    /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
  52     * statistics registers), and we already reset it to zero before using it.
  53     */
  54    const int reg = GEN7_SO_WRITE_OFFSET(0);
  55    const int expected_value = 0x1337d0d0;
  56    const int offset = 100;
  57
  58    /* The register we picked only exists on Gen7+. */
  59    assert(brw->gen == 7);
  60
  61    uint32_t *data;
  62    /* Set a value in a BO to a known quantity.  The workaround BO already
  63     * exists and doesn't contain anything important, so we may as well use it.
  64     */
  65    drm_intel_bo_map(brw->workaround_bo, true);
  66    data = brw->workaround_bo->virtual;
  67    data[offset] = 0xffffffff;
  68    drm_intel_bo_unmap(brw->workaround_bo);
  69
  70    /* Write the register. */
  71    BEGIN_BATCH(3);
  72    OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
  73    OUT_BATCH(reg);
  74    OUT_BATCH(expected_value);
  75    ADVANCE_BATCH();
  76
  77    brw_emit_mi_flush(brw);
  78
  79    /* Save the register's value back to the buffer. */
  80    BEGIN_BATCH(3);
  81    OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
  82    OUT_BATCH(reg);
  83    OUT_RELOC(brw->workaround_bo,
  84              I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
  85              offset * sizeof(uint32_t));
  86    ADVANCE_BATCH();
  87
  88    intel_batchbuffer_flush(brw);
  89
  90    /* Check whether the value got written. */
  91    drm_intel_bo_map(brw->workaround_bo, false);
  92    data = brw->workaround_bo->virtual;
  93    bool success = data[offset] == expected_value;
  94    drm_intel_bo_unmap(brw->workaround_bo);
  95
  96    result = success;
  97
  98    return success;
  99 }
 100
 101 static bool
 102 can_write_oacontrol(struct brw_context *brw)
 103 {
 104    if (brw->gen < 6 || brw->gen >= 8)
 105       return false;
 106
 107    static int result = -1;
 108    if (result != -1)
 109       return result;
 110
 111    /* Set "Select Context ID" to a particular address (which is likely not a
 112     * context), but leave all counting disabled.  This should be harmless.
 113     */
 114    const int expected_value = 0x31337000;
 115    const int offset = 110;
 116
 117    uint32_t *data;
 118    /* Set a value in a BO to a known quantity.  The workaround BO already
 119     * exists and doesn't contain anything important, so we may as well use it.
 120     */
 121    drm_intel_bo_map(brw->workaround_bo, true);
 122    data = brw->workaround_bo->virtual;
 123    data[offset] = 0xffffffff;
 124    drm_intel_bo_unmap(brw->workaround_bo);
 125
 126    /* Write OACONTROL. */
 127    BEGIN_BATCH(3);
 128    OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
 129    OUT_BATCH(OACONTROL);
 130    OUT_BATCH(expected_value);
 131    ADVANCE_BATCH();
 132
 133    brw_emit_mi_flush(brw);
 134
 135    /* Save the register's value back to the buffer. */
 136    BEGIN_BATCH(3);
 137    OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
 138    OUT_BATCH(OACONTROL);
 139    OUT_RELOC(brw->workaround_bo,
 140              I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 141              offset * sizeof(uint32_t));
 142    ADVANCE_BATCH();
 143
 144    brw_emit_mi_flush(brw);
 145
 146    /* Set OACONTROL back to zero (everything off). */
 147    BEGIN_BATCH(3);
 148    OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
 149    OUT_BATCH(OACONTROL);
 150    OUT_BATCH(0);
 151    ADVANCE_BATCH();
 152
 153    intel_batchbuffer_flush(brw);
 154
 155    /* Check whether the value got written. */
 156    drm_intel_bo_map(brw->workaround_bo, false);
 157    data = brw->workaround_bo->virtual;
 158    bool success = data[offset] == expected_value;
 159    drm_intel_bo_unmap(brw->workaround_bo);
 160
 161    result = success;
 162
 163    return success;
 164 }
 165
 166 /**
 167  * Initializes potential list of extensions if ctx == NULL, or actually enables
 168  * extensions for a context.
 169  */
 170 void
 171 intelInitExtensions(struct gl_context *ctx)
 172 {
 173    struct brw_context *brw = brw_context(ctx);
 174
 175    assert(brw->gen >= 4);
 176
 177    ctx->Extensions.ARB_buffer_storage = true;
 178    ctx->Extensions.ARB_clear_texture = true;
 179    ctx->Extensions.ARB_clip_control = true;
 180    ctx->Extensions.ARB_copy_image = true;
 181    ctx->Extensions.ARB_depth_buffer_float = true;
 182    ctx->Extensions.ARB_depth_clamp = true;
 183    ctx->Extensions.ARB_depth_texture = true;
 184    ctx->Extensions.ARB_draw_elements_base_vertex = true;
 185    ctx->Extensions.ARB_draw_instanced = true;
 186    ctx->Extensions.ARB_ES2_compatibility = true;
 187    ctx->Extensions.ARB_explicit_attrib_location = true;
 188    ctx->Extensions.ARB_explicit_uniform_location = true;
 189    ctx->Extensions.ARB_fragment_coord_conventions = true;
 190    ctx->Extensions.ARB_fragment_program = true;
 191    ctx->Extensions.ARB_fragment_program_shadow = true;
 192    ctx->Extensions.ARB_fragment_shader = true;
 193    ctx->Extensions.ARB_framebuffer_object = true;
 194    ctx->Extensions.ARB_half_float_vertex = true;
 195    ctx->Extensions.ARB_instanced_arrays = true;
 196    ctx->Extensions.ARB_internalformat_query = true;
 197    ctx->Extensions.ARB_map_buffer_range = true;
 198    ctx->Extensions.ARB_occlusion_query = true;
 199    ctx->Extensions.ARB_occlusion_query2 = true;
 200    ctx->Extensions.ARB_pipeline_statistics_query = true;
 201    ctx->Extensions.ARB_point_sprite = true;
 202    ctx->Extensions.ARB_seamless_cube_map = true;
 203    ctx->Extensions.ARB_shader_bit_encoding = true;
 204    ctx->Extensions.ARB_shader_texture_lod = true;
 205    ctx->Extensions.ARB_shadow = true;
 206    ctx->Extensions.ARB_sync = true;
 207    ctx->Extensions.ARB_texture_border_clamp = true;
 208    ctx->Extensions.ARB_texture_compression_rgtc = true;
 209    ctx->Extensions.ARB_texture_cube_map = true;
 210    ctx->Extensions.ARB_texture_env_combine = true;
 211    ctx->Extensions.ARB_texture_env_crossbar = true;
 212    ctx->Extensions.ARB_texture_env_dot3 = true;
 213    ctx->Extensions.ARB_texture_float = true;
 214    ctx->Extensions.ARB_texture_mirror_clamp_to_edge = true;
 215    ctx->Extensions.ARB_texture_non_power_of_two = true;
 216    ctx->Extensions.ARB_texture_rg = true;
 217    ctx->Extensions.ARB_texture_rgb10_a2ui = true;
 218    ctx->Extensions.ARB_vertex_program = true;
 219    ctx->Extensions.ARB_vertex_shader = true;
 220    ctx->Extensions.ARB_vertex_type_2_10_10_10_rev = true;
 221    ctx->Extensions.ARB_vertex_type_10f_11f_11f_rev = true;
 222    ctx->Extensions.EXT_blend_color = true;
 223    ctx->Extensions.EXT_blend_equation_separate = true;
 224    ctx->Extensions.EXT_blend_func_separate = true;
 225    ctx->Extensions.EXT_blend_minmax = true;
 226    ctx->Extensions.EXT_draw_buffers2 = true;
 227    ctx->Extensions.EXT_framebuffer_sRGB = true;
 228    ctx->Extensions.EXT_gpu_program_parameters = true;
 229    ctx->Extensions.EXT_packed_float = true;
 230    ctx->Extensions.EXT_pixel_buffer_object = true;
 231    ctx->Extensions.EXT_point_parameters = true;
 232    ctx->Extensions.EXT_provoking_vertex = true;
 233    ctx->Extensions.EXT_stencil_two_side = true;
 234    ctx->Extensions.EXT_texture_array = true;
 235    ctx->Extensions.EXT_texture_env_dot3 = true;
 236    ctx->Extensions.EXT_texture_filter_anisotropic = true;
 237    ctx->Extensions.EXT_texture_integer = true;
 238    ctx->Extensions.EXT_texture_shared_exponent = true;
 239    ctx->Extensions.EXT_texture_snorm = true;
 240    ctx->Extensions.EXT_texture_sRGB = true;
 241    ctx->Extensions.EXT_texture_sRGB_decode = true;
 242    ctx->Extensions.EXT_texture_swizzle = true;
 243    ctx->Extensions.EXT_vertex_array_bgra = true;
 244    ctx->Extensions.AMD_seamless_cubemap_per_texture = true;
 245    ctx->Extensions.APPLE_object_purgeable = true;
 246    ctx->Extensions.ATI_separate_stencil = true;
 247    ctx->Extensions.ATI_texture_env_combine3 = true;
 248    ctx->Extensions.MESA_pack_invert = true;
 249    ctx->Extensions.NV_conditional_render = true;
 250    ctx->Extensions.NV_primitive_restart = true;
 251    ctx->Extensions.NV_texture_env_combine4 = true;
 252    ctx->Extensions.NV_texture_rectangle = true;
 253    ctx->Extensions.TDFX_texture_compression_FXT1 = true;
 254    ctx->Extensions.OES_compressed_ETC1_RGB8_texture = true;
 255    ctx->Extensions.OES_draw_texture = true;
 256    ctx->Extensions.OES_EGL_image = true;
 257    ctx->Extensions.OES_EGL_image_external = true;
 258    ctx->Extensions.OES_standard_derivatives = true;
 259    ctx->Extensions.OES_texture_float = true;
 260    ctx->Extensions.OES_texture_float_linear = true;
 261    ctx->Extensions.OES_texture_half_float = true;
 262    ctx->Extensions.OES_texture_half_float_linear = true;
 263
 264    if (brw->gen >= 6)
 265       ctx->Const.GLSLVersion = 330;
 266    else
 267       ctx->Const.GLSLVersion = 120;
 268    _mesa_override_glsl_version(&ctx->Const);
 269
 270    if (brw->gen >= 5) {
 271       ctx->Extensions.ARB_texture_query_levels = ctx->Const.GLSLVersion >= 130;
 272       ctx->Extensions.ARB_texture_query_lod = true;
 273       ctx->Extensions.EXT_shader_integer_mix = ctx->Const.GLSLVersion >= 130;
 274       ctx->Extensions.EXT_timer_query = true;
 275
 276       if (brw->gen == 5 || can_write_oacontrol(brw)) {
 277          ctx->Extensions.AMD_performance_monitor = true;
 278          ctx->Extensions.INTEL_performance_query = true;
 279       }
 280    }
 281
 282    if (brw->gen >= 6) {
 283       ctx->Extensions.ARB_blend_func_extended =
 284          !driQueryOptionb(&brw->optionCache, "disable_blend_func_extended");
 285       ctx->Extensions.ARB_conditional_render_inverted = true;
 286       ctx->Extensions.ARB_draw_buffers_blend = true;
 287       ctx->Extensions.ARB_ES3_compatibility = true;
 288       ctx->Extensions.ARB_sample_shading = true;
 289       ctx->Extensions.ARB_shading_language_420pack = true;
 290       ctx->Extensions.ARB_shading_language_packing = true;
 291       ctx->Extensions.ARB_texture_buffer_object = true;
 292       ctx->Extensions.ARB_texture_buffer_object_rgb32 = true;
 293       ctx->Extensions.ARB_texture_buffer_range = true;
 294       ctx->Extensions.ARB_texture_cube_map_array = true;
 295       ctx->Extensions.ARB_texture_gather = true;
 296       ctx->Extensions.ARB_texture_multisample = true;
 297       ctx->Extensions.ARB_uniform_buffer_object = true;
 298
 299       ctx->Extensions.AMD_vertex_shader_layer = true;
 300       ctx->Extensions.EXT_framebuffer_multisample = true;
 301       ctx->Extensions.EXT_framebuffer_multisample_blit_scaled = true;
 302       ctx->Extensions.EXT_polygon_offset_clamp = true;
 303       ctx->Extensions.EXT_transform_feedback = true;
 304       ctx->Extensions.OES_depth_texture_cube_map = true;
 305
 306       ctx->Extensions.ARB_timer_query = brw->intelScreen->hw_has_timestamp;
 307
 308       /* Only enable this in core profile because other parts of Mesa behave
 309        * slightly differently when the extension is enabled.
 310        */
 311       if (ctx->API == API_OPENGL_CORE) {
 312          ctx->Extensions.ARB_shader_subroutine = true;
 313          ctx->Extensions.ARB_viewport_array = true;
 314          ctx->Extensions.AMD_vertex_shader_viewport_index = true;
 315       }
 316    }
 317
 318    brw->predicate.supported = false;
 319
 320    if (brw->gen >= 7) {
 321       ctx->Extensions.ARB_conservative_depth = true;
 322       ctx->Extensions.ARB_derivative_control = true;
 323       ctx->Extensions.ARB_framebuffer_no_attachments = true;
 324       ctx->Extensions.ARB_gpu_shader5 = true;
 325       ctx->Extensions.ARB_shader_atomic_counters = true;
 326       ctx->Extensions.ARB_shader_image_load_store = true;
 327       ctx->Extensions.ARB_shader_image_size = true;
 328       ctx->Extensions.ARB_texture_compression_bptc = true;
 329       ctx->Extensions.ARB_texture_view = true;
 330
 331       if (can_do_pipelined_register_writes(brw)) {
 332          ctx->Extensions.ARB_draw_indirect = true;
 333          ctx->Extensions.ARB_transform_feedback2 = true;
 334          ctx->Extensions.ARB_transform_feedback3 = true;
 335          ctx->Extensions.ARB_transform_feedback_instanced = true;
 336
 337          if (brw->intelScreen->cmd_parser_version >= 2)
 338             brw->predicate.supported = true;
 339       }
 340
 341       /* Only enable this in core profile because other parts of Mesa behave
 342        * slightly differently when the extension is enabled.
 343        */
 344       if (ctx->API == API_OPENGL_CORE) {
 345          ctx->Extensions.ARB_viewport_array = true;
 346          ctx->Extensions.AMD_vertex_shader_viewport_index = true;
 347          ctx->Extensions.ARB_shader_subroutine = true;
 348       }
 349    }
 350
 351    if (brw->gen >= 8) {
 352       ctx->Extensions.ARB_stencil_texturing = true;
 353    }
 354
 355    if (brw->gen >= 9) {
 356       ctx->Extensions.KHR_texture_compression_astc_ldr = true;
 357       ctx->Extensions.KHR_texture_compression_astc_hdr = true;
 358    }
 359
 360    if (ctx->API == API_OPENGL_CORE)
 361       ctx->Extensions.ARB_base_instance = true;
 362    if (ctx->API != API_OPENGL_CORE)
 363       ctx->Extensions.ARB_color_buffer_float = true;
 364
 365    if (ctx->Mesa_DXTn || driQueryOptionb(&brw->optionCache, "force_s3tc_enable"))
 366       ctx->Extensions.EXT_texture_compression_s3tc = true;
 367
 368    ctx->Extensions.ANGLE_texture_compression_dxt = true;
 369 }