i965: Use miptree_create_for_dri_image in image_target_renderbuffer_storage
[mesa.git] / src / mesa / drivers / dri / i965 / intel_fbo.c
1 /*
2 * Copyright 2006 VMware, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "main/enums.h"
27 #include "main/imports.h"
28 #include "main/macros.h"
29 #include "main/mtypes.h"
30 #include "main/fbobject.h"
31 #include "main/framebuffer.h"
32 #include "main/renderbuffer.h"
33 #include "main/context.h"
34 #include "main/teximage.h"
35 #include "main/image.h"
36 #include "main/condrender.h"
37 #include "util/hash_table.h"
38 #include "util/set.h"
39
40 #include "swrast/swrast.h"
41 #include "drivers/common/meta.h"
42
43 #include "intel_batchbuffer.h"
44 #include "intel_buffers.h"
45 #include "intel_blit.h"
46 #include "intel_fbo.h"
47 #include "intel_mipmap_tree.h"
48 #include "intel_image.h"
49 #include "intel_screen.h"
50 #include "intel_tex.h"
51 #include "brw_context.h"
52 #include "brw_defines.h"
53
54 #define FILE_DEBUG_FLAG DEBUG_FBO
55
56 /** Called by gl_renderbuffer::Delete() */
57 static void
58 intel_delete_renderbuffer(struct gl_context *ctx, struct gl_renderbuffer *rb)
59 {
60 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
61
62 assert(irb);
63
64 intel_miptree_release(&irb->mt);
65 intel_miptree_release(&irb->singlesample_mt);
66
67 _mesa_delete_renderbuffer(ctx, rb);
68 }
69
70 /**
71 * \brief Downsample a winsys renderbuffer from mt to singlesample_mt.
72 *
73 * If the miptree needs no downsample, then skip.
74 */
75 void
76 intel_renderbuffer_downsample(struct brw_context *brw,
77 struct intel_renderbuffer *irb)
78 {
79 if (!irb->need_downsample)
80 return;
81 intel_miptree_updownsample(brw, irb->mt, irb->singlesample_mt);
82 irb->need_downsample = false;
83 }
84
85 /**
86 * \brief Upsample a winsys renderbuffer from singlesample_mt to mt.
87 *
88 * The upsample is done unconditionally.
89 */
90 void
91 intel_renderbuffer_upsample(struct brw_context *brw,
92 struct intel_renderbuffer *irb)
93 {
94 assert(!irb->need_downsample);
95
96 intel_miptree_updownsample(brw, irb->singlesample_mt, irb->mt);
97 }
98
99 /**
100 * \see dd_function_table::MapRenderbuffer
101 */
102 static void
103 intel_map_renderbuffer(struct gl_context *ctx,
104 struct gl_renderbuffer *rb,
105 GLuint x, GLuint y, GLuint w, GLuint h,
106 GLbitfield mode,
107 GLubyte **out_map,
108 GLint *out_stride)
109 {
110 struct brw_context *brw = brw_context(ctx);
111 struct swrast_renderbuffer *srb = (struct swrast_renderbuffer *)rb;
112 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
113 struct intel_mipmap_tree *mt;
114 void *map;
115 ptrdiff_t stride;
116
117 if (srb->Buffer) {
118 /* this is a malloc'd renderbuffer (accum buffer), not an irb */
119 GLint bpp = _mesa_get_format_bytes(rb->Format);
120 GLint rowStride = srb->RowStride;
121 *out_map = (GLubyte *) srb->Buffer + y * rowStride + x * bpp;
122 *out_stride = rowStride;
123 return;
124 }
125
126 intel_prepare_render(brw);
127
128 /* The MapRenderbuffer API should always return a single-sampled mapping.
129 * The case we are asked to map multisampled RBs is in glReadPixels() (or
130 * swrast paths like glCopyTexImage()) from a window-system MSAA buffer,
131 * and GL expects an automatic resolve to happen.
132 *
133 * If it's a color miptree, there is a ->singlesample_mt which wraps the
134 * actual window system renderbuffer (which we may resolve to at any time),
135 * while the miptree itself is our driver-private allocation. If it's a
136 * depth or stencil miptree, we have a private MSAA buffer and no shared
137 * singlesample buffer, and since we don't expect anybody to ever actually
138 * resolve it, we just make a temporary singlesample buffer now when we
139 * have to.
140 */
141 if (rb->NumSamples > 1) {
142 if (!irb->singlesample_mt) {
143 irb->singlesample_mt =
144 intel_miptree_create_for_renderbuffer(brw, irb->mt->format,
145 rb->Width, rb->Height,
146 0 /*num_samples*/);
147 if (!irb->singlesample_mt)
148 goto fail;
149 irb->singlesample_mt_is_tmp = true;
150 irb->need_downsample = true;
151 }
152
153 intel_renderbuffer_downsample(brw, irb);
154 mt = irb->singlesample_mt;
155
156 irb->need_map_upsample = mode & GL_MAP_WRITE_BIT;
157 } else {
158 mt = irb->mt;
159 }
160
161 /* For a window-system renderbuffer, we need to flip the mapping we receive
162 * upside-down. So we need to ask for a rectangle on flipped vertically, and
163 * we then return a pointer to the bottom of it with a negative stride.
164 */
165 if (rb->Name == 0) {
166 y = rb->Height - y - h;
167 }
168
169 intel_miptree_map(brw, mt, irb->mt_level, irb->mt_layer,
170 x, y, w, h, mode, &map, &stride);
171
172 if (rb->Name == 0) {
173 map += (h - 1) * stride;
174 stride = -stride;
175 }
176
177 DBG("%s: rb %d (%s) mt mapped: (%d, %d) (%dx%d) -> %p/%"PRIdPTR"\n",
178 __func__, rb->Name, _mesa_get_format_name(rb->Format),
179 x, y, w, h, map, stride);
180
181 *out_map = map;
182 *out_stride = stride;
183 return;
184
185 fail:
186 *out_map = NULL;
187 *out_stride = 0;
188 }
189
190 /**
191 * \see dd_function_table::UnmapRenderbuffer
192 */
193 static void
194 intel_unmap_renderbuffer(struct gl_context *ctx,
195 struct gl_renderbuffer *rb)
196 {
197 struct brw_context *brw = brw_context(ctx);
198 struct swrast_renderbuffer *srb = (struct swrast_renderbuffer *)rb;
199 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
200 struct intel_mipmap_tree *mt;
201
202 DBG("%s: rb %d (%s)\n", __func__,
203 rb->Name, _mesa_get_format_name(rb->Format));
204
205 if (srb->Buffer) {
206 /* this is a malloc'd renderbuffer (accum buffer) */
207 /* nothing to do */
208 return;
209 }
210
211 if (rb->NumSamples > 1) {
212 mt = irb->singlesample_mt;
213 } else {
214 mt = irb->mt;
215 }
216
217 intel_miptree_unmap(brw, mt, irb->mt_level, irb->mt_layer);
218
219 if (irb->need_map_upsample) {
220 intel_renderbuffer_upsample(brw, irb);
221 irb->need_map_upsample = false;
222 }
223
224 if (irb->singlesample_mt_is_tmp)
225 intel_miptree_release(&irb->singlesample_mt);
226 }
227
228
229 /**
230 * Round up the requested multisample count to the next supported sample size.
231 */
232 unsigned
233 intel_quantize_num_samples(struct intel_screen *intel, unsigned num_samples)
234 {
235 const int *msaa_modes = intel_supported_msaa_modes(intel);
236 int quantized_samples = 0;
237
238 for (int i = 0; msaa_modes[i] != -1; ++i) {
239 if (msaa_modes[i] >= num_samples)
240 quantized_samples = msaa_modes[i];
241 else
242 break;
243 }
244
245 return quantized_samples;
246 }
247
248 static mesa_format
249 intel_renderbuffer_format(struct gl_context * ctx, GLenum internalFormat)
250 {
251 struct brw_context *brw = brw_context(ctx);
252
253 switch (internalFormat) {
254 default:
255 /* Use the same format-choice logic as for textures.
256 * Renderbuffers aren't any different from textures for us,
257 * except they're less useful because you can't texture with
258 * them.
259 */
260 return ctx->Driver.ChooseTextureFormat(ctx, GL_TEXTURE_2D,
261 internalFormat,
262 GL_NONE, GL_NONE);
263 break;
264 case GL_STENCIL_INDEX:
265 case GL_STENCIL_INDEX1_EXT:
266 case GL_STENCIL_INDEX4_EXT:
267 case GL_STENCIL_INDEX8_EXT:
268 case GL_STENCIL_INDEX16_EXT:
269 /* These aren't actual texture formats, so force them here. */
270 if (brw->has_separate_stencil) {
271 return MESA_FORMAT_S_UINT8;
272 } else {
273 assert(!brw->must_use_separate_stencil);
274 return MESA_FORMAT_Z24_UNORM_S8_UINT;
275 }
276 }
277 }
278
279 static GLboolean
280 intel_alloc_private_renderbuffer_storage(struct gl_context * ctx, struct gl_renderbuffer *rb,
281 GLenum internalFormat,
282 GLuint width, GLuint height)
283 {
284 struct brw_context *brw = brw_context(ctx);
285 struct intel_screen *screen = brw->screen;
286 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
287
288 assert(rb->Format != MESA_FORMAT_NONE);
289
290 rb->NumSamples = intel_quantize_num_samples(screen, rb->NumSamples);
291 rb->Width = width;
292 rb->Height = height;
293 rb->_BaseFormat = _mesa_get_format_base_format(rb->Format);
294
295 intel_miptree_release(&irb->mt);
296
297 DBG("%s: %s: %s (%dx%d)\n", __func__,
298 _mesa_enum_to_string(internalFormat),
299 _mesa_get_format_name(rb->Format), width, height);
300
301 if (width == 0 || height == 0)
302 return true;
303
304 irb->mt = intel_miptree_create_for_renderbuffer(brw, rb->Format,
305 width, height,
306 rb->NumSamples);
307 if (!irb->mt)
308 return false;
309
310 irb->layer_count = 1;
311
312 return true;
313 }
314
315 /**
316 * Called via glRenderbufferStorageEXT() to set the format and allocate
317 * storage for a user-created renderbuffer.
318 */
319 static GLboolean
320 intel_alloc_renderbuffer_storage(struct gl_context * ctx, struct gl_renderbuffer *rb,
321 GLenum internalFormat,
322 GLuint width, GLuint height)
323 {
324 rb->Format = intel_renderbuffer_format(ctx, internalFormat);
325 return intel_alloc_private_renderbuffer_storage(ctx, rb, internalFormat, width, height);
326 }
327
328 static void
329 intel_image_target_renderbuffer_storage(struct gl_context *ctx,
330 struct gl_renderbuffer *rb,
331 void *image_handle)
332 {
333 struct brw_context *brw = brw_context(ctx);
334 struct intel_renderbuffer *irb;
335 __DRIscreen *dri_screen = brw->screen->driScrnPriv;
336 __DRIimage *image;
337
338 image = dri_screen->dri2.image->lookupEGLImage(dri_screen, image_handle,
339 dri_screen->loaderPrivate);
340 if (image == NULL)
341 return;
342
343 if (image->planar_format && image->planar_format->nplanes > 1) {
344 _mesa_error(ctx, GL_INVALID_OPERATION,
345 "glEGLImageTargetRenderbufferStorage(planar buffers are not "
346 "supported as render targets.)");
347 return;
348 }
349
350 /* __DRIimage is opaque to the core so it has to be checked here */
351 if (!brw->mesa_format_supports_render[image->format]) {
352 _mesa_error(ctx, GL_INVALID_OPERATION,
353 "glEGLImageTargetRenderbufferStorage(unsupported image format)");
354 return;
355 }
356
357 irb = intel_renderbuffer(rb);
358 intel_miptree_release(&irb->mt);
359
360 /* Disable creation of the miptree's aux buffers because the driver exposes
361 * no EGL API to manage them. That is, there is no API for resolving the aux
362 * buffer's content to the main buffer nor for invalidating the aux buffer's
363 * content.
364 */
365 irb->mt = intel_miptree_create_for_dri_image(brw, image, GL_TEXTURE_2D);
366 if (!irb->mt)
367 return;
368
369 rb->InternalFormat = image->internal_format;
370 rb->Width = image->width;
371 rb->Height = image->height;
372 rb->Format = image->format;
373 rb->_BaseFormat = _mesa_get_format_base_format(image->format);
374 rb->NeedsFinishRenderTexture = true;
375 irb->layer_count = 1;
376 }
377
378 /**
379 * Called by _mesa_resize_framebuffer() for each hardware renderbuffer when a
380 * window system framebuffer is resized.
381 *
382 * Any actual buffer reallocations for hardware renderbuffers (which would
383 * have triggered _mesa_resize_framebuffer()) were done by
384 * intel_process_dri2_buffer().
385 */
386 static GLboolean
387 intel_alloc_window_storage(struct gl_context * ctx, struct gl_renderbuffer *rb,
388 GLenum internalFormat, GLuint width, GLuint height)
389 {
390 (void) ctx;
391 assert(rb->Name == 0);
392 rb->Width = width;
393 rb->Height = height;
394 rb->InternalFormat = internalFormat;
395
396 return true;
397 }
398
399 /** Dummy function for gl_renderbuffer::AllocStorage() */
400 static GLboolean
401 intel_nop_alloc_storage(struct gl_context * ctx, struct gl_renderbuffer *rb,
402 GLenum internalFormat, GLuint width, GLuint height)
403 {
404 (void) rb;
405 (void) internalFormat;
406 (void) width;
407 (void) height;
408 _mesa_problem(ctx, "intel_nop_alloc_storage should never be called.");
409 return false;
410 }
411
412 /**
413 * Create an intel_renderbuffer for a __DRIdrawable. This function is
414 * unrelated to GL renderbuffers (that is, those created by
415 * glGenRenderbuffers).
416 *
417 * \param num_samples must be quantized.
418 */
419 struct intel_renderbuffer *
420 intel_create_winsys_renderbuffer(struct intel_screen *screen,
421 mesa_format format, unsigned num_samples)
422 {
423 struct intel_renderbuffer *irb = CALLOC_STRUCT(intel_renderbuffer);
424 if (!irb)
425 return NULL;
426
427 struct gl_renderbuffer *rb = &irb->Base.Base;
428 irb->layer_count = 1;
429
430 _mesa_init_renderbuffer(rb, 0);
431 rb->ClassID = INTEL_RB_CLASS;
432 rb->NumSamples = num_samples;
433
434 /* The base format and internal format must be derived from the user-visible
435 * format (that is, the gl_config's format), even if we internally use
436 * choose a different format for the renderbuffer. Otherwise, rendering may
437 * use incorrect channel write masks.
438 */
439 rb->_BaseFormat = _mesa_get_format_base_format(format);
440 rb->InternalFormat = rb->_BaseFormat;
441
442 rb->Format = format;
443 if (!screen->mesa_format_supports_render[rb->Format]) {
444 /* The glRenderbufferStorage paths in core Mesa detect if the driver
445 * does not support the user-requested format, and then searches for
446 * a falback format. The DRI code bypasses core Mesa, though. So we do
447 * the fallbacks here.
448 *
449 * We must support MESA_FORMAT_R8G8B8X8 on Android because the Android
450 * framework requires HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces.
451 */
452 rb->Format = _mesa_format_fallback_rgbx_to_rgba(rb->Format);
453 assert(screen->mesa_format_supports_render[rb->Format]);
454 }
455
456 /* intel-specific methods */
457 rb->Delete = intel_delete_renderbuffer;
458 rb->AllocStorage = intel_alloc_window_storage;
459
460 return irb;
461 }
462
463 /**
464 * Private window-system buffers (as opposed to ones shared with the display
465 * server created with intel_create_winsys_renderbuffer()) are most similar in their
466 * handling to user-created renderbuffers, but they have a resize handler that
467 * may be called at intel_update_renderbuffers() time.
468 *
469 * \param num_samples must be quantized.
470 */
471 struct intel_renderbuffer *
472 intel_create_private_renderbuffer(struct intel_screen *screen,
473 mesa_format format, unsigned num_samples)
474 {
475 struct intel_renderbuffer *irb;
476
477 irb = intel_create_winsys_renderbuffer(screen, format, num_samples);
478 irb->Base.Base.AllocStorage = intel_alloc_private_renderbuffer_storage;
479
480 return irb;
481 }
482
483 /**
484 * Create a new renderbuffer object.
485 * Typically called via glBindRenderbufferEXT().
486 */
487 static struct gl_renderbuffer *
488 intel_new_renderbuffer(struct gl_context * ctx, GLuint name)
489 {
490 struct intel_renderbuffer *irb;
491 struct gl_renderbuffer *rb;
492
493 irb = CALLOC_STRUCT(intel_renderbuffer);
494 if (!irb) {
495 _mesa_error(ctx, GL_OUT_OF_MEMORY, "creating renderbuffer");
496 return NULL;
497 }
498
499 rb = &irb->Base.Base;
500
501 _mesa_init_renderbuffer(rb, name);
502 rb->ClassID = INTEL_RB_CLASS;
503
504 /* intel-specific methods */
505 rb->Delete = intel_delete_renderbuffer;
506 rb->AllocStorage = intel_alloc_renderbuffer_storage;
507 /* span routines set in alloc_storage function */
508
509 return rb;
510 }
511
512 static bool
513 intel_renderbuffer_update_wrapper(struct brw_context *brw,
514 struct intel_renderbuffer *irb,
515 struct gl_texture_image *image,
516 uint32_t layer,
517 bool layered)
518 {
519 struct gl_renderbuffer *rb = &irb->Base.Base;
520 struct intel_texture_image *intel_image = intel_texture_image(image);
521 struct intel_mipmap_tree *mt = intel_image->mt;
522 int level = image->Level;
523
524 rb->AllocStorage = intel_nop_alloc_storage;
525
526 /* adjust for texture view parameters */
527 layer += image->TexObject->MinLayer;
528 level += image->TexObject->MinLevel;
529
530 intel_miptree_check_level_layer(mt, level, layer);
531 irb->mt_level = level;
532
533 int layer_multiplier;
534 switch (mt->msaa_layout) {
535 case INTEL_MSAA_LAYOUT_UMS:
536 case INTEL_MSAA_LAYOUT_CMS:
537 layer_multiplier = MAX2(mt->num_samples, 1);
538 break;
539
540 default:
541 layer_multiplier = 1;
542 }
543
544 irb->mt_layer = layer_multiplier * layer;
545
546 if (!layered) {
547 irb->layer_count = 1;
548 } else if (mt->target != GL_TEXTURE_3D && image->TexObject->NumLayers > 0) {
549 irb->layer_count = image->TexObject->NumLayers;
550 } else {
551 irb->layer_count = mt->level[level].depth / layer_multiplier;
552 }
553
554 intel_miptree_reference(&irb->mt, mt);
555
556 intel_renderbuffer_set_draw_offset(irb);
557
558 if (mt->aux_usage == ISL_AUX_USAGE_HIZ && !mt->hiz_buf) {
559 intel_miptree_alloc_hiz(brw, mt);
560 if (!mt->hiz_buf)
561 return false;
562 }
563
564 return true;
565 }
566
567 void
568 intel_renderbuffer_set_draw_offset(struct intel_renderbuffer *irb)
569 {
570 unsigned int dst_x, dst_y;
571
572 /* compute offset of the particular 2D image within the texture region */
573 intel_miptree_get_image_offset(irb->mt,
574 irb->mt_level,
575 irb->mt_layer,
576 &dst_x, &dst_y);
577
578 irb->draw_x = dst_x;
579 irb->draw_y = dst_y;
580 }
581
582 /**
583 * Called by glFramebufferTexture[123]DEXT() (and other places) to
584 * prepare for rendering into texture memory. This might be called
585 * many times to choose different texture levels, cube faces, etc
586 * before intel_finish_render_texture() is ever called.
587 */
588 static void
589 intel_render_texture(struct gl_context * ctx,
590 struct gl_framebuffer *fb,
591 struct gl_renderbuffer_attachment *att)
592 {
593 struct brw_context *brw = brw_context(ctx);
594 struct gl_renderbuffer *rb = att->Renderbuffer;
595 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
596 struct gl_texture_image *image = rb->TexImage;
597 struct intel_texture_image *intel_image = intel_texture_image(image);
598 struct intel_mipmap_tree *mt = intel_image->mt;
599 int layer;
600
601 (void) fb;
602
603 if (att->CubeMapFace > 0) {
604 assert(att->Zoffset == 0);
605 layer = att->CubeMapFace;
606 } else {
607 layer = att->Zoffset;
608 }
609
610 if (!intel_image->mt) {
611 /* Fallback on drawing to a texture that doesn't have a miptree
612 * (has a border, width/height 0, etc.)
613 */
614 _swrast_render_texture(ctx, fb, att);
615 return;
616 }
617
618 intel_miptree_check_level_layer(mt, att->TextureLevel, layer);
619
620 if (!intel_renderbuffer_update_wrapper(brw, irb, image, layer, att->Layered)) {
621 _swrast_render_texture(ctx, fb, att);
622 return;
623 }
624
625 DBG("Begin render %s texture tex=%u w=%d h=%d d=%d refcount=%d\n",
626 _mesa_get_format_name(image->TexFormat),
627 att->Texture->Name, image->Width, image->Height, image->Depth,
628 rb->RefCount);
629 }
630
631
632 #define fbo_incomplete(fb, ...) do { \
633 static GLuint msg_id = 0; \
634 if (unlikely(ctx->Const.ContextFlags & GL_CONTEXT_FLAG_DEBUG_BIT)) { \
635 _mesa_gl_debug(ctx, &msg_id, \
636 MESA_DEBUG_SOURCE_API, \
637 MESA_DEBUG_TYPE_OTHER, \
638 MESA_DEBUG_SEVERITY_MEDIUM, \
639 __VA_ARGS__); \
640 } \
641 DBG(__VA_ARGS__); \
642 fb->_Status = GL_FRAMEBUFFER_UNSUPPORTED; \
643 } while (0)
644
645 /**
646 * Do additional "completeness" testing of a framebuffer object.
647 */
648 static void
649 intel_validate_framebuffer(struct gl_context *ctx, struct gl_framebuffer *fb)
650 {
651 struct brw_context *brw = brw_context(ctx);
652 struct intel_renderbuffer *depthRb =
653 intel_get_renderbuffer(fb, BUFFER_DEPTH);
654 struct intel_renderbuffer *stencilRb =
655 intel_get_renderbuffer(fb, BUFFER_STENCIL);
656 struct intel_mipmap_tree *depth_mt = NULL, *stencil_mt = NULL;
657 unsigned i;
658
659 DBG("%s() on fb %p (%s)\n", __func__,
660 fb, (fb == ctx->DrawBuffer ? "drawbuffer" :
661 (fb == ctx->ReadBuffer ? "readbuffer" : "other buffer")));
662
663 if (depthRb)
664 depth_mt = depthRb->mt;
665 if (stencilRb) {
666 stencil_mt = stencilRb->mt;
667 if (stencil_mt->stencil_mt)
668 stencil_mt = stencil_mt->stencil_mt;
669 }
670
671 if (depth_mt && stencil_mt) {
672 if (brw->gen >= 6) {
673 unsigned d_width, d_height, d_depth;
674 unsigned s_width, s_height, s_depth;
675
676 if (depth_mt->surf.size > 0) {
677 d_width = depth_mt->surf.phys_level0_sa.width;
678 d_height = depth_mt->surf.phys_level0_sa.height;
679 d_depth = depth_mt->surf.dim == ISL_SURF_DIM_3D ?
680 depth_mt->surf.phys_level0_sa.depth :
681 depth_mt->surf.phys_level0_sa.array_len;
682 } else {
683 d_width = depth_mt->physical_width0;
684 d_height = depth_mt->physical_height0;
685 d_depth = depth_mt->physical_depth0;
686 }
687
688 if (stencil_mt->surf.size > 0) {
689 s_width = stencil_mt->surf.phys_level0_sa.width;
690 s_height = stencil_mt->surf.phys_level0_sa.height;
691 s_depth = stencil_mt->surf.dim == ISL_SURF_DIM_3D ?
692 stencil_mt->surf.phys_level0_sa.depth :
693 stencil_mt->surf.phys_level0_sa.array_len;
694 } else {
695 s_width = stencil_mt->physical_width0;
696 s_height = stencil_mt->physical_height0;
697 s_depth = stencil_mt->physical_depth0;
698 }
699
700 /* For gen >= 6, we are using the lod/minimum-array-element fields
701 * and supporting layered rendering. This means that we must restrict
702 * the depth & stencil attachments to match in various more retrictive
703 * ways. (width, height, depth, LOD and layer)
704 */
705 if (d_width != s_width ||
706 d_height != s_height ||
707 d_depth != s_depth ||
708 depthRb->mt_level != stencilRb->mt_level ||
709 depthRb->mt_layer != stencilRb->mt_layer) {
710 fbo_incomplete(fb,
711 "FBO incomplete: depth and stencil must match in"
712 "width, height, depth, LOD and layer\n");
713 }
714 }
715 if (depth_mt == stencil_mt) {
716 /* For true packed depth/stencil (not faked on prefers-separate-stencil
717 * hardware) we need to be sure they're the same level/layer, since
718 * we'll be emitting a single packet describing the packed setup.
719 */
720 if (depthRb->mt_level != stencilRb->mt_level ||
721 depthRb->mt_layer != stencilRb->mt_layer) {
722 fbo_incomplete(fb,
723 "FBO incomplete: depth image level/layer %d/%d != "
724 "stencil image %d/%d\n",
725 depthRb->mt_level,
726 depthRb->mt_layer,
727 stencilRb->mt_level,
728 stencilRb->mt_layer);
729 }
730 } else {
731 if (!brw->has_separate_stencil) {
732 fbo_incomplete(fb, "FBO incomplete: separate stencil "
733 "unsupported\n");
734 }
735 if (stencil_mt->format != MESA_FORMAT_S_UINT8) {
736 fbo_incomplete(fb, "FBO incomplete: separate stencil is %s "
737 "instead of S8\n",
738 _mesa_get_format_name(stencil_mt->format));
739 }
740 if (brw->gen < 7 && !intel_renderbuffer_has_hiz(depthRb)) {
741 /* Before Gen7, separate depth and stencil buffers can be used
742 * only if HiZ is enabled. From the Sandybridge PRM, Volume 2,
743 * Part 1, Bit 3DSTATE_DEPTH_BUFFER.SeparateStencilBufferEnable:
744 * [DevSNB]: This field must be set to the same value (enabled
745 * or disabled) as Hierarchical Depth Buffer Enable.
746 */
747 fbo_incomplete(fb, "FBO incomplete: separate stencil "
748 "without HiZ\n");
749 }
750 }
751 }
752
753 for (i = 0; i < ARRAY_SIZE(fb->Attachment); i++) {
754 struct gl_renderbuffer *rb;
755 struct intel_renderbuffer *irb;
756
757 if (fb->Attachment[i].Type == GL_NONE)
758 continue;
759
760 /* A supported attachment will have a Renderbuffer set either
761 * from being a Renderbuffer or being a texture that got the
762 * intel_wrap_texture() treatment.
763 */
764 rb = fb->Attachment[i].Renderbuffer;
765 if (rb == NULL) {
766 fbo_incomplete(fb, "FBO incomplete: attachment without "
767 "renderbuffer\n");
768 continue;
769 }
770
771 if (fb->Attachment[i].Type == GL_TEXTURE) {
772 if (rb->TexImage->Border) {
773 fbo_incomplete(fb, "FBO incomplete: texture with border\n");
774 continue;
775 }
776 }
777
778 irb = intel_renderbuffer(rb);
779 if (irb == NULL) {
780 fbo_incomplete(fb, "FBO incomplete: software rendering "
781 "renderbuffer\n");
782 continue;
783 }
784
785 if (!brw_render_target_supported(brw, rb)) {
786 fbo_incomplete(fb, "FBO incomplete: Unsupported HW "
787 "texture/renderbuffer format attached: %s\n",
788 _mesa_get_format_name(intel_rb_format(irb)));
789 }
790 }
791 }
792
793 /**
794 * Try to do a glBlitFramebuffer using glCopyTexSubImage2D
795 * We can do this when the dst renderbuffer is actually a texture and
796 * there is no scaling, mirroring or scissoring.
797 *
798 * \return new buffer mask indicating the buffers left to blit using the
799 * normal path.
800 */
801 static GLbitfield
802 intel_blit_framebuffer_with_blitter(struct gl_context *ctx,
803 const struct gl_framebuffer *readFb,
804 const struct gl_framebuffer *drawFb,
805 GLint srcX0, GLint srcY0,
806 GLint srcX1, GLint srcY1,
807 GLint dstX0, GLint dstY0,
808 GLint dstX1, GLint dstY1,
809 GLbitfield mask)
810 {
811 struct brw_context *brw = brw_context(ctx);
812
813 /* Sync up the state of window system buffers. We need to do this before
814 * we go looking for the buffers.
815 */
816 intel_prepare_render(brw);
817
818 if (mask & GL_COLOR_BUFFER_BIT) {
819 unsigned i;
820 struct gl_renderbuffer *src_rb = readFb->_ColorReadBuffer;
821 struct intel_renderbuffer *src_irb = intel_renderbuffer(src_rb);
822
823 if (!src_irb) {
824 perf_debug("glBlitFramebuffer(): missing src renderbuffer. "
825 "Falling back to software rendering.\n");
826 return mask;
827 }
828
829 /* If the source and destination are the same size with no mirroring,
830 * the rectangles are within the size of the texture and there is no
831 * scissor, then we can probably use the blit engine.
832 */
833 if (!(srcX0 - srcX1 == dstX0 - dstX1 &&
834 srcY0 - srcY1 == dstY0 - dstY1 &&
835 srcX1 >= srcX0 &&
836 srcY1 >= srcY0 &&
837 srcX0 >= 0 && srcX1 <= readFb->Width &&
838 srcY0 >= 0 && srcY1 <= readFb->Height &&
839 dstX0 >= 0 && dstX1 <= drawFb->Width &&
840 dstY0 >= 0 && dstY1 <= drawFb->Height &&
841 !(ctx->Scissor.EnableFlags))) {
842 perf_debug("glBlitFramebuffer(): non-1:1 blit. "
843 "Falling back to software rendering.\n");
844 return mask;
845 }
846
847 /* Blit to all active draw buffers. We don't do any pre-checking,
848 * because we assume that copying to MRTs is rare, and failure midway
849 * through copying is even more rare. Even if it was to occur, it's
850 * safe to let meta start the copy over from scratch, because
851 * glBlitFramebuffer completely overwrites the destination pixels, and
852 * results are undefined if any destination pixels have a dependency on
853 * source pixels.
854 */
855 for (i = 0; i < drawFb->_NumColorDrawBuffers; i++) {
856 struct gl_renderbuffer *dst_rb = drawFb->_ColorDrawBuffers[i];
857 struct intel_renderbuffer *dst_irb = intel_renderbuffer(dst_rb);
858
859 if (!dst_irb) {
860 perf_debug("glBlitFramebuffer(): missing dst renderbuffer. "
861 "Falling back to software rendering.\n");
862 return mask;
863 }
864
865 if (ctx->Color.sRGBEnabled &&
866 _mesa_get_format_color_encoding(src_irb->mt->format) !=
867 _mesa_get_format_color_encoding(dst_irb->mt->format)) {
868 perf_debug("glBlitFramebuffer() with sRGB conversion cannot be "
869 "handled by BLT path.\n");
870 return mask;
871 }
872
873 if (!intel_miptree_blit(brw,
874 src_irb->mt,
875 src_irb->mt_level, src_irb->mt_layer,
876 srcX0, srcY0, src_rb->Name == 0,
877 dst_irb->mt,
878 dst_irb->mt_level, dst_irb->mt_layer,
879 dstX0, dstY0, dst_rb->Name == 0,
880 dstX1 - dstX0, dstY1 - dstY0, GL_COPY)) {
881 perf_debug("glBlitFramebuffer(): unknown blit failure. "
882 "Falling back to software rendering.\n");
883 return mask;
884 }
885 }
886
887 mask &= ~GL_COLOR_BUFFER_BIT;
888 }
889
890 return mask;
891 }
892
893 static void
894 intel_blit_framebuffer(struct gl_context *ctx,
895 struct gl_framebuffer *readFb,
896 struct gl_framebuffer *drawFb,
897 GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1,
898 GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
899 GLbitfield mask, GLenum filter)
900 {
901 struct brw_context *brw = brw_context(ctx);
902
903 /* Page 679 of OpenGL 4.4 spec says:
904 * "Added BlitFramebuffer to commands affected by conditional rendering in
905 * section 10.10 (Bug 9562)."
906 */
907 if (!_mesa_check_conditional_render(ctx))
908 return;
909
910 if (brw->gen < 6) {
911 /* On gen4-5, try BLT first.
912 *
913 * Gen4-5 have a single ring for both 3D and BLT operations, so there's
914 * no inter-ring synchronization issues like on Gen6+. It is apparently
915 * faster than using the 3D pipeline. Original Gen4 also has to rebase
916 * and copy miptree slices in order to render to unaligned locations.
917 */
918 mask = intel_blit_framebuffer_with_blitter(ctx, readFb, drawFb,
919 srcX0, srcY0, srcX1, srcY1,
920 dstX0, dstY0, dstX1, dstY1,
921 mask);
922 if (mask == 0x0)
923 return;
924 }
925
926 mask = brw_blorp_framebuffer(brw, readFb, drawFb,
927 srcX0, srcY0, srcX1, srcY1,
928 dstX0, dstY0, dstX1, dstY1,
929 mask, filter);
930 if (mask == 0x0)
931 return;
932
933 mask = _mesa_meta_BlitFramebuffer(ctx, readFb, drawFb,
934 srcX0, srcY0, srcX1, srcY1,
935 dstX0, dstY0, dstX1, dstY1,
936 mask, filter);
937 if (mask == 0x0)
938 return;
939
940 if (brw->gen >= 8 && (mask & GL_STENCIL_BUFFER_BIT)) {
941 assert(!"Invalid blit");
942 }
943
944 /* Try using the BLT engine. */
945 mask = intel_blit_framebuffer_with_blitter(ctx, readFb, drawFb,
946 srcX0, srcY0, srcX1, srcY1,
947 dstX0, dstY0, dstX1, dstY1,
948 mask);
949 if (mask == 0x0)
950 return;
951
952 _swrast_BlitFramebuffer(ctx, readFb, drawFb,
953 srcX0, srcY0, srcX1, srcY1,
954 dstX0, dstY0, dstX1, dstY1,
955 mask, filter);
956 }
957
958 /**
959 * Does the renderbuffer have hiz enabled?
960 */
961 bool
962 intel_renderbuffer_has_hiz(struct intel_renderbuffer *irb)
963 {
964 return intel_miptree_level_has_hiz(irb->mt, irb->mt_level);
965 }
966
967 void
968 intel_renderbuffer_move_to_temp(struct brw_context *brw,
969 struct intel_renderbuffer *irb,
970 bool invalidate)
971 {
972 struct gl_renderbuffer *rb =&irb->Base.Base;
973 struct intel_texture_image *intel_image = intel_texture_image(rb->TexImage);
974 struct intel_mipmap_tree *new_mt;
975 int width, height, depth;
976
977 uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD |
978 MIPTREE_LAYOUT_TILING_ANY;
979
980 intel_get_image_dims(rb->TexImage, &width, &height, &depth);
981
982 assert(irb->align_wa_mt == NULL);
983 new_mt = intel_miptree_create(brw, GL_TEXTURE_2D,
984 intel_image->base.Base.TexFormat,
985 0, 0,
986 width, height, 1,
987 irb->mt->num_samples,
988 layout_flags);
989
990 if (!invalidate)
991 intel_miptree_copy_slice(brw, intel_image->mt,
992 intel_image->base.Base.Level, irb->mt_layer,
993 new_mt, 0, 0);
994
995 intel_miptree_reference(&irb->align_wa_mt, new_mt);
996 intel_miptree_release(&new_mt);
997
998 irb->draw_x = 0;
999 irb->draw_y = 0;
1000 }
1001
1002 void
1003 brw_render_cache_set_clear(struct brw_context *brw)
1004 {
1005 struct set_entry *entry;
1006
1007 set_foreach(brw->render_cache, entry) {
1008 _mesa_set_remove(brw->render_cache, entry);
1009 }
1010 }
1011
1012 void
1013 brw_render_cache_set_add_bo(struct brw_context *brw, struct brw_bo *bo)
1014 {
1015 _mesa_set_add(brw->render_cache, bo);
1016 }
1017
1018 /**
1019 * Emits an appropriate flush for a BO if it has been rendered to within the
1020 * same batchbuffer as a read that's about to be emitted.
1021 *
1022 * The GPU has separate, incoherent caches for the render cache and the
1023 * sampler cache, along with other caches. Usually data in the different
1024 * caches don't interact (e.g. we don't render to our driver-generated
1025 * immediate constant data), but for render-to-texture in FBOs we definitely
1026 * do. When a batchbuffer is flushed, the kernel will ensure that everything
1027 * necessary is flushed before another use of that BO, but for reuse from
1028 * different caches within a batchbuffer, it's all our responsibility.
1029 */
1030 void
1031 brw_render_cache_set_check_flush(struct brw_context *brw, struct brw_bo *bo)
1032 {
1033 if (!_mesa_set_search(brw->render_cache, bo))
1034 return;
1035
1036 if (brw->gen >= 6) {
1037 brw_emit_pipe_control_flush(brw,
1038 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
1039 PIPE_CONTROL_RENDER_TARGET_FLUSH |
1040 PIPE_CONTROL_CS_STALL);
1041
1042 brw_emit_pipe_control_flush(brw,
1043 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1044 PIPE_CONTROL_CONST_CACHE_INVALIDATE);
1045 } else {
1046 brw_emit_mi_flush(brw);
1047 }
1048
1049 brw_render_cache_set_clear(brw);
1050 }
1051
1052 /**
1053 * Do one-time context initializations related to GL_EXT_framebuffer_object.
1054 * Hook in device driver functions.
1055 */
1056 void
1057 intel_fbo_init(struct brw_context *brw)
1058 {
1059 struct dd_function_table *dd = &brw->ctx.Driver;
1060 dd->NewRenderbuffer = intel_new_renderbuffer;
1061 dd->MapRenderbuffer = intel_map_renderbuffer;
1062 dd->UnmapRenderbuffer = intel_unmap_renderbuffer;
1063 dd->RenderTexture = intel_render_texture;
1064 dd->ValidateFramebuffer = intel_validate_framebuffer;
1065 dd->BlitFramebuffer = intel_blit_framebuffer;
1066 dd->EGLImageTargetRenderbufferStorage =
1067 intel_image_target_renderbuffer_storage;
1068
1069 brw->render_cache = _mesa_set_create(brw, _mesa_hash_pointer,
1070 _mesa_key_pointer_equal);
1071 }