i965/miptree: Use num_samples of 1 instead of 0 for single-sampled
[mesa.git] / src / mesa / drivers / dri / i965 / intel_fbo.c
1 /*
2 * Copyright 2006 VMware, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "main/enums.h"
27 #include "main/imports.h"
28 #include "main/macros.h"
29 #include "main/mtypes.h"
30 #include "main/fbobject.h"
31 #include "main/framebuffer.h"
32 #include "main/renderbuffer.h"
33 #include "main/context.h"
34 #include "main/teximage.h"
35 #include "main/image.h"
36 #include "main/condrender.h"
37 #include "util/hash_table.h"
38 #include "util/set.h"
39
40 #include "swrast/swrast.h"
41 #include "drivers/common/meta.h"
42
43 #include "intel_batchbuffer.h"
44 #include "intel_buffers.h"
45 #include "intel_blit.h"
46 #include "intel_fbo.h"
47 #include "intel_mipmap_tree.h"
48 #include "intel_image.h"
49 #include "intel_screen.h"
50 #include "intel_tex.h"
51 #include "brw_context.h"
52 #include "brw_defines.h"
53
54 #define FILE_DEBUG_FLAG DEBUG_FBO
55
56 /** Called by gl_renderbuffer::Delete() */
57 static void
58 intel_delete_renderbuffer(struct gl_context *ctx, struct gl_renderbuffer *rb)
59 {
60 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
61
62 assert(irb);
63
64 intel_miptree_release(&irb->mt);
65 intel_miptree_release(&irb->singlesample_mt);
66
67 _mesa_delete_renderbuffer(ctx, rb);
68 }
69
70 /**
71 * \brief Downsample a winsys renderbuffer from mt to singlesample_mt.
72 *
73 * If the miptree needs no downsample, then skip.
74 */
75 void
76 intel_renderbuffer_downsample(struct brw_context *brw,
77 struct intel_renderbuffer *irb)
78 {
79 if (!irb->need_downsample)
80 return;
81 intel_miptree_updownsample(brw, irb->mt, irb->singlesample_mt);
82 irb->need_downsample = false;
83 }
84
85 /**
86 * \brief Upsample a winsys renderbuffer from singlesample_mt to mt.
87 *
88 * The upsample is done unconditionally.
89 */
90 void
91 intel_renderbuffer_upsample(struct brw_context *brw,
92 struct intel_renderbuffer *irb)
93 {
94 assert(!irb->need_downsample);
95
96 intel_miptree_updownsample(brw, irb->singlesample_mt, irb->mt);
97 }
98
99 /**
100 * \see dd_function_table::MapRenderbuffer
101 */
102 static void
103 intel_map_renderbuffer(struct gl_context *ctx,
104 struct gl_renderbuffer *rb,
105 GLuint x, GLuint y, GLuint w, GLuint h,
106 GLbitfield mode,
107 GLubyte **out_map,
108 GLint *out_stride)
109 {
110 struct brw_context *brw = brw_context(ctx);
111 struct swrast_renderbuffer *srb = (struct swrast_renderbuffer *)rb;
112 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
113 struct intel_mipmap_tree *mt;
114 void *map;
115 ptrdiff_t stride;
116
117 if (srb->Buffer) {
118 /* this is a malloc'd renderbuffer (accum buffer), not an irb */
119 GLint bpp = _mesa_get_format_bytes(rb->Format);
120 GLint rowStride = srb->RowStride;
121 *out_map = (GLubyte *) srb->Buffer + y * rowStride + x * bpp;
122 *out_stride = rowStride;
123 return;
124 }
125
126 intel_prepare_render(brw);
127
128 /* The MapRenderbuffer API should always return a single-sampled mapping.
129 * The case we are asked to map multisampled RBs is in glReadPixels() (or
130 * swrast paths like glCopyTexImage()) from a window-system MSAA buffer,
131 * and GL expects an automatic resolve to happen.
132 *
133 * If it's a color miptree, there is a ->singlesample_mt which wraps the
134 * actual window system renderbuffer (which we may resolve to at any time),
135 * while the miptree itself is our driver-private allocation. If it's a
136 * depth or stencil miptree, we have a private MSAA buffer and no shared
137 * singlesample buffer, and since we don't expect anybody to ever actually
138 * resolve it, we just make a temporary singlesample buffer now when we
139 * have to.
140 */
141 if (rb->NumSamples > 1) {
142 if (!irb->singlesample_mt) {
143 irb->singlesample_mt =
144 intel_miptree_create_for_renderbuffer(brw, irb->mt->format,
145 rb->Width, rb->Height,
146 1 /*num_samples*/);
147 if (!irb->singlesample_mt)
148 goto fail;
149 irb->singlesample_mt_is_tmp = true;
150 irb->need_downsample = true;
151 }
152
153 intel_renderbuffer_downsample(brw, irb);
154 mt = irb->singlesample_mt;
155
156 irb->need_map_upsample = mode & GL_MAP_WRITE_BIT;
157 } else {
158 mt = irb->mt;
159 }
160
161 /* For a window-system renderbuffer, we need to flip the mapping we receive
162 * upside-down. So we need to ask for a rectangle on flipped vertically, and
163 * we then return a pointer to the bottom of it with a negative stride.
164 */
165 if (rb->Name == 0) {
166 y = rb->Height - y - h;
167 }
168
169 intel_miptree_map(brw, mt, irb->mt_level, irb->mt_layer,
170 x, y, w, h, mode, &map, &stride);
171
172 if (rb->Name == 0) {
173 map += (h - 1) * stride;
174 stride = -stride;
175 }
176
177 DBG("%s: rb %d (%s) mt mapped: (%d, %d) (%dx%d) -> %p/%"PRIdPTR"\n",
178 __func__, rb->Name, _mesa_get_format_name(rb->Format),
179 x, y, w, h, map, stride);
180
181 *out_map = map;
182 *out_stride = stride;
183 return;
184
185 fail:
186 *out_map = NULL;
187 *out_stride = 0;
188 }
189
190 /**
191 * \see dd_function_table::UnmapRenderbuffer
192 */
193 static void
194 intel_unmap_renderbuffer(struct gl_context *ctx,
195 struct gl_renderbuffer *rb)
196 {
197 struct brw_context *brw = brw_context(ctx);
198 struct swrast_renderbuffer *srb = (struct swrast_renderbuffer *)rb;
199 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
200 struct intel_mipmap_tree *mt;
201
202 DBG("%s: rb %d (%s)\n", __func__,
203 rb->Name, _mesa_get_format_name(rb->Format));
204
205 if (srb->Buffer) {
206 /* this is a malloc'd renderbuffer (accum buffer) */
207 /* nothing to do */
208 return;
209 }
210
211 if (rb->NumSamples > 1) {
212 mt = irb->singlesample_mt;
213 } else {
214 mt = irb->mt;
215 }
216
217 intel_miptree_unmap(brw, mt, irb->mt_level, irb->mt_layer);
218
219 if (irb->need_map_upsample) {
220 intel_renderbuffer_upsample(brw, irb);
221 irb->need_map_upsample = false;
222 }
223
224 if (irb->singlesample_mt_is_tmp)
225 intel_miptree_release(&irb->singlesample_mt);
226 }
227
228
229 /**
230 * Round up the requested multisample count to the next supported sample size.
231 */
232 unsigned
233 intel_quantize_num_samples(struct intel_screen *intel, unsigned num_samples)
234 {
235 const int *msaa_modes = intel_supported_msaa_modes(intel);
236 int quantized_samples = 0;
237
238 for (int i = 0; msaa_modes[i] != -1; ++i) {
239 if (msaa_modes[i] >= num_samples)
240 quantized_samples = msaa_modes[i];
241 else
242 break;
243 }
244
245 return quantized_samples;
246 }
247
248 static mesa_format
249 intel_renderbuffer_format(struct gl_context * ctx, GLenum internalFormat)
250 {
251 struct brw_context *brw = brw_context(ctx);
252
253 switch (internalFormat) {
254 default:
255 /* Use the same format-choice logic as for textures.
256 * Renderbuffers aren't any different from textures for us,
257 * except they're less useful because you can't texture with
258 * them.
259 */
260 return ctx->Driver.ChooseTextureFormat(ctx, GL_TEXTURE_2D,
261 internalFormat,
262 GL_NONE, GL_NONE);
263 break;
264 case GL_STENCIL_INDEX:
265 case GL_STENCIL_INDEX1_EXT:
266 case GL_STENCIL_INDEX4_EXT:
267 case GL_STENCIL_INDEX8_EXT:
268 case GL_STENCIL_INDEX16_EXT:
269 /* These aren't actual texture formats, so force them here. */
270 if (brw->has_separate_stencil) {
271 return MESA_FORMAT_S_UINT8;
272 } else {
273 assert(!brw->must_use_separate_stencil);
274 return MESA_FORMAT_Z24_UNORM_S8_UINT;
275 }
276 }
277 }
278
279 static GLboolean
280 intel_alloc_private_renderbuffer_storage(struct gl_context * ctx, struct gl_renderbuffer *rb,
281 GLenum internalFormat,
282 GLuint width, GLuint height)
283 {
284 struct brw_context *brw = brw_context(ctx);
285 struct intel_screen *screen = brw->screen;
286 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
287
288 assert(rb->Format != MESA_FORMAT_NONE);
289
290 rb->NumSamples = intel_quantize_num_samples(screen, rb->NumSamples);
291 rb->Width = width;
292 rb->Height = height;
293 rb->_BaseFormat = _mesa_get_format_base_format(rb->Format);
294
295 intel_miptree_release(&irb->mt);
296
297 DBG("%s: %s: %s (%dx%d)\n", __func__,
298 _mesa_enum_to_string(internalFormat),
299 _mesa_get_format_name(rb->Format), width, height);
300
301 if (width == 0 || height == 0)
302 return true;
303
304 irb->mt = intel_miptree_create_for_renderbuffer(brw, rb->Format,
305 width, height,
306 MAX2(rb->NumSamples, 1));
307 if (!irb->mt)
308 return false;
309
310 irb->layer_count = 1;
311
312 return true;
313 }
314
315 /**
316 * Called via glRenderbufferStorageEXT() to set the format and allocate
317 * storage for a user-created renderbuffer.
318 */
319 static GLboolean
320 intel_alloc_renderbuffer_storage(struct gl_context * ctx, struct gl_renderbuffer *rb,
321 GLenum internalFormat,
322 GLuint width, GLuint height)
323 {
324 rb->Format = intel_renderbuffer_format(ctx, internalFormat);
325 return intel_alloc_private_renderbuffer_storage(ctx, rb, internalFormat, width, height);
326 }
327
328 static void
329 intel_image_target_renderbuffer_storage(struct gl_context *ctx,
330 struct gl_renderbuffer *rb,
331 void *image_handle)
332 {
333 struct brw_context *brw = brw_context(ctx);
334 struct intel_renderbuffer *irb;
335 __DRIscreen *dri_screen = brw->screen->driScrnPriv;
336 __DRIimage *image;
337
338 image = dri_screen->dri2.image->lookupEGLImage(dri_screen, image_handle,
339 dri_screen->loaderPrivate);
340 if (image == NULL)
341 return;
342
343 if (image->planar_format && image->planar_format->nplanes > 1) {
344 _mesa_error(ctx, GL_INVALID_OPERATION,
345 "glEGLImageTargetRenderbufferStorage(planar buffers are not "
346 "supported as render targets.)");
347 return;
348 }
349
350 /* __DRIimage is opaque to the core so it has to be checked here */
351 if (!brw->mesa_format_supports_render[image->format]) {
352 _mesa_error(ctx, GL_INVALID_OPERATION,
353 "glEGLImageTargetRenderbufferStorage(unsupported image format)");
354 return;
355 }
356
357 irb = intel_renderbuffer(rb);
358 intel_miptree_release(&irb->mt);
359
360 /* Disable creation of the miptree's aux buffers because the driver exposes
361 * no EGL API to manage them. That is, there is no API for resolving the aux
362 * buffer's content to the main buffer nor for invalidating the aux buffer's
363 * content.
364 */
365 irb->mt = intel_miptree_create_for_dri_image(brw, image, GL_TEXTURE_2D,
366 ISL_COLORSPACE_NONE, false);
367 if (!irb->mt)
368 return;
369
370 rb->InternalFormat = image->internal_format;
371 rb->Width = image->width;
372 rb->Height = image->height;
373 rb->Format = image->format;
374 rb->_BaseFormat = _mesa_get_format_base_format(image->format);
375 rb->NeedsFinishRenderTexture = true;
376 irb->layer_count = 1;
377 }
378
379 /**
380 * Called by _mesa_resize_framebuffer() for each hardware renderbuffer when a
381 * window system framebuffer is resized.
382 *
383 * Any actual buffer reallocations for hardware renderbuffers (which would
384 * have triggered _mesa_resize_framebuffer()) were done by
385 * intel_process_dri2_buffer().
386 */
387 static GLboolean
388 intel_alloc_window_storage(struct gl_context * ctx, struct gl_renderbuffer *rb,
389 GLenum internalFormat, GLuint width, GLuint height)
390 {
391 (void) ctx;
392 assert(rb->Name == 0);
393 rb->Width = width;
394 rb->Height = height;
395 rb->InternalFormat = internalFormat;
396
397 return true;
398 }
399
400 /** Dummy function for gl_renderbuffer::AllocStorage() */
401 static GLboolean
402 intel_nop_alloc_storage(struct gl_context * ctx, struct gl_renderbuffer *rb,
403 GLenum internalFormat, GLuint width, GLuint height)
404 {
405 (void) rb;
406 (void) internalFormat;
407 (void) width;
408 (void) height;
409 _mesa_problem(ctx, "intel_nop_alloc_storage should never be called.");
410 return false;
411 }
412
413 /**
414 * Create an intel_renderbuffer for a __DRIdrawable. This function is
415 * unrelated to GL renderbuffers (that is, those created by
416 * glGenRenderbuffers).
417 *
418 * \param num_samples must be quantized.
419 */
420 struct intel_renderbuffer *
421 intel_create_winsys_renderbuffer(struct intel_screen *screen,
422 mesa_format format, unsigned num_samples)
423 {
424 struct intel_renderbuffer *irb = CALLOC_STRUCT(intel_renderbuffer);
425 if (!irb)
426 return NULL;
427
428 struct gl_renderbuffer *rb = &irb->Base.Base;
429 irb->layer_count = 1;
430
431 _mesa_init_renderbuffer(rb, 0);
432 rb->ClassID = INTEL_RB_CLASS;
433 rb->NumSamples = num_samples;
434
435 /* The base format and internal format must be derived from the user-visible
436 * format (that is, the gl_config's format), even if we internally use
437 * choose a different format for the renderbuffer. Otherwise, rendering may
438 * use incorrect channel write masks.
439 */
440 rb->_BaseFormat = _mesa_get_format_base_format(format);
441 rb->InternalFormat = rb->_BaseFormat;
442
443 rb->Format = format;
444 if (!screen->mesa_format_supports_render[rb->Format]) {
445 /* The glRenderbufferStorage paths in core Mesa detect if the driver
446 * does not support the user-requested format, and then searches for
447 * a falback format. The DRI code bypasses core Mesa, though. So we do
448 * the fallbacks here.
449 *
450 * We must support MESA_FORMAT_R8G8B8X8 on Android because the Android
451 * framework requires HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces.
452 */
453 rb->Format = _mesa_format_fallback_rgbx_to_rgba(rb->Format);
454 assert(screen->mesa_format_supports_render[rb->Format]);
455 }
456
457 /* intel-specific methods */
458 rb->Delete = intel_delete_renderbuffer;
459 rb->AllocStorage = intel_alloc_window_storage;
460
461 return irb;
462 }
463
464 /**
465 * Private window-system buffers (as opposed to ones shared with the display
466 * server created with intel_create_winsys_renderbuffer()) are most similar in their
467 * handling to user-created renderbuffers, but they have a resize handler that
468 * may be called at intel_update_renderbuffers() time.
469 *
470 * \param num_samples must be quantized.
471 */
472 struct intel_renderbuffer *
473 intel_create_private_renderbuffer(struct intel_screen *screen,
474 mesa_format format, unsigned num_samples)
475 {
476 struct intel_renderbuffer *irb;
477
478 irb = intel_create_winsys_renderbuffer(screen, format, num_samples);
479 irb->Base.Base.AllocStorage = intel_alloc_private_renderbuffer_storage;
480
481 return irb;
482 }
483
484 /**
485 * Create a new renderbuffer object.
486 * Typically called via glBindRenderbufferEXT().
487 */
488 static struct gl_renderbuffer *
489 intel_new_renderbuffer(struct gl_context * ctx, GLuint name)
490 {
491 struct intel_renderbuffer *irb;
492 struct gl_renderbuffer *rb;
493
494 irb = CALLOC_STRUCT(intel_renderbuffer);
495 if (!irb) {
496 _mesa_error(ctx, GL_OUT_OF_MEMORY, "creating renderbuffer");
497 return NULL;
498 }
499
500 rb = &irb->Base.Base;
501
502 _mesa_init_renderbuffer(rb, name);
503 rb->ClassID = INTEL_RB_CLASS;
504
505 /* intel-specific methods */
506 rb->Delete = intel_delete_renderbuffer;
507 rb->AllocStorage = intel_alloc_renderbuffer_storage;
508 /* span routines set in alloc_storage function */
509
510 return rb;
511 }
512
513 static bool
514 intel_renderbuffer_update_wrapper(struct brw_context *brw,
515 struct intel_renderbuffer *irb,
516 struct gl_texture_image *image,
517 uint32_t layer,
518 bool layered)
519 {
520 struct gl_renderbuffer *rb = &irb->Base.Base;
521 struct intel_texture_image *intel_image = intel_texture_image(image);
522 struct intel_mipmap_tree *mt = intel_image->mt;
523 int level = image->Level;
524
525 rb->AllocStorage = intel_nop_alloc_storage;
526
527 /* adjust for texture view parameters */
528 layer += image->TexObject->MinLayer;
529 level += image->TexObject->MinLevel;
530
531 intel_miptree_check_level_layer(mt, level, layer);
532 irb->mt_level = level;
533 irb->mt_layer = layer;
534
535 const unsigned layer_multiplier =
536 mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY ? mt->num_samples : 1;
537
538 if (!layered) {
539 irb->layer_count = 1;
540 } else if (mt->target != GL_TEXTURE_3D && image->TexObject->NumLayers > 0) {
541 irb->layer_count = image->TexObject->NumLayers;
542 } else {
543 irb->layer_count = mt->level[level].depth / layer_multiplier;
544 }
545
546 intel_miptree_reference(&irb->mt, mt);
547
548 intel_renderbuffer_set_draw_offset(irb);
549
550 return true;
551 }
552
553 void
554 intel_renderbuffer_set_draw_offset(struct intel_renderbuffer *irb)
555 {
556 unsigned int dst_x, dst_y;
557
558 /* compute offset of the particular 2D image within the texture region */
559 intel_miptree_get_image_offset(irb->mt,
560 irb->mt_level,
561 irb->mt_layer,
562 &dst_x, &dst_y);
563
564 irb->draw_x = dst_x;
565 irb->draw_y = dst_y;
566 }
567
568 /**
569 * Called by glFramebufferTexture[123]DEXT() (and other places) to
570 * prepare for rendering into texture memory. This might be called
571 * many times to choose different texture levels, cube faces, etc
572 * before intel_finish_render_texture() is ever called.
573 */
574 static void
575 intel_render_texture(struct gl_context * ctx,
576 struct gl_framebuffer *fb,
577 struct gl_renderbuffer_attachment *att)
578 {
579 struct brw_context *brw = brw_context(ctx);
580 struct gl_renderbuffer *rb = att->Renderbuffer;
581 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
582 struct gl_texture_image *image = rb->TexImage;
583 struct intel_texture_image *intel_image = intel_texture_image(image);
584 struct intel_mipmap_tree *mt = intel_image->mt;
585 int layer;
586
587 (void) fb;
588
589 if (att->CubeMapFace > 0) {
590 assert(att->Zoffset == 0);
591 layer = att->CubeMapFace;
592 } else {
593 layer = att->Zoffset;
594 }
595
596 if (!intel_image->mt) {
597 /* Fallback on drawing to a texture that doesn't have a miptree
598 * (has a border, width/height 0, etc.)
599 */
600 _swrast_render_texture(ctx, fb, att);
601 return;
602 }
603
604 intel_miptree_check_level_layer(mt, att->TextureLevel, layer);
605
606 if (!intel_renderbuffer_update_wrapper(brw, irb, image, layer, att->Layered)) {
607 _swrast_render_texture(ctx, fb, att);
608 return;
609 }
610
611 DBG("Begin render %s texture tex=%u w=%d h=%d d=%d refcount=%d\n",
612 _mesa_get_format_name(image->TexFormat),
613 att->Texture->Name, image->Width, image->Height, image->Depth,
614 rb->RefCount);
615 }
616
617
618 #define fbo_incomplete(fb, ...) do { \
619 static GLuint msg_id = 0; \
620 if (unlikely(ctx->Const.ContextFlags & GL_CONTEXT_FLAG_DEBUG_BIT)) { \
621 _mesa_gl_debug(ctx, &msg_id, \
622 MESA_DEBUG_SOURCE_API, \
623 MESA_DEBUG_TYPE_OTHER, \
624 MESA_DEBUG_SEVERITY_MEDIUM, \
625 __VA_ARGS__); \
626 } \
627 DBG(__VA_ARGS__); \
628 fb->_Status = GL_FRAMEBUFFER_UNSUPPORTED; \
629 } while (0)
630
631 /**
632 * Do additional "completeness" testing of a framebuffer object.
633 */
634 static void
635 intel_validate_framebuffer(struct gl_context *ctx, struct gl_framebuffer *fb)
636 {
637 struct brw_context *brw = brw_context(ctx);
638 struct intel_renderbuffer *depthRb =
639 intel_get_renderbuffer(fb, BUFFER_DEPTH);
640 struct intel_renderbuffer *stencilRb =
641 intel_get_renderbuffer(fb, BUFFER_STENCIL);
642 struct intel_mipmap_tree *depth_mt = NULL, *stencil_mt = NULL;
643 unsigned i;
644
645 DBG("%s() on fb %p (%s)\n", __func__,
646 fb, (fb == ctx->DrawBuffer ? "drawbuffer" :
647 (fb == ctx->ReadBuffer ? "readbuffer" : "other buffer")));
648
649 if (depthRb)
650 depth_mt = depthRb->mt;
651 if (stencilRb) {
652 stencil_mt = stencilRb->mt;
653 if (stencil_mt->stencil_mt)
654 stencil_mt = stencil_mt->stencil_mt;
655 }
656
657 if (depth_mt && stencil_mt) {
658 if (brw->gen >= 6) {
659 unsigned d_width, d_height, d_depth;
660 unsigned s_width, s_height, s_depth;
661
662 if (depth_mt->surf.size > 0) {
663 d_width = depth_mt->surf.phys_level0_sa.width;
664 d_height = depth_mt->surf.phys_level0_sa.height;
665 d_depth = depth_mt->surf.dim == ISL_SURF_DIM_3D ?
666 depth_mt->surf.phys_level0_sa.depth :
667 depth_mt->surf.phys_level0_sa.array_len;
668 } else {
669 d_width = depth_mt->physical_width0;
670 d_height = depth_mt->physical_height0;
671 d_depth = depth_mt->physical_depth0;
672 }
673
674 if (stencil_mt->surf.size > 0) {
675 s_width = stencil_mt->surf.phys_level0_sa.width;
676 s_height = stencil_mt->surf.phys_level0_sa.height;
677 s_depth = stencil_mt->surf.dim == ISL_SURF_DIM_3D ?
678 stencil_mt->surf.phys_level0_sa.depth :
679 stencil_mt->surf.phys_level0_sa.array_len;
680 } else {
681 s_width = stencil_mt->physical_width0;
682 s_height = stencil_mt->physical_height0;
683 s_depth = stencil_mt->physical_depth0;
684 }
685
686 /* For gen >= 6, we are using the lod/minimum-array-element fields
687 * and supporting layered rendering. This means that we must restrict
688 * the depth & stencil attachments to match in various more retrictive
689 * ways. (width, height, depth, LOD and layer)
690 */
691 if (d_width != s_width ||
692 d_height != s_height ||
693 d_depth != s_depth ||
694 depthRb->mt_level != stencilRb->mt_level ||
695 depthRb->mt_layer != stencilRb->mt_layer) {
696 fbo_incomplete(fb,
697 "FBO incomplete: depth and stencil must match in"
698 "width, height, depth, LOD and layer\n");
699 }
700 }
701 if (depth_mt == stencil_mt) {
702 /* For true packed depth/stencil (not faked on prefers-separate-stencil
703 * hardware) we need to be sure they're the same level/layer, since
704 * we'll be emitting a single packet describing the packed setup.
705 */
706 if (depthRb->mt_level != stencilRb->mt_level ||
707 depthRb->mt_layer != stencilRb->mt_layer) {
708 fbo_incomplete(fb,
709 "FBO incomplete: depth image level/layer %d/%d != "
710 "stencil image %d/%d\n",
711 depthRb->mt_level,
712 depthRb->mt_layer,
713 stencilRb->mt_level,
714 stencilRb->mt_layer);
715 }
716 } else {
717 if (!brw->has_separate_stencil) {
718 fbo_incomplete(fb, "FBO incomplete: separate stencil "
719 "unsupported\n");
720 }
721 if (stencil_mt->format != MESA_FORMAT_S_UINT8) {
722 fbo_incomplete(fb, "FBO incomplete: separate stencil is %s "
723 "instead of S8\n",
724 _mesa_get_format_name(stencil_mt->format));
725 }
726 if (brw->gen < 7 && !intel_renderbuffer_has_hiz(depthRb)) {
727 /* Before Gen7, separate depth and stencil buffers can be used
728 * only if HiZ is enabled. From the Sandybridge PRM, Volume 2,
729 * Part 1, Bit 3DSTATE_DEPTH_BUFFER.SeparateStencilBufferEnable:
730 * [DevSNB]: This field must be set to the same value (enabled
731 * or disabled) as Hierarchical Depth Buffer Enable.
732 */
733 fbo_incomplete(fb, "FBO incomplete: separate stencil "
734 "without HiZ\n");
735 }
736 }
737 }
738
739 for (i = 0; i < ARRAY_SIZE(fb->Attachment); i++) {
740 struct gl_renderbuffer *rb;
741 struct intel_renderbuffer *irb;
742
743 if (fb->Attachment[i].Type == GL_NONE)
744 continue;
745
746 /* A supported attachment will have a Renderbuffer set either
747 * from being a Renderbuffer or being a texture that got the
748 * intel_wrap_texture() treatment.
749 */
750 rb = fb->Attachment[i].Renderbuffer;
751 if (rb == NULL) {
752 fbo_incomplete(fb, "FBO incomplete: attachment without "
753 "renderbuffer\n");
754 continue;
755 }
756
757 if (fb->Attachment[i].Type == GL_TEXTURE) {
758 if (rb->TexImage->Border) {
759 fbo_incomplete(fb, "FBO incomplete: texture with border\n");
760 continue;
761 }
762 }
763
764 irb = intel_renderbuffer(rb);
765 if (irb == NULL) {
766 fbo_incomplete(fb, "FBO incomplete: software rendering "
767 "renderbuffer\n");
768 continue;
769 }
770
771 if (!brw_render_target_supported(brw, rb)) {
772 fbo_incomplete(fb, "FBO incomplete: Unsupported HW "
773 "texture/renderbuffer format attached: %s\n",
774 _mesa_get_format_name(intel_rb_format(irb)));
775 }
776 }
777 }
778
779 /**
780 * Try to do a glBlitFramebuffer using glCopyTexSubImage2D
781 * We can do this when the dst renderbuffer is actually a texture and
782 * there is no scaling, mirroring or scissoring.
783 *
784 * \return new buffer mask indicating the buffers left to blit using the
785 * normal path.
786 */
787 static GLbitfield
788 intel_blit_framebuffer_with_blitter(struct gl_context *ctx,
789 const struct gl_framebuffer *readFb,
790 const struct gl_framebuffer *drawFb,
791 GLint srcX0, GLint srcY0,
792 GLint srcX1, GLint srcY1,
793 GLint dstX0, GLint dstY0,
794 GLint dstX1, GLint dstY1,
795 GLbitfield mask)
796 {
797 struct brw_context *brw = brw_context(ctx);
798
799 /* Sync up the state of window system buffers. We need to do this before
800 * we go looking for the buffers.
801 */
802 intel_prepare_render(brw);
803
804 if (mask & GL_COLOR_BUFFER_BIT) {
805 unsigned i;
806 struct gl_renderbuffer *src_rb = readFb->_ColorReadBuffer;
807 struct intel_renderbuffer *src_irb = intel_renderbuffer(src_rb);
808
809 if (!src_irb) {
810 perf_debug("glBlitFramebuffer(): missing src renderbuffer. "
811 "Falling back to software rendering.\n");
812 return mask;
813 }
814
815 /* If the source and destination are the same size with no mirroring,
816 * the rectangles are within the size of the texture and there is no
817 * scissor, then we can probably use the blit engine.
818 */
819 if (!(srcX0 - srcX1 == dstX0 - dstX1 &&
820 srcY0 - srcY1 == dstY0 - dstY1 &&
821 srcX1 >= srcX0 &&
822 srcY1 >= srcY0 &&
823 srcX0 >= 0 && srcX1 <= readFb->Width &&
824 srcY0 >= 0 && srcY1 <= readFb->Height &&
825 dstX0 >= 0 && dstX1 <= drawFb->Width &&
826 dstY0 >= 0 && dstY1 <= drawFb->Height &&
827 !(ctx->Scissor.EnableFlags))) {
828 perf_debug("glBlitFramebuffer(): non-1:1 blit. "
829 "Falling back to software rendering.\n");
830 return mask;
831 }
832
833 /* Blit to all active draw buffers. We don't do any pre-checking,
834 * because we assume that copying to MRTs is rare, and failure midway
835 * through copying is even more rare. Even if it was to occur, it's
836 * safe to let meta start the copy over from scratch, because
837 * glBlitFramebuffer completely overwrites the destination pixels, and
838 * results are undefined if any destination pixels have a dependency on
839 * source pixels.
840 */
841 for (i = 0; i < drawFb->_NumColorDrawBuffers; i++) {
842 struct gl_renderbuffer *dst_rb = drawFb->_ColorDrawBuffers[i];
843 struct intel_renderbuffer *dst_irb = intel_renderbuffer(dst_rb);
844
845 if (!dst_irb) {
846 perf_debug("glBlitFramebuffer(): missing dst renderbuffer. "
847 "Falling back to software rendering.\n");
848 return mask;
849 }
850
851 if (ctx->Color.sRGBEnabled &&
852 _mesa_get_format_color_encoding(src_irb->mt->format) !=
853 _mesa_get_format_color_encoding(dst_irb->mt->format)) {
854 perf_debug("glBlitFramebuffer() with sRGB conversion cannot be "
855 "handled by BLT path.\n");
856 return mask;
857 }
858
859 if (!intel_miptree_blit(brw,
860 src_irb->mt,
861 src_irb->mt_level, src_irb->mt_layer,
862 srcX0, srcY0, src_rb->Name == 0,
863 dst_irb->mt,
864 dst_irb->mt_level, dst_irb->mt_layer,
865 dstX0, dstY0, dst_rb->Name == 0,
866 dstX1 - dstX0, dstY1 - dstY0, GL_COPY)) {
867 perf_debug("glBlitFramebuffer(): unknown blit failure. "
868 "Falling back to software rendering.\n");
869 return mask;
870 }
871 }
872
873 mask &= ~GL_COLOR_BUFFER_BIT;
874 }
875
876 return mask;
877 }
878
879 static void
880 intel_blit_framebuffer(struct gl_context *ctx,
881 struct gl_framebuffer *readFb,
882 struct gl_framebuffer *drawFb,
883 GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1,
884 GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
885 GLbitfield mask, GLenum filter)
886 {
887 struct brw_context *brw = brw_context(ctx);
888
889 /* Page 679 of OpenGL 4.4 spec says:
890 * "Added BlitFramebuffer to commands affected by conditional rendering in
891 * section 10.10 (Bug 9562)."
892 */
893 if (!_mesa_check_conditional_render(ctx))
894 return;
895
896 if (brw->gen < 6) {
897 /* On gen4-5, try BLT first.
898 *
899 * Gen4-5 have a single ring for both 3D and BLT operations, so there's
900 * no inter-ring synchronization issues like on Gen6+. It is apparently
901 * faster than using the 3D pipeline. Original Gen4 also has to rebase
902 * and copy miptree slices in order to render to unaligned locations.
903 */
904 mask = intel_blit_framebuffer_with_blitter(ctx, readFb, drawFb,
905 srcX0, srcY0, srcX1, srcY1,
906 dstX0, dstY0, dstX1, dstY1,
907 mask);
908 if (mask == 0x0)
909 return;
910 }
911
912 mask = brw_blorp_framebuffer(brw, readFb, drawFb,
913 srcX0, srcY0, srcX1, srcY1,
914 dstX0, dstY0, dstX1, dstY1,
915 mask, filter);
916 if (mask == 0x0)
917 return;
918
919 mask = _mesa_meta_BlitFramebuffer(ctx, readFb, drawFb,
920 srcX0, srcY0, srcX1, srcY1,
921 dstX0, dstY0, dstX1, dstY1,
922 mask, filter);
923 if (mask == 0x0)
924 return;
925
926 if (brw->gen >= 8 && (mask & GL_STENCIL_BUFFER_BIT)) {
927 assert(!"Invalid blit");
928 }
929
930 /* Try using the BLT engine. */
931 mask = intel_blit_framebuffer_with_blitter(ctx, readFb, drawFb,
932 srcX0, srcY0, srcX1, srcY1,
933 dstX0, dstY0, dstX1, dstY1,
934 mask);
935 if (mask == 0x0)
936 return;
937
938 _swrast_BlitFramebuffer(ctx, readFb, drawFb,
939 srcX0, srcY0, srcX1, srcY1,
940 dstX0, dstY0, dstX1, dstY1,
941 mask, filter);
942 }
943
944 /**
945 * Does the renderbuffer have hiz enabled?
946 */
947 bool
948 intel_renderbuffer_has_hiz(struct intel_renderbuffer *irb)
949 {
950 return intel_miptree_level_has_hiz(irb->mt, irb->mt_level);
951 }
952
953 void
954 intel_renderbuffer_move_to_temp(struct brw_context *brw,
955 struct intel_renderbuffer *irb,
956 bool invalidate)
957 {
958 struct gl_renderbuffer *rb =&irb->Base.Base;
959 struct intel_texture_image *intel_image = intel_texture_image(rb->TexImage);
960 struct intel_mipmap_tree *new_mt;
961 int width, height, depth;
962
963 uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD |
964 MIPTREE_LAYOUT_TILING_ANY;
965
966 intel_get_image_dims(rb->TexImage, &width, &height, &depth);
967
968 assert(irb->align_wa_mt == NULL);
969 new_mt = intel_miptree_create(brw, GL_TEXTURE_2D,
970 intel_image->base.Base.TexFormat,
971 0, 0,
972 width, height, 1,
973 irb->mt->num_samples,
974 layout_flags);
975
976 if (!invalidate)
977 intel_miptree_copy_slice(brw, intel_image->mt,
978 intel_image->base.Base.Level, irb->mt_layer,
979 new_mt, 0, 0);
980
981 intel_miptree_reference(&irb->align_wa_mt, new_mt);
982 intel_miptree_release(&new_mt);
983
984 irb->draw_x = 0;
985 irb->draw_y = 0;
986 }
987
988 void
989 brw_render_cache_set_clear(struct brw_context *brw)
990 {
991 struct set_entry *entry;
992
993 set_foreach(brw->render_cache, entry) {
994 _mesa_set_remove(brw->render_cache, entry);
995 }
996 }
997
998 void
999 brw_render_cache_set_add_bo(struct brw_context *brw, struct brw_bo *bo)
1000 {
1001 _mesa_set_add(brw->render_cache, bo);
1002 }
1003
1004 /**
1005 * Emits an appropriate flush for a BO if it has been rendered to within the
1006 * same batchbuffer as a read that's about to be emitted.
1007 *
1008 * The GPU has separate, incoherent caches for the render cache and the
1009 * sampler cache, along with other caches. Usually data in the different
1010 * caches don't interact (e.g. we don't render to our driver-generated
1011 * immediate constant data), but for render-to-texture in FBOs we definitely
1012 * do. When a batchbuffer is flushed, the kernel will ensure that everything
1013 * necessary is flushed before another use of that BO, but for reuse from
1014 * different caches within a batchbuffer, it's all our responsibility.
1015 */
1016 void
1017 brw_render_cache_set_check_flush(struct brw_context *brw, struct brw_bo *bo)
1018 {
1019 if (!_mesa_set_search(brw->render_cache, bo))
1020 return;
1021
1022 if (brw->gen >= 6) {
1023 brw_emit_pipe_control_flush(brw,
1024 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
1025 PIPE_CONTROL_RENDER_TARGET_FLUSH |
1026 PIPE_CONTROL_CS_STALL);
1027
1028 brw_emit_pipe_control_flush(brw,
1029 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1030 PIPE_CONTROL_CONST_CACHE_INVALIDATE);
1031 } else {
1032 brw_emit_mi_flush(brw);
1033 }
1034
1035 brw_render_cache_set_clear(brw);
1036 }
1037
1038 /**
1039 * Do one-time context initializations related to GL_EXT_framebuffer_object.
1040 * Hook in device driver functions.
1041 */
1042 void
1043 intel_fbo_init(struct brw_context *brw)
1044 {
1045 struct dd_function_table *dd = &brw->ctx.Driver;
1046 dd->NewRenderbuffer = intel_new_renderbuffer;
1047 dd->MapRenderbuffer = intel_map_renderbuffer;
1048 dd->UnmapRenderbuffer = intel_unmap_renderbuffer;
1049 dd->RenderTexture = intel_render_texture;
1050 dd->ValidateFramebuffer = intel_validate_framebuffer;
1051 dd->BlitFramebuffer = intel_blit_framebuffer;
1052 dd->EGLImageTargetRenderbufferStorage =
1053 intel_image_target_renderbuffer_storage;
1054
1055 brw->render_cache = _mesa_set_create(brw, _mesa_hash_pointer,
1056 _mesa_key_pointer_equal);
1057 }