i965: Don't bother with HiZ in renderbuffer_move_to_temp
[mesa.git] / src / mesa / drivers / dri / i965 / intel_fbo.c
1 /*
2 * Copyright 2006 VMware, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "main/enums.h"
27 #include "main/imports.h"
28 #include "main/macros.h"
29 #include "main/mtypes.h"
30 #include "main/fbobject.h"
31 #include "main/framebuffer.h"
32 #include "main/renderbuffer.h"
33 #include "main/context.h"
34 #include "main/teximage.h"
35 #include "main/image.h"
36 #include "main/condrender.h"
37 #include "util/hash_table.h"
38 #include "util/set.h"
39
40 #include "swrast/swrast.h"
41 #include "drivers/common/meta.h"
42
43 #include "intel_batchbuffer.h"
44 #include "intel_buffers.h"
45 #include "intel_blit.h"
46 #include "intel_fbo.h"
47 #include "intel_mipmap_tree.h"
48 #include "intel_image.h"
49 #include "intel_screen.h"
50 #include "intel_tex.h"
51 #include "brw_context.h"
52 #include "brw_defines.h"
53
54 #define FILE_DEBUG_FLAG DEBUG_FBO
55
56 /** Called by gl_renderbuffer::Delete() */
57 static void
58 intel_delete_renderbuffer(struct gl_context *ctx, struct gl_renderbuffer *rb)
59 {
60 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
61
62 assert(irb);
63
64 intel_miptree_release(&irb->mt);
65 intel_miptree_release(&irb->singlesample_mt);
66
67 _mesa_delete_renderbuffer(ctx, rb);
68 }
69
70 /**
71 * \brief Downsample a winsys renderbuffer from mt to singlesample_mt.
72 *
73 * If the miptree needs no downsample, then skip.
74 */
75 void
76 intel_renderbuffer_downsample(struct brw_context *brw,
77 struct intel_renderbuffer *irb)
78 {
79 if (!irb->need_downsample)
80 return;
81 intel_miptree_updownsample(brw, irb->mt, irb->singlesample_mt);
82 irb->need_downsample = false;
83 }
84
85 /**
86 * \brief Upsample a winsys renderbuffer from singlesample_mt to mt.
87 *
88 * The upsample is done unconditionally.
89 */
90 void
91 intel_renderbuffer_upsample(struct brw_context *brw,
92 struct intel_renderbuffer *irb)
93 {
94 assert(!irb->need_downsample);
95
96 intel_miptree_updownsample(brw, irb->singlesample_mt, irb->mt);
97 }
98
99 /**
100 * \see dd_function_table::MapRenderbuffer
101 */
102 static void
103 intel_map_renderbuffer(struct gl_context *ctx,
104 struct gl_renderbuffer *rb,
105 GLuint x, GLuint y, GLuint w, GLuint h,
106 GLbitfield mode,
107 GLubyte **out_map,
108 GLint *out_stride)
109 {
110 struct brw_context *brw = brw_context(ctx);
111 struct swrast_renderbuffer *srb = (struct swrast_renderbuffer *)rb;
112 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
113 struct intel_mipmap_tree *mt;
114 void *map;
115 ptrdiff_t stride;
116
117 if (srb->Buffer) {
118 /* this is a malloc'd renderbuffer (accum buffer), not an irb */
119 GLint bpp = _mesa_get_format_bytes(rb->Format);
120 GLint rowStride = srb->RowStride;
121 *out_map = (GLubyte *) srb->Buffer + y * rowStride + x * bpp;
122 *out_stride = rowStride;
123 return;
124 }
125
126 intel_prepare_render(brw);
127
128 /* The MapRenderbuffer API should always return a single-sampled mapping.
129 * The case we are asked to map multisampled RBs is in glReadPixels() (or
130 * swrast paths like glCopyTexImage()) from a window-system MSAA buffer,
131 * and GL expects an automatic resolve to happen.
132 *
133 * If it's a color miptree, there is a ->singlesample_mt which wraps the
134 * actual window system renderbuffer (which we may resolve to at any time),
135 * while the miptree itself is our driver-private allocation. If it's a
136 * depth or stencil miptree, we have a private MSAA buffer and no shared
137 * singlesample buffer, and since we don't expect anybody to ever actually
138 * resolve it, we just make a temporary singlesample buffer now when we
139 * have to.
140 */
141 if (rb->NumSamples > 1) {
142 if (!irb->singlesample_mt) {
143 irb->singlesample_mt =
144 intel_miptree_create_for_renderbuffer(brw, irb->mt->format,
145 rb->Width, rb->Height,
146 0 /*num_samples*/);
147 if (!irb->singlesample_mt)
148 goto fail;
149 irb->singlesample_mt_is_tmp = true;
150 irb->need_downsample = true;
151 }
152
153 intel_renderbuffer_downsample(brw, irb);
154 mt = irb->singlesample_mt;
155
156 irb->need_map_upsample = mode & GL_MAP_WRITE_BIT;
157 } else {
158 mt = irb->mt;
159 }
160
161 /* For a window-system renderbuffer, we need to flip the mapping we receive
162 * upside-down. So we need to ask for a rectangle on flipped vertically, and
163 * we then return a pointer to the bottom of it with a negative stride.
164 */
165 if (rb->Name == 0) {
166 y = rb->Height - y - h;
167 }
168
169 intel_miptree_map(brw, mt, irb->mt_level, irb->mt_layer,
170 x, y, w, h, mode, &map, &stride);
171
172 if (rb->Name == 0) {
173 map += (h - 1) * stride;
174 stride = -stride;
175 }
176
177 DBG("%s: rb %d (%s) mt mapped: (%d, %d) (%dx%d) -> %p/%"PRIdPTR"\n",
178 __func__, rb->Name, _mesa_get_format_name(rb->Format),
179 x, y, w, h, map, stride);
180
181 *out_map = map;
182 *out_stride = stride;
183 return;
184
185 fail:
186 *out_map = NULL;
187 *out_stride = 0;
188 }
189
190 /**
191 * \see dd_function_table::UnmapRenderbuffer
192 */
193 static void
194 intel_unmap_renderbuffer(struct gl_context *ctx,
195 struct gl_renderbuffer *rb)
196 {
197 struct brw_context *brw = brw_context(ctx);
198 struct swrast_renderbuffer *srb = (struct swrast_renderbuffer *)rb;
199 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
200 struct intel_mipmap_tree *mt;
201
202 DBG("%s: rb %d (%s)\n", __func__,
203 rb->Name, _mesa_get_format_name(rb->Format));
204
205 if (srb->Buffer) {
206 /* this is a malloc'd renderbuffer (accum buffer) */
207 /* nothing to do */
208 return;
209 }
210
211 if (rb->NumSamples > 1) {
212 mt = irb->singlesample_mt;
213 } else {
214 mt = irb->mt;
215 }
216
217 intel_miptree_unmap(brw, mt, irb->mt_level, irb->mt_layer);
218
219 if (irb->need_map_upsample) {
220 intel_renderbuffer_upsample(brw, irb);
221 irb->need_map_upsample = false;
222 }
223
224 if (irb->singlesample_mt_is_tmp)
225 intel_miptree_release(&irb->singlesample_mt);
226 }
227
228
229 /**
230 * Round up the requested multisample count to the next supported sample size.
231 */
232 unsigned
233 intel_quantize_num_samples(struct intel_screen *intel, unsigned num_samples)
234 {
235 const int *msaa_modes = intel_supported_msaa_modes(intel);
236 int quantized_samples = 0;
237
238 for (int i = 0; msaa_modes[i] != -1; ++i) {
239 if (msaa_modes[i] >= num_samples)
240 quantized_samples = msaa_modes[i];
241 else
242 break;
243 }
244
245 return quantized_samples;
246 }
247
248 static mesa_format
249 intel_renderbuffer_format(struct gl_context * ctx, GLenum internalFormat)
250 {
251 struct brw_context *brw = brw_context(ctx);
252
253 switch (internalFormat) {
254 default:
255 /* Use the same format-choice logic as for textures.
256 * Renderbuffers aren't any different from textures for us,
257 * except they're less useful because you can't texture with
258 * them.
259 */
260 return ctx->Driver.ChooseTextureFormat(ctx, GL_TEXTURE_2D,
261 internalFormat,
262 GL_NONE, GL_NONE);
263 break;
264 case GL_STENCIL_INDEX:
265 case GL_STENCIL_INDEX1_EXT:
266 case GL_STENCIL_INDEX4_EXT:
267 case GL_STENCIL_INDEX8_EXT:
268 case GL_STENCIL_INDEX16_EXT:
269 /* These aren't actual texture formats, so force them here. */
270 if (brw->has_separate_stencil) {
271 return MESA_FORMAT_S_UINT8;
272 } else {
273 assert(!brw->must_use_separate_stencil);
274 return MESA_FORMAT_Z24_UNORM_S8_UINT;
275 }
276 }
277 }
278
279 static GLboolean
280 intel_alloc_private_renderbuffer_storage(struct gl_context * ctx, struct gl_renderbuffer *rb,
281 GLenum internalFormat,
282 GLuint width, GLuint height)
283 {
284 struct brw_context *brw = brw_context(ctx);
285 struct intel_screen *screen = brw->screen;
286 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
287
288 assert(rb->Format != MESA_FORMAT_NONE);
289
290 rb->NumSamples = intel_quantize_num_samples(screen, rb->NumSamples);
291 rb->Width = width;
292 rb->Height = height;
293 rb->_BaseFormat = _mesa_get_format_base_format(rb->Format);
294
295 intel_miptree_release(&irb->mt);
296
297 DBG("%s: %s: %s (%dx%d)\n", __func__,
298 _mesa_enum_to_string(internalFormat),
299 _mesa_get_format_name(rb->Format), width, height);
300
301 if (width == 0 || height == 0)
302 return true;
303
304 irb->mt = intel_miptree_create_for_renderbuffer(brw, rb->Format,
305 width, height,
306 rb->NumSamples);
307 if (!irb->mt)
308 return false;
309
310 irb->layer_count = 1;
311
312 return true;
313 }
314
315 /**
316 * Called via glRenderbufferStorageEXT() to set the format and allocate
317 * storage for a user-created renderbuffer.
318 */
319 static GLboolean
320 intel_alloc_renderbuffer_storage(struct gl_context * ctx, struct gl_renderbuffer *rb,
321 GLenum internalFormat,
322 GLuint width, GLuint height)
323 {
324 rb->Format = intel_renderbuffer_format(ctx, internalFormat);
325 return intel_alloc_private_renderbuffer_storage(ctx, rb, internalFormat, width, height);
326 }
327
328 static void
329 intel_image_target_renderbuffer_storage(struct gl_context *ctx,
330 struct gl_renderbuffer *rb,
331 void *image_handle)
332 {
333 struct brw_context *brw = brw_context(ctx);
334 struct intel_renderbuffer *irb;
335 __DRIscreen *dri_screen = brw->screen->driScrnPriv;
336 __DRIimage *image;
337
338 image = dri_screen->dri2.image->lookupEGLImage(dri_screen, image_handle,
339 dri_screen->loaderPrivate);
340 if (image == NULL)
341 return;
342
343 if (image->planar_format && image->planar_format->nplanes > 1) {
344 _mesa_error(ctx, GL_INVALID_OPERATION,
345 "glEGLImageTargetRenderbufferStorage(planar buffers are not "
346 "supported as render targets.)");
347 return;
348 }
349
350 /* __DRIimage is opaque to the core so it has to be checked here */
351 if (!brw->mesa_format_supports_render[image->format]) {
352 _mesa_error(ctx, GL_INVALID_OPERATION,
353 "glEGLImageTargetRenderbufferStorage(unsupported image format)");
354 return;
355 }
356
357 irb = intel_renderbuffer(rb);
358 intel_miptree_release(&irb->mt);
359
360 /* Disable creation of the miptree's aux buffers because the driver exposes
361 * no EGL API to manage them. That is, there is no API for resolving the aux
362 * buffer's content to the main buffer nor for invalidating the aux buffer's
363 * content.
364 */
365 irb->mt = intel_miptree_create_for_bo(brw,
366 image->bo,
367 image->format,
368 image->offset,
369 image->width,
370 image->height,
371 1,
372 image->pitch,
373 MIPTREE_LAYOUT_DISABLE_AUX);
374 if (!irb->mt)
375 return;
376
377 /* Adjust the miptree's upper-left coordinate.
378 *
379 * FIXME: Adjusting the miptree's layout outside of
380 * intel_miptree_create_layout() is fragile. Plumb the adjustment through
381 * intel_miptree_create_layout() and brw_tex_layout().
382 */
383 irb->mt->level[0].level_x = image->tile_x;
384 irb->mt->level[0].level_y = image->tile_y;
385 irb->mt->level[0].slice[0].x_offset = image->tile_x;
386 irb->mt->level[0].slice[0].y_offset = image->tile_y;
387 irb->mt->total_width += image->tile_x;
388 irb->mt->total_height += image->tile_y;
389
390 rb->InternalFormat = image->internal_format;
391 rb->Width = image->width;
392 rb->Height = image->height;
393 rb->Format = image->format;
394 rb->_BaseFormat = _mesa_get_format_base_format(image->format);
395 rb->NeedsFinishRenderTexture = true;
396 irb->layer_count = 1;
397 }
398
399 /**
400 * Called by _mesa_resize_framebuffer() for each hardware renderbuffer when a
401 * window system framebuffer is resized.
402 *
403 * Any actual buffer reallocations for hardware renderbuffers (which would
404 * have triggered _mesa_resize_framebuffer()) were done by
405 * intel_process_dri2_buffer().
406 */
407 static GLboolean
408 intel_alloc_window_storage(struct gl_context * ctx, struct gl_renderbuffer *rb,
409 GLenum internalFormat, GLuint width, GLuint height)
410 {
411 (void) ctx;
412 assert(rb->Name == 0);
413 rb->Width = width;
414 rb->Height = height;
415 rb->InternalFormat = internalFormat;
416
417 return true;
418 }
419
420 /** Dummy function for gl_renderbuffer::AllocStorage() */
421 static GLboolean
422 intel_nop_alloc_storage(struct gl_context * ctx, struct gl_renderbuffer *rb,
423 GLenum internalFormat, GLuint width, GLuint height)
424 {
425 (void) rb;
426 (void) internalFormat;
427 (void) width;
428 (void) height;
429 _mesa_problem(ctx, "intel_nop_alloc_storage should never be called.");
430 return false;
431 }
432
433 /**
434 * Create an intel_renderbuffer for a __DRIdrawable. This function is
435 * unrelated to GL renderbuffers (that is, those created by
436 * glGenRenderbuffers).
437 *
438 * \param num_samples must be quantized.
439 */
440 struct intel_renderbuffer *
441 intel_create_winsys_renderbuffer(struct intel_screen *screen,
442 mesa_format format, unsigned num_samples)
443 {
444 struct intel_renderbuffer *irb = CALLOC_STRUCT(intel_renderbuffer);
445 if (!irb)
446 return NULL;
447
448 struct gl_renderbuffer *rb = &irb->Base.Base;
449 irb->layer_count = 1;
450
451 _mesa_init_renderbuffer(rb, 0);
452 rb->ClassID = INTEL_RB_CLASS;
453 rb->_BaseFormat = _mesa_get_format_base_format(format);
454 rb->Format = format;
455 rb->InternalFormat = rb->_BaseFormat;
456 rb->NumSamples = num_samples;
457
458 /* intel-specific methods */
459 rb->Delete = intel_delete_renderbuffer;
460 rb->AllocStorage = intel_alloc_window_storage;
461
462 return irb;
463 }
464
465 /**
466 * Private window-system buffers (as opposed to ones shared with the display
467 * server created with intel_create_winsys_renderbuffer()) are most similar in their
468 * handling to user-created renderbuffers, but they have a resize handler that
469 * may be called at intel_update_renderbuffers() time.
470 *
471 * \param num_samples must be quantized.
472 */
473 struct intel_renderbuffer *
474 intel_create_private_renderbuffer(struct intel_screen *screen,
475 mesa_format format, unsigned num_samples)
476 {
477 struct intel_renderbuffer *irb;
478
479 irb = intel_create_winsys_renderbuffer(screen, format, num_samples);
480 irb->Base.Base.AllocStorage = intel_alloc_private_renderbuffer_storage;
481
482 return irb;
483 }
484
485 /**
486 * Create a new renderbuffer object.
487 * Typically called via glBindRenderbufferEXT().
488 */
489 static struct gl_renderbuffer *
490 intel_new_renderbuffer(struct gl_context * ctx, GLuint name)
491 {
492 struct intel_renderbuffer *irb;
493 struct gl_renderbuffer *rb;
494
495 irb = CALLOC_STRUCT(intel_renderbuffer);
496 if (!irb) {
497 _mesa_error(ctx, GL_OUT_OF_MEMORY, "creating renderbuffer");
498 return NULL;
499 }
500
501 rb = &irb->Base.Base;
502
503 _mesa_init_renderbuffer(rb, name);
504 rb->ClassID = INTEL_RB_CLASS;
505
506 /* intel-specific methods */
507 rb->Delete = intel_delete_renderbuffer;
508 rb->AllocStorage = intel_alloc_renderbuffer_storage;
509 /* span routines set in alloc_storage function */
510
511 return rb;
512 }
513
514 static bool
515 intel_renderbuffer_update_wrapper(struct brw_context *brw,
516 struct intel_renderbuffer *irb,
517 struct gl_texture_image *image,
518 uint32_t layer,
519 bool layered)
520 {
521 struct gl_renderbuffer *rb = &irb->Base.Base;
522 struct intel_texture_image *intel_image = intel_texture_image(image);
523 struct intel_mipmap_tree *mt = intel_image->mt;
524 int level = image->Level;
525
526 rb->AllocStorage = intel_nop_alloc_storage;
527
528 /* adjust for texture view parameters */
529 layer += image->TexObject->MinLayer;
530 level += image->TexObject->MinLevel;
531
532 intel_miptree_check_level_layer(mt, level, layer);
533 irb->mt_level = level;
534
535 int layer_multiplier;
536 switch (mt->msaa_layout) {
537 case INTEL_MSAA_LAYOUT_UMS:
538 case INTEL_MSAA_LAYOUT_CMS:
539 layer_multiplier = MAX2(mt->num_samples, 1);
540 break;
541
542 default:
543 layer_multiplier = 1;
544 }
545
546 irb->mt_layer = layer_multiplier * layer;
547
548 if (!layered) {
549 irb->layer_count = 1;
550 } else if (mt->target != GL_TEXTURE_3D && image->TexObject->NumLayers > 0) {
551 irb->layer_count = image->TexObject->NumLayers;
552 } else {
553 irb->layer_count = mt->level[level].depth / layer_multiplier;
554 }
555
556 intel_miptree_reference(&irb->mt, mt);
557
558 intel_renderbuffer_set_draw_offset(irb);
559
560 if (intel_miptree_wants_hiz_buffer(brw, mt)) {
561 intel_miptree_alloc_hiz(brw, mt);
562 if (!mt->hiz_buf)
563 return false;
564 }
565
566 return true;
567 }
568
569 void
570 intel_renderbuffer_set_draw_offset(struct intel_renderbuffer *irb)
571 {
572 unsigned int dst_x, dst_y;
573
574 /* compute offset of the particular 2D image within the texture region */
575 intel_miptree_get_image_offset(irb->mt,
576 irb->mt_level,
577 irb->mt_layer,
578 &dst_x, &dst_y);
579
580 irb->draw_x = dst_x;
581 irb->draw_y = dst_y;
582 }
583
584 /**
585 * Called by glFramebufferTexture[123]DEXT() (and other places) to
586 * prepare for rendering into texture memory. This might be called
587 * many times to choose different texture levels, cube faces, etc
588 * before intel_finish_render_texture() is ever called.
589 */
590 static void
591 intel_render_texture(struct gl_context * ctx,
592 struct gl_framebuffer *fb,
593 struct gl_renderbuffer_attachment *att)
594 {
595 struct brw_context *brw = brw_context(ctx);
596 struct gl_renderbuffer *rb = att->Renderbuffer;
597 struct intel_renderbuffer *irb = intel_renderbuffer(rb);
598 struct gl_texture_image *image = rb->TexImage;
599 struct intel_texture_image *intel_image = intel_texture_image(image);
600 struct intel_mipmap_tree *mt = intel_image->mt;
601 int layer;
602
603 (void) fb;
604
605 if (att->CubeMapFace > 0) {
606 assert(att->Zoffset == 0);
607 layer = att->CubeMapFace;
608 } else {
609 layer = att->Zoffset;
610 }
611
612 if (!intel_image->mt) {
613 /* Fallback on drawing to a texture that doesn't have a miptree
614 * (has a border, width/height 0, etc.)
615 */
616 _swrast_render_texture(ctx, fb, att);
617 return;
618 }
619
620 intel_miptree_check_level_layer(mt, att->TextureLevel, layer);
621
622 if (!intel_renderbuffer_update_wrapper(brw, irb, image, layer, att->Layered)) {
623 _swrast_render_texture(ctx, fb, att);
624 return;
625 }
626
627 DBG("Begin render %s texture tex=%u w=%d h=%d d=%d refcount=%d\n",
628 _mesa_get_format_name(image->TexFormat),
629 att->Texture->Name, image->Width, image->Height, image->Depth,
630 rb->RefCount);
631 }
632
633
634 #define fbo_incomplete(fb, ...) do { \
635 static GLuint msg_id = 0; \
636 if (unlikely(ctx->Const.ContextFlags & GL_CONTEXT_FLAG_DEBUG_BIT)) { \
637 _mesa_gl_debug(ctx, &msg_id, \
638 MESA_DEBUG_SOURCE_API, \
639 MESA_DEBUG_TYPE_OTHER, \
640 MESA_DEBUG_SEVERITY_MEDIUM, \
641 __VA_ARGS__); \
642 } \
643 DBG(__VA_ARGS__); \
644 fb->_Status = GL_FRAMEBUFFER_UNSUPPORTED; \
645 } while (0)
646
647 /**
648 * Do additional "completeness" testing of a framebuffer object.
649 */
650 static void
651 intel_validate_framebuffer(struct gl_context *ctx, struct gl_framebuffer *fb)
652 {
653 struct brw_context *brw = brw_context(ctx);
654 struct intel_renderbuffer *depthRb =
655 intel_get_renderbuffer(fb, BUFFER_DEPTH);
656 struct intel_renderbuffer *stencilRb =
657 intel_get_renderbuffer(fb, BUFFER_STENCIL);
658 struct intel_mipmap_tree *depth_mt = NULL, *stencil_mt = NULL;
659 unsigned i;
660
661 DBG("%s() on fb %p (%s)\n", __func__,
662 fb, (fb == ctx->DrawBuffer ? "drawbuffer" :
663 (fb == ctx->ReadBuffer ? "readbuffer" : "other buffer")));
664
665 if (depthRb)
666 depth_mt = depthRb->mt;
667 if (stencilRb) {
668 stencil_mt = stencilRb->mt;
669 if (stencil_mt->stencil_mt)
670 stencil_mt = stencil_mt->stencil_mt;
671 }
672
673 if (depth_mt && stencil_mt) {
674 if (brw->gen >= 6) {
675 unsigned d_width, d_height, d_depth;
676 unsigned s_width, s_height, s_depth;
677
678 if (depth_mt->surf.size > 0) {
679 d_width = depth_mt->surf.phys_level0_sa.width;
680 d_height = depth_mt->surf.phys_level0_sa.height;
681 d_depth = depth_mt->surf.dim == ISL_SURF_DIM_3D ?
682 depth_mt->surf.phys_level0_sa.depth :
683 depth_mt->surf.phys_level0_sa.array_len;
684 } else {
685 d_width = depth_mt->physical_width0;
686 d_height = depth_mt->physical_height0;
687 d_depth = depth_mt->physical_depth0;
688 }
689
690 if (stencil_mt->surf.size > 0) {
691 s_width = stencil_mt->surf.phys_level0_sa.width;
692 s_height = stencil_mt->surf.phys_level0_sa.height;
693 s_depth = stencil_mt->surf.dim == ISL_SURF_DIM_3D ?
694 stencil_mt->surf.phys_level0_sa.depth :
695 stencil_mt->surf.phys_level0_sa.array_len;
696 } else {
697 s_width = stencil_mt->physical_width0;
698 s_height = stencil_mt->physical_height0;
699 s_depth = stencil_mt->physical_depth0;
700 }
701
702 /* For gen >= 6, we are using the lod/minimum-array-element fields
703 * and supporting layered rendering. This means that we must restrict
704 * the depth & stencil attachments to match in various more retrictive
705 * ways. (width, height, depth, LOD and layer)
706 */
707 if (d_width != s_width ||
708 d_height != s_height ||
709 d_depth != s_depth ||
710 depthRb->mt_level != stencilRb->mt_level ||
711 depthRb->mt_layer != stencilRb->mt_layer) {
712 fbo_incomplete(fb,
713 "FBO incomplete: depth and stencil must match in"
714 "width, height, depth, LOD and layer\n");
715 }
716 }
717 if (depth_mt == stencil_mt) {
718 /* For true packed depth/stencil (not faked on prefers-separate-stencil
719 * hardware) we need to be sure they're the same level/layer, since
720 * we'll be emitting a single packet describing the packed setup.
721 */
722 if (depthRb->mt_level != stencilRb->mt_level ||
723 depthRb->mt_layer != stencilRb->mt_layer) {
724 fbo_incomplete(fb,
725 "FBO incomplete: depth image level/layer %d/%d != "
726 "stencil image %d/%d\n",
727 depthRb->mt_level,
728 depthRb->mt_layer,
729 stencilRb->mt_level,
730 stencilRb->mt_layer);
731 }
732 } else {
733 if (!brw->has_separate_stencil) {
734 fbo_incomplete(fb, "FBO incomplete: separate stencil "
735 "unsupported\n");
736 }
737 if (stencil_mt->format != MESA_FORMAT_S_UINT8) {
738 fbo_incomplete(fb, "FBO incomplete: separate stencil is %s "
739 "instead of S8\n",
740 _mesa_get_format_name(stencil_mt->format));
741 }
742 if (brw->gen < 7 && !intel_renderbuffer_has_hiz(depthRb)) {
743 /* Before Gen7, separate depth and stencil buffers can be used
744 * only if HiZ is enabled. From the Sandybridge PRM, Volume 2,
745 * Part 1, Bit 3DSTATE_DEPTH_BUFFER.SeparateStencilBufferEnable:
746 * [DevSNB]: This field must be set to the same value (enabled
747 * or disabled) as Hierarchical Depth Buffer Enable.
748 */
749 fbo_incomplete(fb, "FBO incomplete: separate stencil "
750 "without HiZ\n");
751 }
752 }
753 }
754
755 for (i = 0; i < ARRAY_SIZE(fb->Attachment); i++) {
756 struct gl_renderbuffer *rb;
757 struct intel_renderbuffer *irb;
758
759 if (fb->Attachment[i].Type == GL_NONE)
760 continue;
761
762 /* A supported attachment will have a Renderbuffer set either
763 * from being a Renderbuffer or being a texture that got the
764 * intel_wrap_texture() treatment.
765 */
766 rb = fb->Attachment[i].Renderbuffer;
767 if (rb == NULL) {
768 fbo_incomplete(fb, "FBO incomplete: attachment without "
769 "renderbuffer\n");
770 continue;
771 }
772
773 if (fb->Attachment[i].Type == GL_TEXTURE) {
774 if (rb->TexImage->Border) {
775 fbo_incomplete(fb, "FBO incomplete: texture with border\n");
776 continue;
777 }
778 }
779
780 irb = intel_renderbuffer(rb);
781 if (irb == NULL) {
782 fbo_incomplete(fb, "FBO incomplete: software rendering "
783 "renderbuffer\n");
784 continue;
785 }
786
787 if (!brw_render_target_supported(brw, rb)) {
788 fbo_incomplete(fb, "FBO incomplete: Unsupported HW "
789 "texture/renderbuffer format attached: %s\n",
790 _mesa_get_format_name(intel_rb_format(irb)));
791 }
792 }
793 }
794
795 /**
796 * Try to do a glBlitFramebuffer using glCopyTexSubImage2D
797 * We can do this when the dst renderbuffer is actually a texture and
798 * there is no scaling, mirroring or scissoring.
799 *
800 * \return new buffer mask indicating the buffers left to blit using the
801 * normal path.
802 */
803 static GLbitfield
804 intel_blit_framebuffer_with_blitter(struct gl_context *ctx,
805 const struct gl_framebuffer *readFb,
806 const struct gl_framebuffer *drawFb,
807 GLint srcX0, GLint srcY0,
808 GLint srcX1, GLint srcY1,
809 GLint dstX0, GLint dstY0,
810 GLint dstX1, GLint dstY1,
811 GLbitfield mask)
812 {
813 struct brw_context *brw = brw_context(ctx);
814
815 /* Sync up the state of window system buffers. We need to do this before
816 * we go looking for the buffers.
817 */
818 intel_prepare_render(brw);
819
820 if (mask & GL_COLOR_BUFFER_BIT) {
821 unsigned i;
822 struct gl_renderbuffer *src_rb = readFb->_ColorReadBuffer;
823 struct intel_renderbuffer *src_irb = intel_renderbuffer(src_rb);
824
825 if (!src_irb) {
826 perf_debug("glBlitFramebuffer(): missing src renderbuffer. "
827 "Falling back to software rendering.\n");
828 return mask;
829 }
830
831 /* If the source and destination are the same size with no mirroring,
832 * the rectangles are within the size of the texture and there is no
833 * scissor, then we can probably use the blit engine.
834 */
835 if (!(srcX0 - srcX1 == dstX0 - dstX1 &&
836 srcY0 - srcY1 == dstY0 - dstY1 &&
837 srcX1 >= srcX0 &&
838 srcY1 >= srcY0 &&
839 srcX0 >= 0 && srcX1 <= readFb->Width &&
840 srcY0 >= 0 && srcY1 <= readFb->Height &&
841 dstX0 >= 0 && dstX1 <= drawFb->Width &&
842 dstY0 >= 0 && dstY1 <= drawFb->Height &&
843 !(ctx->Scissor.EnableFlags))) {
844 perf_debug("glBlitFramebuffer(): non-1:1 blit. "
845 "Falling back to software rendering.\n");
846 return mask;
847 }
848
849 /* Blit to all active draw buffers. We don't do any pre-checking,
850 * because we assume that copying to MRTs is rare, and failure midway
851 * through copying is even more rare. Even if it was to occur, it's
852 * safe to let meta start the copy over from scratch, because
853 * glBlitFramebuffer completely overwrites the destination pixels, and
854 * results are undefined if any destination pixels have a dependency on
855 * source pixels.
856 */
857 for (i = 0; i < drawFb->_NumColorDrawBuffers; i++) {
858 struct gl_renderbuffer *dst_rb = drawFb->_ColorDrawBuffers[i];
859 struct intel_renderbuffer *dst_irb = intel_renderbuffer(dst_rb);
860
861 if (!dst_irb) {
862 perf_debug("glBlitFramebuffer(): missing dst renderbuffer. "
863 "Falling back to software rendering.\n");
864 return mask;
865 }
866
867 if (ctx->Color.sRGBEnabled &&
868 _mesa_get_format_color_encoding(src_irb->mt->format) !=
869 _mesa_get_format_color_encoding(dst_irb->mt->format)) {
870 perf_debug("glBlitFramebuffer() with sRGB conversion cannot be "
871 "handled by BLT path.\n");
872 return mask;
873 }
874
875 if (!intel_miptree_blit(brw,
876 src_irb->mt,
877 src_irb->mt_level, src_irb->mt_layer,
878 srcX0, srcY0, src_rb->Name == 0,
879 dst_irb->mt,
880 dst_irb->mt_level, dst_irb->mt_layer,
881 dstX0, dstY0, dst_rb->Name == 0,
882 dstX1 - dstX0, dstY1 - dstY0, GL_COPY)) {
883 perf_debug("glBlitFramebuffer(): unknown blit failure. "
884 "Falling back to software rendering.\n");
885 return mask;
886 }
887 }
888
889 mask &= ~GL_COLOR_BUFFER_BIT;
890 }
891
892 return mask;
893 }
894
895 static void
896 intel_blit_framebuffer(struct gl_context *ctx,
897 struct gl_framebuffer *readFb,
898 struct gl_framebuffer *drawFb,
899 GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1,
900 GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
901 GLbitfield mask, GLenum filter)
902 {
903 struct brw_context *brw = brw_context(ctx);
904
905 /* Page 679 of OpenGL 4.4 spec says:
906 * "Added BlitFramebuffer to commands affected by conditional rendering in
907 * section 10.10 (Bug 9562)."
908 */
909 if (!_mesa_check_conditional_render(ctx))
910 return;
911
912 if (brw->gen < 6) {
913 /* On gen4-5, try BLT first.
914 *
915 * Gen4-5 have a single ring for both 3D and BLT operations, so there's
916 * no inter-ring synchronization issues like on Gen6+. It is apparently
917 * faster than using the 3D pipeline. Original Gen4 also has to rebase
918 * and copy miptree slices in order to render to unaligned locations.
919 */
920 mask = intel_blit_framebuffer_with_blitter(ctx, readFb, drawFb,
921 srcX0, srcY0, srcX1, srcY1,
922 dstX0, dstY0, dstX1, dstY1,
923 mask);
924 if (mask == 0x0)
925 return;
926 }
927
928 mask = brw_blorp_framebuffer(brw, readFb, drawFb,
929 srcX0, srcY0, srcX1, srcY1,
930 dstX0, dstY0, dstX1, dstY1,
931 mask, filter);
932 if (mask == 0x0)
933 return;
934
935 mask = _mesa_meta_BlitFramebuffer(ctx, readFb, drawFb,
936 srcX0, srcY0, srcX1, srcY1,
937 dstX0, dstY0, dstX1, dstY1,
938 mask, filter);
939 if (mask == 0x0)
940 return;
941
942 if (brw->gen >= 8 && (mask & GL_STENCIL_BUFFER_BIT)) {
943 assert(!"Invalid blit");
944 }
945
946 /* Try using the BLT engine. */
947 mask = intel_blit_framebuffer_with_blitter(ctx, readFb, drawFb,
948 srcX0, srcY0, srcX1, srcY1,
949 dstX0, dstY0, dstX1, dstY1,
950 mask);
951 if (mask == 0x0)
952 return;
953
954 _swrast_BlitFramebuffer(ctx, readFb, drawFb,
955 srcX0, srcY0, srcX1, srcY1,
956 dstX0, dstY0, dstX1, dstY1,
957 mask, filter);
958 }
959
960 /**
961 * Does the renderbuffer have hiz enabled?
962 */
963 bool
964 intel_renderbuffer_has_hiz(struct intel_renderbuffer *irb)
965 {
966 return intel_miptree_level_has_hiz(irb->mt, irb->mt_level);
967 }
968
969 void
970 intel_renderbuffer_move_to_temp(struct brw_context *brw,
971 struct intel_renderbuffer *irb,
972 bool invalidate)
973 {
974 struct gl_renderbuffer *rb =&irb->Base.Base;
975 struct intel_texture_image *intel_image = intel_texture_image(rb->TexImage);
976 struct intel_mipmap_tree *new_mt;
977 int width, height, depth;
978
979 uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD |
980 MIPTREE_LAYOUT_TILING_ANY;
981
982 intel_get_image_dims(rb->TexImage, &width, &height, &depth);
983
984 assert(irb->align_wa_mt == NULL);
985 new_mt = intel_miptree_create(brw, GL_TEXTURE_2D,
986 intel_image->base.Base.TexFormat,
987 0, 0,
988 width, height, 1,
989 irb->mt->num_samples,
990 layout_flags);
991
992 if (!invalidate)
993 intel_miptree_copy_slice(brw, intel_image->mt,
994 intel_image->base.Base.Level, irb->mt_layer,
995 new_mt, 0, 0);
996
997 intel_miptree_reference(&irb->align_wa_mt, new_mt);
998 intel_miptree_release(&new_mt);
999
1000 irb->draw_x = 0;
1001 irb->draw_y = 0;
1002 }
1003
1004 void
1005 brw_render_cache_set_clear(struct brw_context *brw)
1006 {
1007 struct set_entry *entry;
1008
1009 set_foreach(brw->render_cache, entry) {
1010 _mesa_set_remove(brw->render_cache, entry);
1011 }
1012 }
1013
1014 void
1015 brw_render_cache_set_add_bo(struct brw_context *brw, struct brw_bo *bo)
1016 {
1017 _mesa_set_add(brw->render_cache, bo);
1018 }
1019
1020 /**
1021 * Emits an appropriate flush for a BO if it has been rendered to within the
1022 * same batchbuffer as a read that's about to be emitted.
1023 *
1024 * The GPU has separate, incoherent caches for the render cache and the
1025 * sampler cache, along with other caches. Usually data in the different
1026 * caches don't interact (e.g. we don't render to our driver-generated
1027 * immediate constant data), but for render-to-texture in FBOs we definitely
1028 * do. When a batchbuffer is flushed, the kernel will ensure that everything
1029 * necessary is flushed before another use of that BO, but for reuse from
1030 * different caches within a batchbuffer, it's all our responsibility.
1031 */
1032 void
1033 brw_render_cache_set_check_flush(struct brw_context *brw, struct brw_bo *bo)
1034 {
1035 if (!_mesa_set_search(brw->render_cache, bo))
1036 return;
1037
1038 if (brw->gen >= 6) {
1039 brw_emit_pipe_control_flush(brw,
1040 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
1041 PIPE_CONTROL_RENDER_TARGET_FLUSH |
1042 PIPE_CONTROL_CS_STALL);
1043
1044 brw_emit_pipe_control_flush(brw,
1045 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1046 PIPE_CONTROL_CONST_CACHE_INVALIDATE);
1047 } else {
1048 brw_emit_mi_flush(brw);
1049 }
1050
1051 brw_render_cache_set_clear(brw);
1052 }
1053
1054 /**
1055 * Do one-time context initializations related to GL_EXT_framebuffer_object.
1056 * Hook in device driver functions.
1057 */
1058 void
1059 intel_fbo_init(struct brw_context *brw)
1060 {
1061 struct dd_function_table *dd = &brw->ctx.Driver;
1062 dd->NewRenderbuffer = intel_new_renderbuffer;
1063 dd->MapRenderbuffer = intel_map_renderbuffer;
1064 dd->UnmapRenderbuffer = intel_unmap_renderbuffer;
1065 dd->RenderTexture = intel_render_texture;
1066 dd->ValidateFramebuffer = intel_validate_framebuffer;
1067 dd->BlitFramebuffer = intel_blit_framebuffer;
1068 dd->EGLImageTargetRenderbufferStorage =
1069 intel_image_target_renderbuffer_storage;
1070
1071 brw->render_cache = _mesa_set_create(brw, _mesa_hash_pointer,
1072 _mesa_key_pointer_equal);
1073 }