2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_mipmap_tree.h"
31 #include "intel_tex.h"
32 #include "intel_blit.h"
33 #include "intel_fbo.h"
35 #include "brw_blorp.h"
36 #include "brw_context.h"
37 #include "brw_state.h"
39 #include "main/enums.h"
40 #include "main/fbobject.h"
41 #include "main/formats.h"
42 #include "main/glformats.h"
43 #include "main/texcompress_etc.h"
44 #include "main/teximage.h"
45 #include "main/streaming-load-memcpy.h"
46 #include "x86/common_x86_asm.h"
48 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
50 static void *intel_miptree_map_raw(struct brw_context
*brw
,
51 struct intel_mipmap_tree
*mt
,
54 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
57 intel_miptree_alloc_mcs(struct brw_context
*brw
,
58 struct intel_mipmap_tree
*mt
,
62 * Determine which MSAA layout should be used by the MSAA surface being
63 * created, based on the chip generation and the surface type.
65 static enum intel_msaa_layout
66 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
67 enum intel_aux_disable aux_disable
)
69 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
71 return INTEL_MSAA_LAYOUT_IMS
;
73 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
74 switch (_mesa_get_format_base_format(format
)) {
75 case GL_DEPTH_COMPONENT
:
76 case GL_STENCIL_INDEX
:
77 case GL_DEPTH_STENCIL
:
78 return INTEL_MSAA_LAYOUT_IMS
;
80 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
82 * This field must be set to 0 for all SINT MSRTs when all RT channels
85 * In practice this means that we have to disable MCS for all signed
86 * integer MSAA buffers. The alternative, to disable MCS only when one
87 * of the render target channels is disabled, is impractical because it
88 * would require converting between CMS and UMS MSAA layouts on the fly,
91 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
92 return INTEL_MSAA_LAYOUT_UMS
;
93 } else if (aux_disable
& INTEL_AUX_DISABLE_MCS
) {
94 /* We can't use the CMS layout because it uses an aux buffer, the MCS
95 * buffer. So fallback to UMS, which is identical to CMS without the
97 return INTEL_MSAA_LAYOUT_UMS
;
99 return INTEL_MSAA_LAYOUT_CMS
;
105 intel_tiling_supports_non_msrt_mcs(const struct brw_context
*brw
,
108 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
109 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
111 * - Support is limited to tiled render targets.
113 * Gen9 changes the restriction to Y-tile only.
116 return tiling
== I915_TILING_Y
;
117 else if (brw
->gen
>= 7)
118 return tiling
!= I915_TILING_NONE
;
124 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
125 * can be used. This doesn't (and should not) inspect any of the properties of
128 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
129 * beneath the "Fast Color Clear" bullet (p326):
131 * - Support is for non-mip-mapped and non-array surface types only.
133 * And then later, on p327:
135 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
138 * From the Skylake documentation, it is made clear that X-tiling is no longer
141 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
145 intel_miptree_supports_non_msrt_fast_clear(struct brw_context
*brw
,
146 const struct intel_mipmap_tree
*mt
)
148 /* MCS support does not exist prior to Gen7 */
152 if (mt
->aux_disable
& INTEL_AUX_DISABLE_MCS
)
155 /* This function applies only to non-multisampled render targets. */
156 if (mt
->num_samples
> 1)
159 /* MCS is only supported for color buffers */
160 switch (_mesa_get_format_base_format(mt
->format
)) {
161 case GL_DEPTH_COMPONENT
:
162 case GL_DEPTH_STENCIL
:
163 case GL_STENCIL_INDEX
:
167 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
170 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
171 const bool arrayed
= mt
->physical_depth0
!= 1;
174 /* Multisample surfaces with the CMS layout are not layered surfaces,
175 * yet still have physical_depth0 > 1. Assert that we don't
176 * accidentally reject a multisampled surface here. We should have
177 * rejected it earlier by explicitly checking the sample count.
179 assert(mt
->num_samples
<= 1);
182 /* Handle the hardware restrictions...
184 * All GENs have the following restriction: "MCS buffer for non-MSRT is
185 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
187 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
188 * Non-MultiSampler Render Target Restrictions) Support is for
189 * non-mip-mapped and non-array surface types only.
191 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
192 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
193 * surfaces are supported with MCS buffer layout with these alignments in
194 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
196 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
197 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
198 * surfaces are supported with MCS buffer layout with these alignments in
199 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
201 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
204 /* There's no point in using an MCS buffer if the surface isn't in a
207 if (!brw
->format_supported_as_render_target
[mt
->format
])
211 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
212 const enum isl_format isl_format
=
213 brw_isl_format_for_mesa_format(linear_format
);
214 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
219 /* On Gen9 support for color buffer compression was extended to single
220 * sampled surfaces. This is a helper considering both auxiliary buffer
221 * type and number of samples telling if the given miptree represents
222 * the new single sampled case - also called lossless compression.
225 intel_miptree_is_lossless_compressed(const struct brw_context
*brw
,
226 const struct intel_mipmap_tree
*mt
)
228 /* Only available from Gen9 onwards. */
232 /* Compression always requires auxiliary buffer. */
236 /* Single sample compression is represented re-using msaa compression
237 * layout type: "Compressed Multisampled Surfaces".
239 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
)
242 /* And finally distinguish between msaa and single sample case. */
243 return mt
->num_samples
<= 1;
247 intel_miptree_supports_lossless_compressed(struct brw_context
*brw
,
248 const struct intel_mipmap_tree
*mt
)
250 /* For now compression is only enabled for integer formats even though
251 * there exist supported floating point formats also. This is a heuristic
252 * decision based on current public benchmarks. In none of the cases these
253 * formats provided any improvement but a few cases were seen to regress.
254 * Hence these are left to to be enabled in the future when they are known
257 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
260 /* Fast clear mechanism and lossless compression go hand in hand. */
261 if (!intel_miptree_supports_non_msrt_fast_clear(brw
, mt
))
264 /* Fast clear can be also used to clear srgb surfaces by using equivalent
265 * linear format. This trick, however, can't be extended to be used with
266 * lossless compression and therefore a check is needed to see if the format
269 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
273 * Determine depth format corresponding to a depth+stencil format,
274 * for separate stencil.
277 intel_depth_format_for_depthstencil_format(mesa_format format
) {
279 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
280 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
281 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
282 return MESA_FORMAT_Z_FLOAT32
;
290 * @param for_bo Indicates that the caller is
291 * intel_miptree_create_for_bo(). If true, then do not create
294 static struct intel_mipmap_tree
*
295 intel_miptree_create_layout(struct brw_context
*brw
,
304 uint32_t layout_flags
)
306 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
310 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
311 _mesa_enum_to_string(target
),
312 _mesa_get_format_name(format
),
313 first_level
, last_level
, depth0
, mt
);
315 if (target
== GL_TEXTURE_1D_ARRAY
)
316 assert(height0
== 1);
320 mt
->first_level
= first_level
;
321 mt
->last_level
= last_level
;
322 mt
->logical_width0
= width0
;
323 mt
->logical_height0
= height0
;
324 mt
->logical_depth0
= depth0
;
325 mt
->aux_disable
= (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) != 0 ?
326 INTEL_AUX_DISABLE_ALL
: INTEL_AUX_DISABLE_NONE
;
327 mt
->aux_disable
|= INTEL_AUX_DISABLE_CCS
;
328 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
329 mt
->aux_state
= NULL
;
330 mt
->cpp
= _mesa_get_format_bytes(format
);
331 mt
->num_samples
= num_samples
;
332 mt
->compressed
= _mesa_is_format_compressed(format
);
333 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
336 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
337 layout_flags
|= MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
;
339 int depth_multiply
= 1;
340 if (num_samples
> 1) {
341 /* Adjust width/height/depth for MSAA */
342 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, mt
->aux_disable
);
343 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
344 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
345 * "If the surface is multisampled and it is a depth or stencil
346 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
347 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
350 * +----------------------------------------------------------------+
351 * | Num Multisamples | W_l = | H_l = |
352 * +----------------------------------------------------------------+
353 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
354 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
355 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
356 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
357 * +----------------------------------------------------------------+
360 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
361 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
362 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
364 * Another more complicated explanation for these adjustments comes
365 * from the Sandybridge PRM, volume 4, part 1, page 31:
367 * "Any of the other messages (sample*, LOD, load4) used with a
368 * (4x) multisampled surface will in-effect sample a surface with
369 * double the height and width as that indicated in the surface
370 * state. Each pixel position on the original-sized surface is
371 * replaced with a 2x2 of samples with the following arrangement:
376 * Thus, when sampling from a multisampled texture, it behaves as
377 * though the layout in memory for (x,y,sample) is:
379 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
380 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
382 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
383 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
385 * However, the actual layout of multisampled data in memory is:
387 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
388 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
390 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
391 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
393 * This pattern repeats for each 2x2 pixel block.
395 * As a result, when calculating the size of our 4-sample buffer for
396 * an odd width or height, we have to align before scaling up because
397 * sample 3 is in that bottom right 2x2 block.
399 switch (num_samples
) {
401 assert(brw
->gen
>= 8);
402 width0
= ALIGN(width0
, 2) * 2;
403 height0
= ALIGN(height0
, 2);
406 width0
= ALIGN(width0
, 2) * 2;
407 height0
= ALIGN(height0
, 2) * 2;
410 width0
= ALIGN(width0
, 2) * 4;
411 height0
= ALIGN(height0
, 2) * 2;
414 width0
= ALIGN(width0
, 2) * 4;
415 height0
= ALIGN(height0
, 2) * 4;
418 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
421 unreachable("not reached");
424 /* Non-interleaved */
425 depth_multiply
= num_samples
;
426 depth0
*= depth_multiply
;
430 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
431 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
432 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
433 * used on Gen8 to make it pick a qpitch value which doesn't include space
434 * for the mipmaps. On Gen9 this is not necessary because it will
435 * automatically pick a packed qpitch value whenever mt->first_level ==
437 * TODO: can we use it elsewhere?
438 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
441 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
443 switch (mt
->msaa_layout
) {
444 case INTEL_MSAA_LAYOUT_NONE
:
445 case INTEL_MSAA_LAYOUT_IMS
:
446 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
448 case INTEL_MSAA_LAYOUT_UMS
:
449 case INTEL_MSAA_LAYOUT_CMS
:
450 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
455 if (target
== GL_TEXTURE_CUBE_MAP
)
456 assert(depth0
== 6 * depth_multiply
);
458 mt
->physical_width0
= width0
;
459 mt
->physical_height0
= height0
;
460 mt
->physical_depth0
= depth0
;
462 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
463 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
464 (brw
->must_use_separate_stencil
||
465 (brw
->has_separate_stencil
&&
466 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
467 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
469 stencil_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
472 mt
->stencil_mt
= intel_miptree_create(brw
,
483 if (!mt
->stencil_mt
) {
484 intel_miptree_release(&mt
);
487 mt
->stencil_mt
->r8stencil_needs_update
= true;
489 /* Fix up the Z miptree format for how we're splitting out separate
490 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
492 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
495 if (format
== mt
->format
) {
496 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
497 _mesa_get_format_name(mt
->format
));
501 if (layout_flags
& MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
)
502 mt
->array_layout
= GEN6_HIZ_STENCIL
;
505 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
506 * multisampled or have an AUX buffer attached to it.
508 * GEN | MSRT | AUX_CCS_* or AUX_MCS
509 * -------------------------------------------
510 * 9 | HALIGN_16 | HALIGN_16
511 * 8 | HALIGN_ANY | HALIGN_16
515 if (intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
516 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
517 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
518 } else if (brw
->gen
>= 9 && num_samples
> 1) {
519 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
521 const UNUSED
bool is_lossless_compressed_aux
=
522 brw
->gen
>= 9 && num_samples
== 1 &&
523 mt
->format
== MESA_FORMAT_R_UINT32
;
525 /* For now, nothing else has this requirement */
526 assert(is_lossless_compressed_aux
||
527 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
530 if (!brw_miptree_layout(brw
, mt
, layout_flags
)) {
531 intel_miptree_release(&mt
);
535 if (mt
->aux_disable
& INTEL_AUX_DISABLE_MCS
)
536 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
543 * Choose an appropriate uncompressed format for a requested
544 * compressed format, if unsupported.
547 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
549 /* No need to lower ETC formats on these platforms,
550 * they are supported natively.
552 if (brw
->gen
>= 8 || brw
->is_baytrail
)
556 case MESA_FORMAT_ETC1_RGB8
:
557 return MESA_FORMAT_R8G8B8X8_UNORM
;
558 case MESA_FORMAT_ETC2_RGB8
:
559 return MESA_FORMAT_R8G8B8X8_UNORM
;
560 case MESA_FORMAT_ETC2_SRGB8
:
561 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
562 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
563 return MESA_FORMAT_B8G8R8A8_SRGB
;
564 case MESA_FORMAT_ETC2_RGBA8_EAC
:
565 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
566 return MESA_FORMAT_R8G8B8A8_UNORM
;
567 case MESA_FORMAT_ETC2_R11_EAC
:
568 return MESA_FORMAT_R_UNORM16
;
569 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
570 return MESA_FORMAT_R_SNORM16
;
571 case MESA_FORMAT_ETC2_RG11_EAC
:
572 return MESA_FORMAT_R16G16_UNORM
;
573 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
574 return MESA_FORMAT_R16G16_SNORM
;
576 /* Non ETC1 / ETC2 format */
581 static enum isl_aux_state
**
582 create_aux_state_map(struct intel_mipmap_tree
*mt
,
583 enum isl_aux_state initial
)
585 const uint32_t levels
= mt
->last_level
+ 1;
587 uint32_t total_slices
= 0;
588 for (uint32_t level
= 0; level
< levels
; level
++)
589 total_slices
+= mt
->level
[level
].depth
;
591 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
593 /* We're going to allocate a single chunk of data for both the per-level
594 * reference array and the arrays of aux_state. This makes cleanup
595 * significantly easier.
597 const size_t total_size
= per_level_array_size
+
598 total_slices
* sizeof(enum isl_aux_state
);
599 void *data
= malloc(total_size
);
603 enum isl_aux_state
**per_level_arr
= data
;
604 enum isl_aux_state
*s
= data
+ per_level_array_size
;
605 for (uint32_t level
= 0; level
< levels
; level
++) {
606 per_level_arr
[level
] = s
;
607 for (uint32_t a
= 0; a
< mt
->level
[level
].depth
; a
++)
610 assert((void *)s
== data
+ total_size
);
612 return per_level_arr
;
616 free_aux_state_map(enum isl_aux_state
**state
)
621 static struct intel_mipmap_tree
*
622 miptree_create(struct brw_context
*brw
,
631 uint32_t layout_flags
)
633 struct intel_mipmap_tree
*mt
;
634 mesa_format tex_format
= format
;
635 mesa_format etc_format
= MESA_FORMAT_NONE
;
636 uint32_t alloc_flags
= 0;
638 format
= intel_lower_compressed_format(brw
, format
);
640 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
642 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
643 mt
= intel_miptree_create_layout(brw
, target
, format
,
644 first_level
, last_level
, width0
,
645 height0
, depth0
, num_samples
,
650 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
))
651 mt
->tiling
= I915_TILING_Y
;
653 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
654 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
656 mt
->etc_format
= etc_format
;
658 if (format
== MESA_FORMAT_S_UINT8
) {
659 /* Align to size of W tile, 64x64. */
660 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
661 ALIGN(mt
->total_width
, 64),
662 ALIGN(mt
->total_height
, 64),
663 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
666 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
667 mt
->total_width
, mt
->total_height
,
668 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
672 if (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
)
673 mt
->bo
->cache_coherent
= false;
678 struct intel_mipmap_tree
*
679 intel_miptree_create(struct brw_context
*brw
,
688 uint32_t layout_flags
)
690 struct intel_mipmap_tree
*mt
= miptree_create(
692 first_level
, last_level
,
693 width0
, height0
, depth0
, num_samples
,
696 /* If the BO is too large to fit in the aperture, we need to use the
697 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
698 * handle Y-tiling, so we need to fall back to X.
700 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
701 mt
->tiling
== I915_TILING_Y
) {
702 const uint32_t alloc_flags
=
703 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
704 BO_ALLOC_FOR_RENDER
: 0;
705 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
706 mt
->total_width
, mt
->total_height
);
708 mt
->tiling
= I915_TILING_X
;
709 brw_bo_unreference(mt
->bo
);
710 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
711 mt
->total_width
, mt
->total_height
, mt
->cpp
,
712 mt
->tiling
, &mt
->pitch
, alloc_flags
);
718 intel_miptree_release(&mt
);
723 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
724 assert(mt
->num_samples
> 1);
725 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
726 intel_miptree_release(&mt
);
731 /* If this miptree is capable of supporting fast color clears, set
732 * fast_clear_state appropriately to ensure that fast clears will occur.
733 * Allocation of the MCS miptree will be deferred until the first fast
734 * clear actually occurs or when compressed single sampled buffer is
735 * written by the GPU for the first time.
737 if (intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) &&
738 intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
739 mt
->aux_disable
&= ~INTEL_AUX_DISABLE_CCS
;
740 assert(brw
->gen
< 8 || mt
->halign
== 16 || num_samples
<= 1);
742 /* On Gen9+ clients are not currently capable of consuming compressed
743 * single-sampled buffers. Disabling compression allows us to skip
746 const bool lossless_compression_disabled
= INTEL_DEBUG
& DEBUG_NO_RBC
;
747 const bool is_lossless_compressed
=
748 unlikely(!lossless_compression_disabled
) &&
749 brw
->gen
>= 9 && !mt
->is_scanout
&&
750 intel_miptree_supports_lossless_compressed(brw
, mt
);
752 if (is_lossless_compressed
) {
753 intel_miptree_alloc_non_msrt_mcs(brw
, mt
, is_lossless_compressed
);
760 struct intel_mipmap_tree
*
761 intel_miptree_create_for_bo(struct brw_context
*brw
,
769 uint32_t layout_flags
)
771 struct intel_mipmap_tree
*mt
;
772 uint32_t tiling
, swizzle
;
775 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
777 /* Nothing will be able to use this miptree with the BO if the offset isn't
780 if (tiling
!= I915_TILING_NONE
)
781 assert(offset
% 4096 == 0);
783 /* miptrees can't handle negative pitch. If you need flipping of images,
784 * that's outside of the scope of the mt.
788 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
790 /* The BO already has a tiling format and we shouldn't confuse the lower
791 * layers by making it try to find a tiling format again.
793 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
794 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
796 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
797 mt
= intel_miptree_create_layout(brw
, target
, format
,
799 width
, height
, depth
, 0,
804 brw_bo_reference(bo
);
814 * For a singlesample renderbuffer, this simply wraps the given BO with a
817 * For a multisample renderbuffer, this wraps the window system's
818 * (singlesample) BO with a singlesample miptree attached to the
819 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
820 * that will contain the actual rendering (which is lazily resolved to
821 * irb->singlesample_mt).
824 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
825 struct intel_renderbuffer
*irb
,
827 uint32_t width
, uint32_t height
,
830 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
831 struct intel_mipmap_tree
*multisample_mt
= NULL
;
832 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
833 mesa_format format
= rb
->Format
;
834 int num_samples
= rb
->NumSamples
;
836 /* Only the front and back buffers, which are color buffers, are allocated
837 * through the image loader.
839 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
840 _mesa_get_format_base_format(format
) == GL_RGBA
);
842 singlesample_mt
= intel_miptree_create_for_bo(intel
,
850 MIPTREE_LAYOUT_FOR_SCANOUT
);
851 if (!singlesample_mt
)
854 /* If this miptree is capable of supporting fast color clears, set
855 * mcs_state appropriately to ensure that fast clears will occur.
856 * Allocation of the MCS miptree will be deferred until the first fast
857 * clear actually occurs.
859 if (intel_tiling_supports_non_msrt_mcs(intel
, singlesample_mt
->tiling
) &&
860 intel_miptree_supports_non_msrt_fast_clear(intel
, singlesample_mt
)) {
861 singlesample_mt
->aux_disable
&= ~INTEL_AUX_DISABLE_CCS
;
864 if (num_samples
== 0) {
865 intel_miptree_release(&irb
->mt
);
866 irb
->mt
= singlesample_mt
;
868 assert(!irb
->singlesample_mt
);
870 intel_miptree_release(&irb
->singlesample_mt
);
871 irb
->singlesample_mt
= singlesample_mt
;
874 irb
->mt
->logical_width0
!= width
||
875 irb
->mt
->logical_height0
!= height
) {
876 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
884 irb
->need_downsample
= false;
885 intel_miptree_release(&irb
->mt
);
886 irb
->mt
= multisample_mt
;
892 intel_miptree_release(&irb
->singlesample_mt
);
893 intel_miptree_release(&irb
->mt
);
897 struct intel_mipmap_tree
*
898 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
902 uint32_t num_samples
)
904 struct intel_mipmap_tree
*mt
;
907 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
908 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
909 MIPTREE_LAYOUT_TILING_ANY
|
910 MIPTREE_LAYOUT_FOR_SCANOUT
;
912 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
913 width
, height
, depth
, num_samples
,
918 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
919 ok
= intel_miptree_alloc_hiz(brw
, mt
);
927 intel_miptree_release(&mt
);
932 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
933 struct intel_mipmap_tree
*src
)
938 intel_miptree_release(dst
);
942 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
949 intel_miptree_hiz_buffer_free(struct intel_miptree_hiz_buffer
*hiz_buf
)
955 intel_miptree_release(&hiz_buf
->mt
);
957 brw_bo_unreference(hiz_buf
->aux_base
.bo
);
963 intel_miptree_release(struct intel_mipmap_tree
**mt
)
968 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
969 if (--(*mt
)->refcount
<= 0) {
972 DBG("%s deleting %p\n", __func__
, *mt
);
974 brw_bo_unreference((*mt
)->bo
);
975 intel_miptree_release(&(*mt
)->stencil_mt
);
976 intel_miptree_release(&(*mt
)->r8stencil_mt
);
977 intel_miptree_hiz_buffer_free((*mt
)->hiz_buf
);
978 if ((*mt
)->mcs_buf
) {
979 brw_bo_unreference((*mt
)->mcs_buf
->bo
);
980 free((*mt
)->mcs_buf
);
982 free_aux_state_map((*mt
)->aux_state
);
984 intel_miptree_release(&(*mt
)->plane
[0]);
985 intel_miptree_release(&(*mt
)->plane
[1]);
987 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
988 free((*mt
)->level
[i
].slice
);
998 intel_get_image_dims(struct gl_texture_image
*image
,
999 int *width
, int *height
, int *depth
)
1001 switch (image
->TexObject
->Target
) {
1002 case GL_TEXTURE_1D_ARRAY
:
1003 /* For a 1D Array texture the OpenGL API will treat the image height as
1004 * the number of array slices. For Intel hardware, we treat the 1D array
1005 * as a 2D Array with a height of 1. So, here we want to swap image
1008 assert(image
->Depth
== 1);
1009 *width
= image
->Width
;
1011 *depth
= image
->Height
;
1013 case GL_TEXTURE_CUBE_MAP
:
1014 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1015 * though we really have 6 slices.
1017 assert(image
->Depth
== 1);
1018 *width
= image
->Width
;
1019 *height
= image
->Height
;
1023 *width
= image
->Width
;
1024 *height
= image
->Height
;
1025 *depth
= image
->Depth
;
1031 * Can the image be pulled into a unified mipmap tree? This mirrors
1032 * the completeness test in a lot of ways.
1034 * Not sure whether I want to pass gl_texture_image here.
1037 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1038 struct gl_texture_image
*image
)
1040 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1041 GLuint level
= intelImage
->base
.Base
.Level
;
1042 int width
, height
, depth
;
1044 /* glTexImage* choose the texture object based on the target passed in, and
1045 * objects can't change targets over their lifetimes, so this should be
1048 assert(image
->TexObject
->Target
== mt
->target
);
1050 mesa_format mt_format
= mt
->format
;
1051 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1052 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1053 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1054 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1055 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1056 mt_format
= mt
->etc_format
;
1058 if (image
->TexFormat
!= mt_format
)
1061 intel_get_image_dims(image
, &width
, &height
, &depth
);
1063 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1066 int level_depth
= mt
->level
[level
].depth
;
1067 if (mt
->num_samples
> 1) {
1068 switch (mt
->msaa_layout
) {
1069 case INTEL_MSAA_LAYOUT_NONE
:
1070 case INTEL_MSAA_LAYOUT_IMS
:
1072 case INTEL_MSAA_LAYOUT_UMS
:
1073 case INTEL_MSAA_LAYOUT_CMS
:
1074 level_depth
/= mt
->num_samples
;
1079 /* Test image dimensions against the base level image adjusted for
1080 * minification. This will also catch images not present in the
1081 * tree, changed targets, etc.
1083 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1084 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1085 depth
!= level_depth
) {
1089 if (image
->NumSamples
!= mt
->num_samples
)
1097 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1099 GLuint x
, GLuint y
, GLuint d
)
1101 mt
->level
[level
].depth
= d
;
1102 mt
->level
[level
].level_x
= x
;
1103 mt
->level
[level
].level_y
= y
;
1105 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1108 assert(mt
->level
[level
].slice
== NULL
);
1110 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
1111 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1112 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1117 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1118 GLuint level
, GLuint img
,
1121 if (img
== 0 && level
== 0)
1122 assert(x
== 0 && y
== 0);
1124 assert(img
< mt
->level
[level
].depth
);
1126 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1127 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1129 DBG("%s level %d img %d pos %d,%d\n",
1130 __func__
, level
, img
,
1131 mt
->level
[level
].slice
[img
].x_offset
,
1132 mt
->level
[level
].slice
[img
].y_offset
);
1136 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1137 GLuint level
, GLuint slice
,
1138 GLuint
*x
, GLuint
*y
)
1140 assert(slice
< mt
->level
[level
].depth
);
1142 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1143 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1148 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1149 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1150 * and tile_h is set to 1.
1153 intel_get_tile_dims(uint32_t tiling
, uint32_t cpp
,
1154 uint32_t *tile_w
, uint32_t *tile_h
)
1165 case I915_TILING_NONE
:
1170 unreachable("not reached");
1176 * This function computes masks that may be used to select the bits of the X
1177 * and Y coordinates that indicate the offset within a tile. If the BO is
1178 * untiled, the masks are set to 0.
1181 intel_get_tile_masks(uint32_t tiling
, uint32_t cpp
,
1182 uint32_t *mask_x
, uint32_t *mask_y
)
1184 uint32_t tile_w_bytes
, tile_h
;
1186 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1188 *mask_x
= tile_w_bytes
/ cpp
- 1;
1189 *mask_y
= tile_h
- 1;
1193 * Compute the offset (in bytes) from the start of the BO to the given x
1194 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1195 * multiples of the tile size.
1198 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1199 uint32_t x
, uint32_t y
)
1202 uint32_t pitch
= mt
->pitch
;
1203 uint32_t tiling
= mt
->tiling
;
1207 unreachable("not reached");
1208 case I915_TILING_NONE
:
1209 return y
* pitch
+ x
* cpp
;
1211 assert((x
% (512 / cpp
)) == 0);
1212 assert((y
% 8) == 0);
1213 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1215 assert((x
% (128 / cpp
)) == 0);
1216 assert((y
% 32) == 0);
1217 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1222 * Rendering with tiled buffers requires that the base address of the buffer
1223 * be aligned to a page boundary. For renderbuffers, and sometimes with
1224 * textures, we may want the surface to point at a texture image level that
1225 * isn't at a page boundary.
1227 * This function returns an appropriately-aligned base offset
1228 * according to the tiling restrictions, plus any required x/y offset
1232 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1233 GLuint level
, GLuint slice
,
1238 uint32_t mask_x
, mask_y
;
1240 intel_get_tile_masks(mt
->tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1241 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1243 *tile_x
= x
& mask_x
;
1244 *tile_y
= y
& mask_y
;
1246 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1250 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1251 struct intel_mipmap_tree
*src_mt
,
1252 unsigned src_level
, unsigned src_layer
,
1253 struct intel_mipmap_tree
*dst_mt
,
1254 unsigned dst_level
, unsigned dst_layer
,
1255 unsigned width
, unsigned height
)
1258 ptrdiff_t src_stride
, dst_stride
;
1259 int cpp
= dst_mt
->cpp
;
1261 intel_miptree_map(brw
, src_mt
,
1262 src_level
, src_layer
,
1265 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1268 intel_miptree_map(brw
, dst_mt
,
1269 dst_level
, dst_layer
,
1272 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1276 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1277 _mesa_get_format_name(src_mt
->format
),
1278 src_mt
, src
, src_stride
,
1279 _mesa_get_format_name(dst_mt
->format
),
1280 dst_mt
, dst
, dst_stride
,
1283 int row_size
= cpp
* width
;
1284 if (src_stride
== row_size
&&
1285 dst_stride
== row_size
) {
1286 memcpy(dst
, src
, row_size
* height
);
1288 for (int i
= 0; i
< height
; i
++) {
1289 memcpy(dst
, src
, row_size
);
1295 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1296 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1298 /* Don't forget to copy the stencil data over, too. We could have skipped
1299 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1300 * shuffling the two data sources in/out of temporary storage instead of
1301 * the direct mapping we get this way.
1303 if (dst_mt
->stencil_mt
) {
1304 assert(src_mt
->stencil_mt
);
1305 intel_miptree_copy_slice_sw(brw
,
1306 src_mt
->stencil_mt
, src_level
, src_layer
,
1307 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1313 intel_miptree_copy_slice(struct brw_context
*brw
,
1314 struct intel_mipmap_tree
*src_mt
,
1315 unsigned src_level
, unsigned src_layer
,
1316 struct intel_mipmap_tree
*dst_mt
,
1317 unsigned dst_level
, unsigned dst_layer
)
1320 uint32_t width
= minify(src_mt
->physical_width0
,
1321 src_level
- src_mt
->first_level
);
1322 uint32_t height
= minify(src_mt
->physical_height0
,
1323 src_level
- src_mt
->first_level
);
1324 mesa_format format
= src_mt
->format
;
1326 assert(src_layer
< src_mt
->level
[src_level
].depth
);
1327 assert(src_mt
->format
== dst_mt
->format
);
1329 if (dst_mt
->compressed
) {
1331 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1332 height
= ALIGN_NPOT(height
, j
) / j
;
1333 width
= ALIGN_NPOT(width
, i
) / i
;
1336 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1337 * below won't apply since we can't do the depth's Y tiling or the
1338 * stencil's W tiling in the blitter.
1340 if (src_mt
->stencil_mt
) {
1341 intel_miptree_copy_slice_sw(brw
,
1342 src_mt
, src_level
, src_layer
,
1343 dst_mt
, dst_level
, dst_layer
,
1348 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1349 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1351 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1354 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1355 _mesa_get_format_name(src_mt
->format
),
1356 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1357 _mesa_get_format_name(dst_mt
->format
),
1358 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1361 if (!intel_miptree_blit(brw
,
1362 src_mt
, src_level
, src_layer
, 0, 0, false,
1363 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1364 width
, height
, GL_COPY
)) {
1365 perf_debug("miptree validate blit for %s failed\n",
1366 _mesa_get_format_name(format
));
1368 intel_miptree_copy_slice_sw(brw
,
1369 src_mt
, src_level
, src_layer
,
1370 dst_mt
, dst_level
, dst_layer
,
1376 * Copies the image's current data to the given miptree, and associates that
1377 * miptree with the image.
1379 * If \c invalidate is true, then the actual image data does not need to be
1380 * copied, but the image still needs to be associated to the new miptree (this
1381 * is set to true if we're about to clear the image).
1384 intel_miptree_copy_teximage(struct brw_context
*brw
,
1385 struct intel_texture_image
*intelImage
,
1386 struct intel_mipmap_tree
*dst_mt
,
1389 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1390 struct intel_texture_object
*intel_obj
=
1391 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1392 int level
= intelImage
->base
.Base
.Level
;
1393 const unsigned face
= intelImage
->base
.Base
.Face
;
1394 unsigned start_layer
, end_layer
;
1396 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1398 assert(intelImage
->base
.Base
.Height
);
1400 end_layer
= intelImage
->base
.Base
.Height
- 1;
1401 } else if (face
> 0) {
1405 assert(intelImage
->base
.Base
.Depth
);
1407 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1411 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1412 intel_miptree_copy_slice(brw
,
1418 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1419 intel_obj
->needs_validate
= true;
1423 intel_miptree_init_mcs(struct brw_context
*brw
,
1424 struct intel_mipmap_tree
*mt
,
1427 assert(mt
->mcs_buf
!= NULL
);
1429 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1431 * When MCS buffer is enabled and bound to MSRT, it is required that it
1432 * is cleared prior to any rendering.
1434 * Since we don't use the MCS buffer for any purpose other than rendering,
1435 * it makes sense to just clear it immediately upon allocation.
1437 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1439 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1440 if (unlikely(map
== NULL
)) {
1441 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1442 brw_bo_unreference(mt
->mcs_buf
->bo
);
1447 memset(data
, init_value
, mt
->mcs_buf
->size
);
1448 brw_bo_unmap(mt
->mcs_buf
->bo
);
1451 static struct intel_miptree_aux_buffer
*
1452 intel_mcs_miptree_buf_create(struct brw_context
*brw
,
1453 struct intel_mipmap_tree
*mt
,
1456 unsigned mcs_height
,
1457 uint32_t layout_flags
)
1459 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1460 struct intel_mipmap_tree
*temp_mt
;
1465 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1467 * "The MCS surface must be stored as Tile Y."
1469 layout_flags
|= MIPTREE_LAYOUT_TILING_Y
;
1470 temp_mt
= miptree_create(brw
,
1478 0 /* num_samples */,
1485 buf
->bo
= temp_mt
->bo
;
1486 buf
->offset
= temp_mt
->offset
;
1487 buf
->size
= temp_mt
->total_height
* temp_mt
->pitch
;
1488 buf
->pitch
= temp_mt
->pitch
;
1489 buf
->qpitch
= temp_mt
->qpitch
;
1491 /* Just hang on to the BO which backs the AUX buffer; the rest of the miptree
1492 * structure should go away. We use miptree create simply as a means to make
1493 * sure all the constraints for the buffer are satisfied.
1495 brw_bo_reference(temp_mt
->bo
);
1496 intel_miptree_release(&temp_mt
);
1502 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1503 struct intel_mipmap_tree
*mt
,
1506 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1507 assert(mt
->mcs_buf
== NULL
);
1508 assert((mt
->aux_disable
& INTEL_AUX_DISABLE_MCS
) == 0);
1510 /* Choose the correct format for the MCS buffer. All that really matters
1511 * is that we allocate the right buffer size, since we'll always be
1512 * accessing this miptree using MCS-specific hardware mechanisms, which
1513 * infer the correct format based on num_samples.
1516 switch (num_samples
) {
1519 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1522 format
= MESA_FORMAT_R_UNORM8
;
1525 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1526 * for each sample, plus 8 padding bits).
1528 format
= MESA_FORMAT_R_UINT32
;
1531 /* 64 bits/pixel are required for MCS data when using 16x MSAA (4 bits
1534 format
= MESA_FORMAT_RG_UINT32
;
1537 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1540 /* Multisampled miptrees are only supported for single level. */
1541 assert(mt
->first_level
== 0);
1542 enum isl_aux_state
**aux_state
=
1543 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1548 intel_mcs_miptree_buf_create(brw
, mt
,
1551 mt
->logical_height0
,
1552 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
);
1558 mt
->aux_state
= aux_state
;
1560 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1566 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1567 struct intel_mipmap_tree
*mt
,
1568 bool is_lossless_compressed
)
1570 assert(mt
->mcs_buf
== NULL
);
1571 assert(!(mt
->aux_disable
& (INTEL_AUX_DISABLE_MCS
| INTEL_AUX_DISABLE_CCS
)));
1573 struct isl_surf temp_main_surf
;
1574 struct isl_surf temp_ccs_surf
;
1576 /* Create first an ISL presentation for the main color surface and let ISL
1577 * calculate equivalent CCS surface against it.
1579 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1580 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_ccs_surf
))
1583 assert(temp_ccs_surf
.size
&&
1584 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1586 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1590 enum isl_aux_state
**aux_state
=
1591 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1597 buf
->size
= temp_ccs_surf
.size
;
1598 buf
->pitch
= temp_ccs_surf
.row_pitch
;
1599 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(&temp_ccs_surf
);
1601 /* In case of compression mcs buffer needs to be initialised requiring the
1602 * buffer to be immediately mapped to cpu space for writing. Therefore do
1603 * not use the gpu access flag which can cause an unnecessary delay if the
1604 * backing pages happened to be just used by the GPU.
1606 const uint32_t alloc_flags
=
1607 is_lossless_compressed
? 0 : BO_ALLOC_FOR_RENDER
;
1609 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "ccs-miptree", buf
->size
,
1610 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1618 mt
->aux_state
= aux_state
;
1620 /* From Gen9 onwards single-sampled (non-msrt) auxiliary buffers are
1621 * used for lossless compression which requires similar initialisation
1622 * as multi-sample compression.
1624 if (is_lossless_compressed
) {
1625 /* Hardware sets the auxiliary buffer to all zeroes when it does full
1626 * resolve. Initialize it accordingly in case the first renderer is
1627 * cpu (or other none compression aware party).
1629 * This is also explicitly stated in the spec (MCS Buffer for Render
1631 * "If Software wants to enable Color Compression without Fast clear,
1632 * Software needs to initialize MCS with zeros."
1634 intel_miptree_init_mcs(brw
, mt
, 0);
1635 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_CMS
;
1642 * Helper for intel_miptree_alloc_hiz() that sets
1643 * \c mt->level[level].has_hiz. Return true if and only if
1644 * \c has_hiz was set.
1647 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1648 struct intel_mipmap_tree
*mt
,
1651 assert(mt
->hiz_buf
);
1653 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1654 uint32_t width
= minify(mt
->physical_width0
, level
);
1655 uint32_t height
= minify(mt
->physical_height0
, level
);
1657 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1658 * and the height is 4 aligned. This allows our HiZ support
1659 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1660 * we can grow the width & height to allow the HiZ op to
1661 * force the proper size alignments.
1663 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1664 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1669 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1670 mt
->level
[level
].has_hiz
= true;
1676 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1677 * buffer dimensions and allocates a bo for the hiz buffer.
1679 static struct intel_miptree_hiz_buffer
*
1680 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1681 struct intel_mipmap_tree
*mt
)
1683 unsigned z_width
= mt
->logical_width0
;
1684 unsigned z_height
= mt
->logical_height0
;
1685 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1686 unsigned hz_width
, hz_height
;
1687 struct intel_miptree_hiz_buffer
*buf
= calloc(sizeof(*buf
), 1);
1692 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1693 * adjustments required for Z_Height and Z_Width based on multisampling.
1695 switch (mt
->num_samples
) {
1709 unreachable("unsupported sample count");
1712 const unsigned vertical_align
= 8; /* 'j' in the docs */
1713 const unsigned H0
= z_height
;
1714 const unsigned h0
= ALIGN(H0
, vertical_align
);
1715 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1716 const unsigned Z0
= z_depth
;
1718 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1719 hz_width
= ALIGN(z_width
, 16);
1721 if (mt
->target
== GL_TEXTURE_3D
) {
1725 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1726 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1727 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1728 hz_height
+= h_i
* Z_i
;
1729 H_i
= minify(H_i
, 1);
1730 Z_i
= minify(Z_i
, 1);
1733 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1735 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1737 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1738 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1739 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1742 buf
->aux_base
.bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "hiz",
1743 hz_width
, hz_height
, 1,
1744 I915_TILING_Y
, &buf
->aux_base
.pitch
,
1745 BO_ALLOC_FOR_RENDER
);
1746 if (!buf
->aux_base
.bo
) {
1751 buf
->aux_base
.size
= hz_width
* hz_height
;
1758 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1759 * buffer dimensions and allocates a bo for the hiz buffer.
1761 static struct intel_miptree_hiz_buffer
*
1762 intel_gen8_hiz_buf_create(struct brw_context
*brw
,
1763 struct intel_mipmap_tree
*mt
)
1765 unsigned z_width
= mt
->logical_width0
;
1766 unsigned z_height
= mt
->logical_height0
;
1767 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1768 unsigned hz_width
, hz_height
;
1769 struct intel_miptree_hiz_buffer
*buf
= calloc(sizeof(*buf
), 1);
1774 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1775 * adjustments required for Z_Height and Z_Width based on multisampling.
1778 switch (mt
->num_samples
) {
1792 unreachable("unsupported sample count");
1796 const unsigned vertical_align
= 8; /* 'j' in the docs */
1797 const unsigned H0
= z_height
;
1798 const unsigned h0
= ALIGN(H0
, vertical_align
);
1799 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1800 const unsigned Z0
= z_depth
;
1802 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1803 hz_width
= ALIGN(z_width
, 16);
1807 unsigned sum_h_i
= 0;
1808 unsigned hz_height_3d_sum
= 0;
1809 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1810 unsigned i
= level
- mt
->first_level
;
1811 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1812 /* sum(i=2 to m; h_i) */
1816 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1817 hz_height_3d_sum
+= h_i
* Z_i
;
1818 H_i
= minify(H_i
, 1);
1819 Z_i
= minify(Z_i
, 1);
1821 /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
1822 buf
->aux_base
.qpitch
= h0
+ MAX2(h1
, sum_h_i
);
1824 if (mt
->target
== GL_TEXTURE_3D
) {
1825 /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1826 hz_height
= DIV_ROUND_UP(hz_height_3d_sum
, 2);
1828 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
1829 hz_height
= DIV_ROUND_UP(buf
->aux_base
.qpitch
, 2 * 8) * 8 * Z0
;
1832 buf
->aux_base
.bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "hiz",
1833 hz_width
, hz_height
, 1,
1834 I915_TILING_Y
, &buf
->aux_base
.pitch
,
1835 BO_ALLOC_FOR_RENDER
);
1836 if (!buf
->aux_base
.bo
) {
1841 buf
->aux_base
.size
= hz_width
* hz_height
;
1847 static struct intel_miptree_hiz_buffer
*
1848 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
1849 struct intel_mipmap_tree
*mt
)
1851 struct intel_miptree_hiz_buffer
*buf
= calloc(sizeof(*buf
), 1);
1852 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1855 layout_flags
|= MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
;
1860 layout_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
1861 buf
->mt
= intel_miptree_create(brw
,
1867 mt
->logical_height0
,
1876 buf
->aux_base
.bo
= buf
->mt
->bo
;
1877 buf
->aux_base
.size
= buf
->mt
->total_height
* buf
->mt
->pitch
;
1878 buf
->aux_base
.pitch
= buf
->mt
->pitch
;
1879 buf
->aux_base
.qpitch
= buf
->mt
->qpitch
* 2;
1885 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
1886 struct intel_mipmap_tree
*mt
)
1891 if (mt
->hiz_buf
!= NULL
)
1894 if (mt
->aux_disable
& INTEL_AUX_DISABLE_HIZ
)
1897 switch (mt
->format
) {
1898 case MESA_FORMAT_Z_FLOAT32
:
1899 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
1900 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
1901 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
1902 case MESA_FORMAT_Z_UNORM16
:
1910 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1911 struct intel_mipmap_tree
*mt
)
1913 assert(mt
->hiz_buf
== NULL
);
1914 assert((mt
->aux_disable
& INTEL_AUX_DISABLE_HIZ
) == 0);
1916 enum isl_aux_state
**aux_state
=
1917 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1921 if (brw
->gen
== 7) {
1922 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
1923 } else if (brw
->gen
>= 8) {
1924 mt
->hiz_buf
= intel_gen8_hiz_buf_create(brw
, mt
);
1926 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
1934 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1935 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1937 mt
->aux_state
= aux_state
;
1943 * Can the miptree sample using the hiz buffer?
1946 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1947 struct intel_mipmap_tree
*mt
)
1949 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
1950 * so keep things conservative for now and never enable it unless we're SKL+.
1960 /* It seems the hardware won't fallback to the depth buffer if some of the
1961 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1962 * of the texture to be HiZ enabled.
1964 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1965 if (!intel_miptree_level_has_hiz(mt
, level
))
1969 /* If compressed multisampling is enabled, then we use it for the auxiliary
1972 * From the BDW PRM (Volume 2d: Command Reference: Structures
1973 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1975 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1976 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1978 * There is no such blurb for 1D textures, but there is sufficient evidence
1979 * that this is broken on SKL+.
1981 return (mt
->num_samples
<= 1 &&
1982 mt
->target
!= GL_TEXTURE_3D
&&
1983 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1987 * Does the miptree slice have hiz enabled?
1990 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
1992 intel_miptree_check_level_layer(mt
, level
, 0);
1993 return mt
->level
[level
].has_hiz
;
1997 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
1998 unsigned start_level
, unsigned num_levels
,
1999 unsigned start_layer
, unsigned num_layers
)
2001 assert(_mesa_is_format_color_format(mt
->format
));
2006 /* Clamp the level range to fit the miptree */
2007 assert(start_level
+ num_levels
>= start_level
);
2008 const uint32_t last_level
=
2009 MIN2(mt
->last_level
, start_level
+ num_levels
- 1);
2010 start_level
= MAX2(mt
->first_level
, start_level
);
2011 num_levels
= last_level
- start_level
+ 1;
2013 for (uint32_t level
= start_level
; level
<= last_level
; level
++) {
2014 const uint32_t level_layers
= MIN2(num_layers
, mt
->level
[level
].depth
);
2015 for (unsigned a
= 0; a
< level_layers
; a
++) {
2016 enum isl_aux_state aux_state
=
2017 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
2018 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
2019 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2028 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2029 const struct intel_mipmap_tree
*mt
,
2030 unsigned level
, unsigned layer
)
2033 if ((mt
->aux_disable
& INTEL_AUX_DISABLE_CCS
) || !mt
->mcs_buf
)
2036 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2037 assert(brw
->gen
>= 8 ||
2038 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2040 /* Compression of arrayed msaa surfaces is supported. */
2041 if (mt
->num_samples
> 1)
2044 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2045 assert(brw
->gen
>= 8 || (layer
== 0 && mt
->logical_depth0
== 1));
2051 static enum blorp_fast_clear_op
2052 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2053 bool ccs_supported
, bool fast_clear_supported
)
2055 assert(ccs_supported
== fast_clear_supported
);
2057 switch (aux_state
) {
2058 case ISL_AUX_STATE_CLEAR
:
2059 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2061 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2063 return BLORP_FAST_CLEAR_OP_NONE
;
2065 case ISL_AUX_STATE_PASS_THROUGH
:
2066 return BLORP_FAST_CLEAR_OP_NONE
;
2068 case ISL_AUX_STATE_RESOLVED
:
2069 case ISL_AUX_STATE_AUX_INVALID
:
2070 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2074 unreachable("Invalid aux state for CCS_D");
2077 static enum blorp_fast_clear_op
2078 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2079 bool ccs_supported
, bool fast_clear_supported
)
2081 switch (aux_state
) {
2082 case ISL_AUX_STATE_CLEAR
:
2083 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2085 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2086 else if (!fast_clear_supported
)
2087 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2089 return BLORP_FAST_CLEAR_OP_NONE
;
2091 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2093 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2095 return BLORP_FAST_CLEAR_OP_NONE
;
2097 case ISL_AUX_STATE_PASS_THROUGH
:
2098 return BLORP_FAST_CLEAR_OP_NONE
;
2100 case ISL_AUX_STATE_RESOLVED
:
2101 case ISL_AUX_STATE_AUX_INVALID
:
2105 unreachable("Invalid aux state for CCS_E");
2109 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2110 struct intel_mipmap_tree
*mt
,
2111 uint32_t level
, uint32_t layer
,
2113 bool fast_clear_supported
)
2115 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2117 enum blorp_fast_clear_op resolve_op
;
2118 if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
2119 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_supported
,
2120 fast_clear_supported
);
2122 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_supported
,
2123 fast_clear_supported
);
2126 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2127 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2128 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2130 switch (resolve_op
) {
2131 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2132 /* The CCS full resolve operation destroys the CCS and sets it to the
2133 * pass-through state. (You can also think of this as being both a
2134 * resolve and an ambiguate in one operation.)
2136 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2137 ISL_AUX_STATE_PASS_THROUGH
);
2140 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2141 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2142 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2146 unreachable("Invalid resolve op");
2152 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2153 struct intel_mipmap_tree
*mt
,
2154 uint32_t level
, uint32_t layer
,
2155 bool written_with_ccs
)
2157 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2159 if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
2160 switch (aux_state
) {
2161 case ISL_AUX_STATE_CLEAR
:
2162 assert(written_with_ccs
);
2163 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2164 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2167 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2168 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2169 assert(written_with_ccs
);
2170 break; /* Nothing to do */
2172 case ISL_AUX_STATE_PASS_THROUGH
:
2173 if (written_with_ccs
) {
2174 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2175 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2181 case ISL_AUX_STATE_RESOLVED
:
2182 case ISL_AUX_STATE_AUX_INVALID
:
2183 unreachable("Invalid aux state for CCS_E");
2186 /* CCS_D is a bit simpler */
2187 switch (aux_state
) {
2188 case ISL_AUX_STATE_CLEAR
:
2189 assert(written_with_ccs
);
2190 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2191 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2194 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2195 assert(written_with_ccs
);
2196 break; /* Nothing to do */
2198 case ISL_AUX_STATE_PASS_THROUGH
:
2202 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2203 case ISL_AUX_STATE_RESOLVED
:
2204 case ISL_AUX_STATE_AUX_INVALID
:
2205 unreachable("Invalid aux state for CCS_D");
2211 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2212 struct intel_mipmap_tree
*mt
,
2213 uint32_t level
, uint32_t layer
,
2214 bool written_with_aux
)
2216 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2217 case ISL_AUX_STATE_CLEAR
:
2218 assert(written_with_aux
);
2219 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2220 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2223 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2224 assert(written_with_aux
);
2225 break; /* Nothing to do */
2227 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2228 case ISL_AUX_STATE_RESOLVED
:
2229 case ISL_AUX_STATE_PASS_THROUGH
:
2230 case ISL_AUX_STATE_AUX_INVALID
:
2231 unreachable("Invalid aux state for MCS");
2236 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2237 struct intel_mipmap_tree
*mt
,
2238 uint32_t level
, uint32_t layer
,
2239 bool hiz_supported
, bool fast_clear_supported
)
2241 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2242 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2243 case ISL_AUX_STATE_CLEAR
:
2244 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2245 if (!hiz_supported
|| !fast_clear_supported
)
2246 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2249 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2251 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2254 case ISL_AUX_STATE_PASS_THROUGH
:
2255 case ISL_AUX_STATE_RESOLVED
:
2258 case ISL_AUX_STATE_AUX_INVALID
:
2260 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2264 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2265 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2268 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2269 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2270 ISL_AUX_STATE_RESOLVED
);
2273 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2274 /* The HiZ resolve operation is actually an ambiguate */
2275 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2276 ISL_AUX_STATE_PASS_THROUGH
);
2280 unreachable("Invalid HiZ op");
2286 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2287 struct intel_mipmap_tree
*mt
,
2288 uint32_t level
, uint32_t layer
,
2289 bool written_with_hiz
)
2291 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2292 case ISL_AUX_STATE_CLEAR
:
2293 assert(written_with_hiz
);
2294 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2295 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2298 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2299 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2300 assert(written_with_hiz
);
2301 break; /* Nothing to do */
2303 case ISL_AUX_STATE_RESOLVED
:
2304 if (written_with_hiz
) {
2305 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2306 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2308 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2309 ISL_AUX_STATE_AUX_INVALID
);
2313 case ISL_AUX_STATE_PASS_THROUGH
:
2314 if (written_with_hiz
) {
2315 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2316 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2320 case ISL_AUX_STATE_AUX_INVALID
:
2321 assert(!written_with_hiz
);
2326 static inline uint32_t
2327 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
2328 uint32_t start_level
, uint32_t num_levels
)
2330 assert(start_level
>= mt
->first_level
);
2331 assert(start_level
<= mt
->last_level
);
2333 if (num_levels
== INTEL_REMAINING_LAYERS
)
2334 num_levels
= mt
->last_level
- start_level
+ 1;
2335 /* Check for overflow */
2336 assert(start_level
+ num_levels
>= start_level
);
2337 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
2342 static inline uint32_t
2343 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
2344 uint32_t start_layer
, uint32_t num_layers
)
2346 assert(level
<= mt
->last_level
);
2347 uint32_t total_num_layers
= mt
->level
[level
].depth
;
2349 assert(start_layer
< total_num_layers
);
2350 if (num_layers
== INTEL_REMAINING_LAYERS
)
2351 num_layers
= total_num_layers
- start_layer
;
2352 /* Check for overflow */
2353 assert(start_layer
+ num_layers
>= start_layer
);
2354 assert(start_layer
+ num_layers
<= total_num_layers
);
2360 intel_miptree_prepare_access(struct brw_context
*brw
,
2361 struct intel_mipmap_tree
*mt
,
2362 uint32_t start_level
, uint32_t num_levels
,
2363 uint32_t start_layer
, uint32_t num_layers
,
2364 bool aux_supported
, bool fast_clear_supported
)
2366 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2368 if (_mesa_is_format_color_format(mt
->format
)) {
2372 if (mt
->num_samples
> 1) {
2373 /* Nothing to do for MSAA */
2374 assert(aux_supported
&& fast_clear_supported
);
2376 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2377 const uint32_t level
= start_level
+ l
;
2378 const uint32_t level_layers
=
2379 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2380 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2381 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2382 start_layer
+ a
, aux_supported
,
2383 fast_clear_supported
);
2387 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2388 /* Nothing to do for stencil */
2393 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2394 const uint32_t level
= start_level
+ l
;
2395 if (!intel_miptree_level_has_hiz(mt
, level
))
2398 const uint32_t level_layers
=
2399 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2400 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2401 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2403 fast_clear_supported
);
2410 intel_miptree_finish_write(struct brw_context
*brw
,
2411 struct intel_mipmap_tree
*mt
, uint32_t level
,
2412 uint32_t start_layer
, uint32_t num_layers
,
2413 bool written_with_aux
)
2415 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2417 if (_mesa_is_format_color_format(mt
->format
)) {
2421 if (mt
->num_samples
> 1) {
2422 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2423 intel_miptree_finish_mcs_write(brw
, mt
, level
, start_layer
+ a
,
2427 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2428 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2432 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2433 /* Nothing to do for stencil */
2435 if (!intel_miptree_level_has_hiz(mt
, level
))
2438 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2439 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2446 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2447 uint32_t level
, uint32_t layer
)
2449 intel_miptree_check_level_layer(mt
, level
, layer
);
2451 if (_mesa_is_format_color_format(mt
->format
)) {
2452 assert(mt
->mcs_buf
!= NULL
);
2453 assert(mt
->num_samples
<= 1 || mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
2454 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2455 unreachable("Cannot get aux state for stencil");
2457 assert(intel_miptree_level_has_hiz(mt
, level
));
2460 return mt
->aux_state
[level
][layer
];
2464 intel_miptree_set_aux_state(struct brw_context
*brw
,
2465 struct intel_mipmap_tree
*mt
, uint32_t level
,
2466 uint32_t start_layer
, uint32_t num_layers
,
2467 enum isl_aux_state aux_state
)
2469 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2471 if (_mesa_is_format_color_format(mt
->format
)) {
2472 assert(mt
->mcs_buf
!= NULL
);
2473 assert(mt
->num_samples
<= 1 || mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
2474 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2475 unreachable("Cannot get aux state for stencil");
2477 assert(intel_miptree_level_has_hiz(mt
, level
));
2480 for (unsigned a
= 0; a
< num_layers
; a
++)
2481 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2484 /* On Gen9 color buffers may be compressed by the hardware (lossless
2485 * compression). There are, however, format restrictions and care needs to be
2486 * taken that the sampler engine is capable for re-interpreting a buffer with
2487 * format different the buffer was originally written with.
2489 * For example, SRGB formats are not compressible and the sampler engine isn't
2490 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2491 * color buffer needs to be resolved so that the sampling surface can be
2492 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2496 can_texture_with_ccs(struct brw_context
*brw
,
2497 struct intel_mipmap_tree
*mt
,
2498 mesa_format view_format
)
2500 if (!intel_miptree_is_lossless_compressed(brw
, mt
))
2503 enum isl_format isl_mt_format
= brw_isl_format_for_mesa_format(mt
->format
);
2504 enum isl_format isl_view_format
= brw_isl_format_for_mesa_format(view_format
);
2506 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2507 isl_mt_format
, isl_view_format
)) {
2508 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2509 _mesa_get_format_name(view_format
),
2510 _mesa_get_format_name(mt
->format
));
2518 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2519 struct intel_mipmap_tree
*mt
,
2520 mesa_format view_format
,
2521 uint32_t start_level
, uint32_t num_levels
,
2522 uint32_t start_layer
, uint32_t num_layers
,
2523 bool *aux_supported_out
)
2525 bool aux_supported
, clear_supported
;
2526 if (_mesa_is_format_color_format(mt
->format
)) {
2527 if (mt
->num_samples
> 1) {
2528 aux_supported
= clear_supported
= true;
2530 aux_supported
= can_texture_with_ccs(brw
, mt
, view_format
);
2532 /* Clear color is specified as ints or floats and the conversion is
2533 * done by the sampler. If we have a texture view, we would have to
2534 * perform the clear color conversion manually. Just disable clear
2537 clear_supported
= aux_supported
&& (mt
->format
== view_format
);
2539 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2540 aux_supported
= clear_supported
= false;
2542 aux_supported
= clear_supported
= intel_miptree_sample_with_hiz(brw
, mt
);
2545 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2546 start_layer
, num_layers
,
2547 aux_supported
, clear_supported
);
2548 if (aux_supported_out
)
2549 *aux_supported_out
= aux_supported
;
2553 intel_miptree_prepare_texture(struct brw_context
*brw
,
2554 struct intel_mipmap_tree
*mt
,
2555 mesa_format view_format
,
2556 bool *aux_supported_out
)
2558 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2559 0, INTEL_REMAINING_LEVELS
,
2560 0, INTEL_REMAINING_LAYERS
,
2565 intel_miptree_prepare_image(struct brw_context
*brw
,
2566 struct intel_mipmap_tree
*mt
)
2568 /* The data port doesn't understand any compression */
2569 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2570 0, INTEL_REMAINING_LAYERS
, false, false);
2574 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2575 struct intel_mipmap_tree
*mt
, uint32_t level
,
2576 uint32_t start_layer
, uint32_t num_layers
)
2578 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->format
, level
, 1,
2579 start_layer
, num_layers
, NULL
);
2583 intel_miptree_prepare_render(struct brw_context
*brw
,
2584 struct intel_mipmap_tree
*mt
, uint32_t level
,
2585 uint32_t start_layer
, uint32_t layer_count
,
2588 /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
2589 * the single-sampled color renderbuffers because the CCS buffer isn't
2590 * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
2591 * enabled because otherwise the surface state will be programmed with
2592 * the linear equivalent format anyway.
2594 if (brw
->gen
== 9 && srgb_enabled
&& mt
->num_samples
<= 1 &&
2595 _mesa_get_srgb_format_linear(mt
->format
) != mt
->format
) {
2597 /* Lossless compression is not supported for SRGB formats, it
2598 * should be impossible to get here with such surfaces.
2600 assert(!intel_miptree_is_lossless_compressed(brw
, mt
));
2601 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2605 /* For layered rendering non-compressed fast cleared buffers need to be
2606 * resolved. Surface state can carry only one fast color clear value
2607 * while each layer may have its own fast clear color value. For
2608 * compressed buffers color value is available in the color buffer.
2610 if (layer_count
> 1 &&
2611 !(mt
->aux_disable
& INTEL_AUX_DISABLE_CCS
) &&
2612 !intel_miptree_is_lossless_compressed(brw
, mt
)) {
2613 assert(brw
->gen
>= 8);
2615 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2621 intel_miptree_finish_render(struct brw_context
*brw
,
2622 struct intel_mipmap_tree
*mt
, uint32_t level
,
2623 uint32_t start_layer
, uint32_t layer_count
)
2625 assert(_mesa_is_format_color_format(mt
->format
));
2626 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2627 mt
->mcs_buf
!= NULL
);
2631 intel_miptree_prepare_depth(struct brw_context
*brw
,
2632 struct intel_mipmap_tree
*mt
, uint32_t level
,
2633 uint32_t start_layer
, uint32_t layer_count
)
2635 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2636 mt
->hiz_buf
!= NULL
, mt
->hiz_buf
!= NULL
);
2640 intel_miptree_finish_depth(struct brw_context
*brw
,
2641 struct intel_mipmap_tree
*mt
, uint32_t level
,
2642 uint32_t start_layer
, uint32_t layer_count
,
2645 if (depth_written
) {
2646 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2647 mt
->hiz_buf
!= NULL
);
2652 * Make it possible to share the BO backing the given miptree with another
2653 * process or another miptree.
2655 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2656 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2657 * ensure that no MCS buffer gets allocated in the future.
2659 * HiZ is similarly unsafe with shared buffers.
2662 intel_miptree_make_shareable(struct brw_context
*brw
,
2663 struct intel_mipmap_tree
*mt
)
2665 /* MCS buffers are also used for multisample buffers, but we can't resolve
2666 * away a multisample MCS buffer because it's an integral part of how the
2667 * pixel data is stored. Fortunately this code path should never be
2668 * reached for multisample buffers.
2670 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
|| mt
->num_samples
<= 1);
2672 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2673 0, INTEL_REMAINING_LAYERS
, false, false);
2676 mt
->aux_disable
|= (INTEL_AUX_DISABLE_CCS
| INTEL_AUX_DISABLE_MCS
);
2677 brw_bo_unreference(mt
->mcs_buf
->bo
);
2681 /* Any pending MCS/CCS operations are no longer needed. Trying to
2682 * execute any will likely crash due to the missing aux buffer. So let's
2683 * delete all pending ops.
2685 free(mt
->aux_state
);
2686 mt
->aux_state
= NULL
;
2690 mt
->aux_disable
|= INTEL_AUX_DISABLE_HIZ
;
2691 intel_miptree_hiz_buffer_free(mt
->hiz_buf
);
2694 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2695 mt
->level
[l
].has_hiz
= false;
2698 /* Any pending HiZ operations are no longer needed. Trying to execute
2699 * any will likely crash due to the missing aux buffer. So let's delete
2702 free(mt
->aux_state
);
2703 mt
->aux_state
= NULL
;
2709 * \brief Get pointer offset into stencil buffer.
2711 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2712 * must decode the tile's layout in software.
2715 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2717 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2719 * Even though the returned offset is always positive, the return type is
2721 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2722 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2725 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2727 uint32_t tile_size
= 4096;
2728 uint32_t tile_width
= 64;
2729 uint32_t tile_height
= 64;
2730 uint32_t row_size
= 64 * stride
;
2732 uint32_t tile_x
= x
/ tile_width
;
2733 uint32_t tile_y
= y
/ tile_height
;
2735 /* The byte's address relative to the tile's base addres. */
2736 uint32_t byte_x
= x
% tile_width
;
2737 uint32_t byte_y
= y
% tile_height
;
2739 uintptr_t u
= tile_y
* row_size
2740 + tile_x
* tile_size
2741 + 512 * (byte_x
/ 8)
2743 + 32 * ((byte_y
/ 4) % 2)
2744 + 16 * ((byte_x
/ 4) % 2)
2745 + 8 * ((byte_y
/ 2) % 2)
2746 + 4 * ((byte_x
/ 2) % 2)
2751 /* adjust for bit6 swizzling */
2752 if (((byte_x
/ 8) % 2) == 1) {
2753 if (((byte_y
/ 8) % 2) == 0) {
2765 intel_miptree_updownsample(struct brw_context
*brw
,
2766 struct intel_mipmap_tree
*src
,
2767 struct intel_mipmap_tree
*dst
)
2769 brw_blorp_blit_miptrees(brw
,
2770 src
, 0 /* level */, 0 /* layer */,
2771 src
->format
, SWIZZLE_XYZW
,
2772 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2774 src
->logical_width0
, src
->logical_height0
,
2776 dst
->logical_width0
, dst
->logical_height0
,
2777 GL_NEAREST
, false, false /*mirror x, y*/,
2780 if (src
->stencil_mt
) {
2781 brw_blorp_blit_miptrees(brw
,
2782 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2783 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2784 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2785 dst
->stencil_mt
->format
,
2787 src
->logical_width0
, src
->logical_height0
,
2789 dst
->logical_width0
, dst
->logical_height0
,
2790 GL_NEAREST
, false, false /*mirror x, y*/,
2791 false, false /* decode/encode srgb */);
2796 intel_update_r8stencil(struct brw_context
*brw
,
2797 struct intel_mipmap_tree
*mt
)
2799 assert(brw
->gen
>= 7);
2800 struct intel_mipmap_tree
*src
=
2801 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2802 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
2805 if (!mt
->r8stencil_mt
) {
2806 const uint32_t r8stencil_flags
=
2807 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
| MIPTREE_LAYOUT_TILING_Y
|
2808 MIPTREE_LAYOUT_DISABLE_AUX
;
2809 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2810 mt
->r8stencil_mt
= intel_miptree_create(brw
,
2812 MESA_FORMAT_R_UINT8
,
2815 src
->logical_width0
,
2816 src
->logical_height0
,
2817 src
->logical_depth0
,
2820 assert(mt
->r8stencil_mt
);
2823 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2825 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2826 const unsigned depth
= src
->level
[level
].depth
;
2828 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2829 brw_blorp_copy_miptrees(brw
,
2833 minify(src
->logical_width0
, level
),
2834 minify(src
->logical_height0
, level
));
2838 brw_render_cache_set_check_flush(brw
, dst
->bo
);
2839 src
->r8stencil_needs_update
= false;
2843 intel_miptree_map_raw(struct brw_context
*brw
,
2844 struct intel_mipmap_tree
*mt
,
2847 struct brw_bo
*bo
= mt
->bo
;
2849 if (brw_batch_references(&brw
->batch
, bo
))
2850 intel_batchbuffer_flush(brw
);
2852 return brw_bo_map(brw
, bo
, mode
);
2856 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2858 brw_bo_unmap(mt
->bo
);
2862 intel_miptree_map_gtt(struct brw_context
*brw
,
2863 struct intel_mipmap_tree
*mt
,
2864 struct intel_miptree_map
*map
,
2865 unsigned int level
, unsigned int slice
)
2867 unsigned int bw
, bh
;
2869 unsigned int image_x
, image_y
;
2870 intptr_t x
= map
->x
;
2871 intptr_t y
= map
->y
;
2873 /* For compressed formats, the stride is the number of bytes per
2874 * row of blocks. intel_miptree_get_image_offset() already does
2877 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2878 assert(y
% bh
== 0);
2879 assert(x
% bw
== 0);
2883 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
) + mt
->offset
;
2888 /* Note that in the case of cube maps, the caller must have passed the
2889 * slice number referencing the face.
2891 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2895 map
->stride
= mt
->pitch
;
2896 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2899 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2900 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2901 map
->x
, map
->y
, map
->w
, map
->h
,
2902 mt
, _mesa_get_format_name(mt
->format
),
2903 x
, y
, map
->ptr
, map
->stride
);
2907 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2909 intel_miptree_unmap_raw(mt
);
2913 intel_miptree_map_blit(struct brw_context
*brw
,
2914 struct intel_mipmap_tree
*mt
,
2915 struct intel_miptree_map
*map
,
2916 unsigned int level
, unsigned int slice
)
2918 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2919 /* first_level */ 0,
2923 MIPTREE_LAYOUT_TILING_NONE
);
2925 if (!map
->linear_mt
) {
2926 fprintf(stderr
, "Failed to allocate blit temporary\n");
2929 map
->stride
= map
->linear_mt
->pitch
;
2931 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2932 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2933 * invalidate is set, since we'll be writing the whole rectangle from our
2934 * temporary buffer back out.
2936 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2937 if (!intel_miptree_copy(brw
,
2938 mt
, level
, slice
, map
->x
, map
->y
,
2939 map
->linear_mt
, 0, 0, 0, 0,
2941 fprintf(stderr
, "Failed to blit\n");
2946 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
2948 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2949 map
->x
, map
->y
, map
->w
, map
->h
,
2950 mt
, _mesa_get_format_name(mt
->format
),
2951 level
, slice
, map
->ptr
, map
->stride
);
2956 intel_miptree_release(&map
->linear_mt
);
2962 intel_miptree_unmap_blit(struct brw_context
*brw
,
2963 struct intel_mipmap_tree
*mt
,
2964 struct intel_miptree_map
*map
,
2968 struct gl_context
*ctx
= &brw
->ctx
;
2970 intel_miptree_unmap_raw(map
->linear_mt
);
2972 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2973 bool ok
= intel_miptree_copy(brw
,
2974 map
->linear_mt
, 0, 0, 0, 0,
2975 mt
, level
, slice
, map
->x
, map
->y
,
2977 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2980 intel_miptree_release(&map
->linear_mt
);
2984 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2986 #if defined(USE_SSE41)
2988 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2989 struct intel_mipmap_tree
*mt
,
2990 struct intel_miptree_map
*map
,
2991 unsigned int level
, unsigned int slice
)
2993 assert(map
->mode
& GL_MAP_READ_BIT
);
2994 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2996 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2997 map
->x
, map
->y
, map
->w
, map
->h
,
2998 mt
, _mesa_get_format_name(mt
->format
),
2999 level
, slice
, map
->ptr
, map
->stride
);
3001 /* Map the original image */
3004 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3008 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3014 src
+= image_y
* mt
->pitch
;
3015 src
+= image_x
* mt
->cpp
;
3017 /* Due to the pixel offsets for the particular image being mapped, our
3018 * src pointer may not be 16-byte aligned. However, if the pitch is
3019 * divisible by 16, then the amount by which it's misaligned will remain
3020 * consistent from row to row.
3022 assert((mt
->pitch
% 16) == 0);
3023 const int misalignment
= ((uintptr_t) src
) & 15;
3025 /* Create an untiled temporary buffer for the mapping. */
3026 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3028 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3030 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3031 /* Offset the destination so it has the same misalignment as src. */
3032 map
->ptr
= map
->buffer
+ misalignment
;
3034 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3036 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3037 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3038 void *src_ptr
= src
+ y
* mt
->pitch
;
3040 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3043 intel_miptree_unmap_raw(mt
);
3047 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3048 struct intel_mipmap_tree
*mt
,
3049 struct intel_miptree_map
*map
,
3053 _mesa_align_free(map
->buffer
);
3060 intel_miptree_map_s8(struct brw_context
*brw
,
3061 struct intel_mipmap_tree
*mt
,
3062 struct intel_miptree_map
*map
,
3063 unsigned int level
, unsigned int slice
)
3065 map
->stride
= map
->w
;
3066 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3070 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3071 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3072 * invalidate is set, since we'll be writing the whole rectangle from our
3073 * temporary buffer back out.
3075 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3076 uint8_t *untiled_s8_map
= map
->ptr
;
3077 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3078 unsigned int image_x
, image_y
;
3080 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3082 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3083 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3084 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
3085 x
+ image_x
+ map
->x
,
3086 y
+ image_y
+ map
->y
,
3087 brw
->has_swizzling
);
3088 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3092 intel_miptree_unmap_raw(mt
);
3094 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3095 map
->x
, map
->y
, map
->w
, map
->h
,
3096 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3098 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3099 map
->x
, map
->y
, map
->w
, map
->h
,
3100 mt
, map
->ptr
, map
->stride
);
3105 intel_miptree_unmap_s8(struct brw_context
*brw
,
3106 struct intel_mipmap_tree
*mt
,
3107 struct intel_miptree_map
*map
,
3111 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3112 unsigned int image_x
, image_y
;
3113 uint8_t *untiled_s8_map
= map
->ptr
;
3114 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3116 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3118 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3119 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3120 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
3121 image_x
+ x
+ map
->x
,
3122 image_y
+ y
+ map
->y
,
3123 brw
->has_swizzling
);
3124 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3128 intel_miptree_unmap_raw(mt
);
3135 intel_miptree_map_etc(struct brw_context
*brw
,
3136 struct intel_mipmap_tree
*mt
,
3137 struct intel_miptree_map
*map
,
3141 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3142 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3143 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3146 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3147 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3149 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3150 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3151 map
->w
, map
->h
, 1));
3152 map
->ptr
= map
->buffer
;
3156 intel_miptree_unmap_etc(struct brw_context
*brw
,
3157 struct intel_mipmap_tree
*mt
,
3158 struct intel_miptree_map
*map
,
3164 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3169 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3170 + image_y
* mt
->pitch
3171 + image_x
* mt
->cpp
;
3173 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3174 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
3175 map
->ptr
, map
->stride
,
3178 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
3179 map
->ptr
, map
->stride
,
3180 map
->w
, map
->h
, mt
->etc_format
);
3182 intel_miptree_unmap_raw(mt
);
3187 * Mapping function for packed depth/stencil miptrees backed by real separate
3188 * miptrees for depth and stencil.
3190 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3191 * separate from the depth buffer. Yet at the GL API level, we have to expose
3192 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3193 * be able to map that memory for texture storage and glReadPixels-type
3194 * operations. We give Mesa core that access by mallocing a temporary and
3195 * copying the data between the actual backing store and the temporary.
3198 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3199 struct intel_mipmap_tree
*mt
,
3200 struct intel_miptree_map
*map
,
3201 unsigned int level
, unsigned int slice
)
3203 struct intel_mipmap_tree
*z_mt
= mt
;
3204 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3205 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3206 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3208 map
->stride
= map
->w
* packed_bpp
;
3209 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3213 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3214 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3215 * invalidate is set, since we'll be writing the whole rectangle from our
3216 * temporary buffer back out.
3218 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3219 uint32_t *packed_map
= map
->ptr
;
3220 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3221 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3222 unsigned int s_image_x
, s_image_y
;
3223 unsigned int z_image_x
, z_image_y
;
3225 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3226 &s_image_x
, &s_image_y
);
3227 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3228 &z_image_x
, &z_image_y
);
3230 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3231 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3232 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3233 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
3236 brw
->has_swizzling
);
3237 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3239 (map_x
+ z_image_x
));
3240 uint8_t s
= s_map
[s_offset
];
3241 uint32_t z
= z_map
[z_offset
];
3243 if (map_z32f_x24s8
) {
3244 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3245 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3247 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3252 intel_miptree_unmap_raw(s_mt
);
3253 intel_miptree_unmap_raw(z_mt
);
3255 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3257 map
->x
, map
->y
, map
->w
, map
->h
,
3258 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3259 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3260 map
->ptr
, map
->stride
);
3262 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3263 map
->x
, map
->y
, map
->w
, map
->h
,
3264 mt
, map
->ptr
, map
->stride
);
3269 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3270 struct intel_mipmap_tree
*mt
,
3271 struct intel_miptree_map
*map
,
3275 struct intel_mipmap_tree
*z_mt
= mt
;
3276 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3277 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3279 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3280 uint32_t *packed_map
= map
->ptr
;
3281 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3282 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3283 unsigned int s_image_x
, s_image_y
;
3284 unsigned int z_image_x
, z_image_y
;
3286 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3287 &s_image_x
, &s_image_y
);
3288 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3289 &z_image_x
, &z_image_y
);
3291 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3292 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3293 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
3294 x
+ s_image_x
+ map
->x
,
3295 y
+ s_image_y
+ map
->y
,
3296 brw
->has_swizzling
);
3297 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3299 (x
+ z_image_x
+ map
->x
));
3301 if (map_z32f_x24s8
) {
3302 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3303 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3305 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3306 s_map
[s_offset
] = packed
>> 24;
3307 z_map
[z_offset
] = packed
;
3312 intel_miptree_unmap_raw(s_mt
);
3313 intel_miptree_unmap_raw(z_mt
);
3315 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3317 map
->x
, map
->y
, map
->w
, map
->h
,
3318 z_mt
, _mesa_get_format_name(z_mt
->format
),
3319 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3320 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3321 map
->ptr
, map
->stride
);
3328 * Create and attach a map to the miptree at (level, slice). Return the
3331 static struct intel_miptree_map
*
3332 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3341 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3346 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3347 mt
->level
[level
].slice
[slice
].map
= map
;
3359 * Release the map at (level, slice).
3362 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3366 struct intel_miptree_map
**map
;
3368 map
= &mt
->level
[level
].slice
[slice
].map
;
3374 can_blit_slice(struct intel_mipmap_tree
*mt
,
3375 unsigned int level
, unsigned int slice
)
3377 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3378 if (mt
->pitch
>= 32768)
3385 use_intel_mipree_map_blit(struct brw_context
*brw
,
3386 struct intel_mipmap_tree
*mt
,
3392 /* It's probably not worth swapping to the blit ring because of
3393 * all the overhead involved.
3395 !(mode
& GL_MAP_WRITE_BIT
) &&
3397 (mt
->tiling
== I915_TILING_X
||
3398 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3399 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
) ||
3400 /* Fast copy blit on skl+ supports all tiling formats. */
3402 can_blit_slice(mt
, level
, slice
))
3405 if (mt
->tiling
!= I915_TILING_NONE
&&
3406 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3407 assert(can_blit_slice(mt
, level
, slice
));
3415 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3416 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3417 * arithmetic overflow.
3419 * If you call this function and use \a out_stride, then you're doing pointer
3420 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3421 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3422 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3423 * which usually have type uint32_t or GLuint.
3426 intel_miptree_map(struct brw_context
*brw
,
3427 struct intel_mipmap_tree
*mt
,
3436 ptrdiff_t *out_stride
)
3438 struct intel_miptree_map
*map
;
3440 assert(mt
->num_samples
<= 1);
3442 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3449 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3450 map
->mode
& GL_MAP_WRITE_BIT
);
3452 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3453 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3454 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3455 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3456 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3457 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3458 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3459 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3460 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3461 #if defined(USE_SSE41)
3462 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3463 !mt
->compressed
&& cpu_has_sse4_1
&&
3464 (mt
->pitch
% 16 == 0)) {
3465 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3468 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3471 *out_ptr
= map
->ptr
;
3472 *out_stride
= map
->stride
;
3474 if (map
->ptr
== NULL
)
3475 intel_miptree_release_map(mt
, level
, slice
);
3479 intel_miptree_unmap(struct brw_context
*brw
,
3480 struct intel_mipmap_tree
*mt
,
3484 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3486 assert(mt
->num_samples
<= 1);
3491 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3492 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3494 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3495 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3496 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3497 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3498 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3499 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3500 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3501 } else if (map
->linear_mt
) {
3502 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3503 #if defined(USE_SSE41)
3504 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3505 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3508 intel_miptree_unmap_gtt(mt
);
3511 intel_miptree_release_map(mt
, level
, slice
);
3515 get_isl_surf_dim(GLenum target
)
3519 case GL_TEXTURE_1D_ARRAY
:
3520 return ISL_SURF_DIM_1D
;
3523 case GL_TEXTURE_2D_ARRAY
:
3524 case GL_TEXTURE_RECTANGLE
:
3525 case GL_TEXTURE_CUBE_MAP
:
3526 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3527 case GL_TEXTURE_2D_MULTISAMPLE
:
3528 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3529 case GL_TEXTURE_EXTERNAL_OES
:
3530 return ISL_SURF_DIM_2D
;
3533 return ISL_SURF_DIM_3D
;
3536 unreachable("Invalid texture target");
3540 get_isl_dim_layout(const struct gen_device_info
*devinfo
, uint32_t tiling
,
3541 GLenum target
, enum miptree_array_layout array_layout
)
3543 if (array_layout
== GEN6_HIZ_STENCIL
)
3544 return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
;
3548 case GL_TEXTURE_1D_ARRAY
:
3549 return (devinfo
->gen
>= 9 && tiling
== I915_TILING_NONE
?
3550 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3553 case GL_TEXTURE_2D_ARRAY
:
3554 case GL_TEXTURE_RECTANGLE
:
3555 case GL_TEXTURE_2D_MULTISAMPLE
:
3556 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3557 case GL_TEXTURE_EXTERNAL_OES
:
3558 return ISL_DIM_LAYOUT_GEN4_2D
;
3560 case GL_TEXTURE_CUBE_MAP
:
3561 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3562 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3563 ISL_DIM_LAYOUT_GEN4_2D
);
3566 return (devinfo
->gen
>= 9 ?
3567 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3570 unreachable("Invalid texture target");
3574 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree
*mt
)
3576 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3577 return ISL_TILING_W
;
3579 switch (mt
->tiling
) {
3580 case I915_TILING_NONE
:
3581 return ISL_TILING_LINEAR
;
3583 return ISL_TILING_X
;
3585 return ISL_TILING_Y0
;
3587 unreachable("Invalid tiling mode");
3593 intel_miptree_get_isl_surf(struct brw_context
*brw
,
3594 const struct intel_mipmap_tree
*mt
,
3595 struct isl_surf
*surf
)
3597 surf
->dim
= get_isl_surf_dim(mt
->target
);
3598 surf
->dim_layout
= get_isl_dim_layout(&brw
->screen
->devinfo
,
3599 mt
->tiling
, mt
->target
,
3602 if (mt
->num_samples
> 1) {
3603 switch (mt
->msaa_layout
) {
3604 case INTEL_MSAA_LAYOUT_IMS
:
3605 surf
->msaa_layout
= ISL_MSAA_LAYOUT_INTERLEAVED
;
3607 case INTEL_MSAA_LAYOUT_UMS
:
3608 case INTEL_MSAA_LAYOUT_CMS
:
3609 surf
->msaa_layout
= ISL_MSAA_LAYOUT_ARRAY
;
3612 unreachable("Invalid MSAA layout");
3615 surf
->msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
3618 surf
->tiling
= intel_miptree_get_isl_tiling(mt
);
3620 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3621 /* The ISL definition of row_pitch matches the surface state pitch field
3622 * a bit better than intel_mipmap_tree. In particular, ISL incorporates
3623 * the factor of 2 for W-tiling in row_pitch.
3625 surf
->row_pitch
= 2 * mt
->pitch
;
3627 surf
->row_pitch
= mt
->pitch
;
3630 surf
->format
= translate_tex_format(brw
, mt
->format
, false);
3632 if (brw
->gen
>= 9) {
3633 if (surf
->dim
== ISL_SURF_DIM_1D
&& surf
->tiling
== ISL_TILING_LINEAR
) {
3634 /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
3635 surf
->image_alignment_el
= isl_extent3d(64, 1, 1);
3637 /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
3638 * alignment in terms of surface elements like we want.
3640 surf
->image_alignment_el
= isl_extent3d(mt
->halign
, mt
->valign
, 1);
3643 /* On earlier gens it's stored in pixels. */
3645 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3646 surf
->image_alignment_el
=
3647 isl_extent3d(mt
->halign
/ bw
, mt
->valign
/ bh
, 1);
3650 surf
->logical_level0_px
.width
= mt
->logical_width0
;
3651 surf
->logical_level0_px
.height
= mt
->logical_height0
;
3652 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3653 surf
->logical_level0_px
.depth
= mt
->logical_depth0
;
3654 surf
->logical_level0_px
.array_len
= 1;
3656 surf
->logical_level0_px
.depth
= 1;
3657 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
;
3660 surf
->phys_level0_sa
.width
= mt
->physical_width0
;
3661 surf
->phys_level0_sa
.height
= mt
->physical_height0
;
3662 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3663 surf
->phys_level0_sa
.depth
= mt
->physical_depth0
;
3664 surf
->phys_level0_sa
.array_len
= 1;
3666 surf
->phys_level0_sa
.depth
= 1;
3667 surf
->phys_level0_sa
.array_len
= mt
->physical_depth0
;
3670 surf
->levels
= mt
->last_level
- mt
->first_level
+ 1;
3671 surf
->samples
= MAX2(mt
->num_samples
, 1);
3673 surf
->size
= 0; /* TODO */
3674 surf
->alignment
= 0; /* TODO */
3676 switch (surf
->dim_layout
) {
3677 case ISL_DIM_LAYOUT_GEN4_2D
:
3678 case ISL_DIM_LAYOUT_GEN4_3D
:
3679 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
3680 if (brw
->gen
>= 9) {
3681 surf
->array_pitch_el_rows
= mt
->qpitch
;
3684 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3685 assert(mt
->qpitch
% bh
== 0);
3686 surf
->array_pitch_el_rows
= mt
->qpitch
/ bh
;
3689 case ISL_DIM_LAYOUT_GEN9_1D
:
3690 surf
->array_pitch_el_rows
= 1;
3694 switch (mt
->array_layout
) {
3695 case ALL_LOD_IN_EACH_SLICE
:
3696 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_FULL
;
3698 case ALL_SLICES_AT_EACH_LOD
:
3699 case GEN6_HIZ_STENCIL
:
3700 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_COMPACT
;
3703 unreachable("Invalid array layout");
3706 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
3707 switch (base_format
) {
3708 case GL_DEPTH_COMPONENT
:
3709 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
3711 case GL_STENCIL_INDEX
:
3712 surf
->usage
= ISL_SURF_USAGE_STENCIL_BIT
;
3714 surf
->usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
3716 case GL_DEPTH_STENCIL
:
3717 /* In this case we only texture from the depth part */
3718 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
|
3719 ISL_SURF_USAGE_TEXTURE_BIT
;
3722 surf
->usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
3723 if (brw
->format_supported_as_render_target
[mt
->format
])
3724 surf
->usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
3728 if (_mesa_is_cube_map_texture(mt
->target
))
3729 surf
->usage
|= ISL_SURF_USAGE_CUBE_BIT
;
3732 /* WARNING: THE SURFACE CREATED BY THIS FUNCTION IS NOT COMPLETE AND CANNOT BE
3733 * USED FOR ANY REAL CALCULATIONS. THE ONLY VALID USE OF SUCH A SURFACE IS TO
3734 * PASS IT INTO isl_surf_fill_state.
3737 intel_miptree_get_aux_isl_surf(struct brw_context
*brw
,
3738 const struct intel_mipmap_tree
*mt
,
3739 struct isl_surf
*surf
,
3740 enum isl_aux_usage
*usage
)
3742 uint32_t aux_pitch
, aux_qpitch
;
3744 aux_pitch
= mt
->mcs_buf
->pitch
;
3745 aux_qpitch
= mt
->mcs_buf
->qpitch
;
3747 if (mt
->num_samples
> 1) {
3748 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
3749 *usage
= ISL_AUX_USAGE_MCS
;
3750 } else if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
3751 assert(brw
->gen
>= 9);
3752 *usage
= ISL_AUX_USAGE_CCS_E
;
3753 } else if ((mt
->aux_disable
& INTEL_AUX_DISABLE_CCS
) == 0) {
3754 *usage
= ISL_AUX_USAGE_CCS_D
;
3756 unreachable("Invalid MCS miptree");
3758 } else if (mt
->hiz_buf
) {
3759 aux_pitch
= mt
->hiz_buf
->aux_base
.pitch
;
3760 aux_qpitch
= mt
->hiz_buf
->aux_base
.qpitch
;
3762 *usage
= ISL_AUX_USAGE_HIZ
;
3764 *usage
= ISL_AUX_USAGE_NONE
;
3768 /* Start with a copy of the original surface. */
3769 intel_miptree_get_isl_surf(brw
, mt
, surf
);
3771 /* Figure out the format and tiling of the auxiliary surface */
3773 case ISL_AUX_USAGE_NONE
:
3774 unreachable("Invalid auxiliary usage");
3776 case ISL_AUX_USAGE_HIZ
:
3777 isl_surf_get_hiz_surf(&brw
->isl_dev
, surf
, surf
);
3780 case ISL_AUX_USAGE_MCS
:
3783 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
3784 * HALIGN 16 must be used."
3787 assert(mt
->halign
== 16);
3789 isl_surf_get_mcs_surf(&brw
->isl_dev
, surf
, surf
);
3792 case ISL_AUX_USAGE_CCS_D
:
3793 case ISL_AUX_USAGE_CCS_E
:
3795 * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
3797 * "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
3799 * From the hardware spec for GEN9:
3801 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
3802 * HALIGN 16 must be used."
3804 assert(mt
->num_samples
<= 1);
3806 assert(mt
->halign
== 16);
3808 isl_surf_get_ccs_surf(&brw
->isl_dev
, surf
, surf
);
3812 /* We want the pitch of the actual aux buffer. */
3813 surf
->row_pitch
= aux_pitch
;
3815 /* Auxiliary surfaces in ISL have compressed formats and array_pitch_el_rows
3816 * is in elements. This doesn't match intel_mipmap_tree::qpitch which is
3817 * in elements of the primary color surface so we have to divide by the
3818 * compression block height.
3820 surf
->array_pitch_el_rows
=
3821 aux_qpitch
/ isl_format_get_layout(surf
->format
)->bh
;