2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_mipmap_tree.h"
31 #include "intel_resolve_map.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
);
54 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
57 intel_miptree_alloc_mcs(struct brw_context
*brw
,
58 struct intel_mipmap_tree
*mt
,
62 * Determine which MSAA layout should be used by the MSAA surface being
63 * created, based on the chip generation and the surface type.
65 static enum intel_msaa_layout
66 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
67 bool disable_aux_buffers
)
69 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
71 return INTEL_MSAA_LAYOUT_IMS
;
73 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
74 switch (_mesa_get_format_base_format(format
)) {
75 case GL_DEPTH_COMPONENT
:
76 case GL_STENCIL_INDEX
:
77 case GL_DEPTH_STENCIL
:
78 return INTEL_MSAA_LAYOUT_IMS
;
80 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
82 * This field must be set to 0 for all SINT MSRTs when all RT channels
85 * In practice this means that we have to disable MCS for all signed
86 * integer MSAA buffers. The alternative, to disable MCS only when one
87 * of the render target channels is disabled, is impractical because it
88 * would require converting between CMS and UMS MSAA layouts on the fly,
91 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
92 return INTEL_MSAA_LAYOUT_UMS
;
93 } else if (disable_aux_buffers
) {
94 /* We can't use the CMS layout because it uses an aux buffer, the MCS
95 * buffer. So fallback to UMS, which is identical to CMS without the
97 return INTEL_MSAA_LAYOUT_UMS
;
99 return INTEL_MSAA_LAYOUT_CMS
;
106 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
107 * scaled-down bitfield representation of the color buffer which is capable of
108 * recording when blocks of the color buffer are equal to the clear value.
109 * This function returns the block size that will be used by the MCS buffer
110 * corresponding to a certain color miptree.
112 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
113 * beneath the "Fast Color Clear" bullet (p327):
115 * The following table describes the RT alignment
129 * This alignment has the following uses:
131 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
132 * buffer contains 128 blocks horizontally and 256 blocks vertically.
134 * - For figuring out alignment restrictions for a fast clear operation. Fast
135 * clear operations must always clear aligned multiples of 16 blocks
136 * horizontally and 32 blocks vertically.
138 * - For scaling down the coordinates sent through the render pipeline during
139 * a fast clear. X coordinates must be scaled down by 8 times the block
140 * width, and Y coordinates by 16 times the block height.
142 * - For scaling down the coordinates sent through the render pipeline during
143 * a "Render Target Resolve" operation. X coordinates must be scaled down
144 * by half the block width, and Y coordinates by half the block height.
147 intel_get_non_msrt_mcs_alignment(struct intel_mipmap_tree
*mt
,
148 unsigned *width_px
, unsigned *height
)
150 switch (mt
->tiling
) {
152 unreachable("Non-MSRT MCS requires X or Y tiling");
153 /* In release builds, fall through */
155 *width_px
= 32 / mt
->cpp
;
159 *width_px
= 64 / mt
->cpp
;
165 intel_tiling_supports_non_msrt_mcs(struct brw_context
*brw
, unsigned tiling
)
167 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
168 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
170 * - Support is limited to tiled render targets.
172 * Gen9 changes the restriction to Y-tile only.
175 return tiling
== I915_TILING_Y
;
176 else if (brw
->gen
>= 7)
177 return tiling
!= I915_TILING_NONE
;
183 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
184 * can be used. This doesn't (and should not) inspect any of the properties of
187 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
188 * beneath the "Fast Color Clear" bullet (p326):
190 * - Support is for non-mip-mapped and non-array surface types only.
192 * And then later, on p327:
194 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
197 * From the Skylake documentation, it is made clear that X-tiling is no longer
200 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
204 intel_miptree_supports_non_msrt_fast_clear(struct brw_context
*brw
,
205 struct intel_mipmap_tree
*mt
)
207 /* MCS support does not exist prior to Gen7 */
212 /* FINISHME: Enable singlesample fast MCS clears on SKL after all GPU
213 * FINISHME: hangs are resolved.
215 perf_debug("singlesample fast MCS clears disabled on gen9");
219 if (mt
->disable_aux_buffers
)
222 /* This function applies only to non-multisampled render targets. */
223 if (mt
->num_samples
> 1)
226 /* MCS is only supported for color buffers */
227 switch (_mesa_get_format_base_format(mt
->format
)) {
228 case GL_DEPTH_COMPONENT
:
229 case GL_DEPTH_STENCIL
:
230 case GL_STENCIL_INDEX
:
234 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
236 if (mt
->first_level
!= 0 || mt
->last_level
!= 0) {
238 perf_debug("Multi-LOD fast clear - giving up (%dx%dx%d).\n",
239 mt
->logical_width0
, mt
->logical_height0
, mt
->last_level
);
245 /* Check for layered surfaces. */
246 if (mt
->physical_depth0
!= 1) {
247 /* Multisample surfaces with the CMS layout are not layered surfaces,
248 * yet still have physical_depth0 > 1. Assert that we don't
249 * accidentally reject a multisampled surface here. We should have
250 * rejected it earlier by explicitly checking the sample count.
252 assert(mt
->num_samples
<= 1);
255 perf_debug("Layered fast clear - giving up. (%dx%d%d)\n",
256 mt
->logical_width0
, mt
->logical_height0
,
257 mt
->physical_depth0
);
263 /* There's no point in using an MCS buffer if the surface isn't in a
266 if (!brw
->format_supported_as_render_target
[mt
->format
])
270 const uint32_t brw_format
= brw_format_for_mesa_format(mt
->format
);
271 return brw_losslessly_compressible_format(brw
, brw_format
);
278 * Determine depth format corresponding to a depth+stencil format,
279 * for separate stencil.
282 intel_depth_format_for_depthstencil_format(mesa_format format
) {
284 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
285 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
286 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
287 return MESA_FORMAT_Z_FLOAT32
;
295 * @param for_bo Indicates that the caller is
296 * intel_miptree_create_for_bo(). If true, then do not create
299 static struct intel_mipmap_tree
*
300 intel_miptree_create_layout(struct brw_context
*brw
,
309 uint32_t layout_flags
)
311 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
315 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
316 _mesa_enum_to_string(target
),
317 _mesa_get_format_name(format
),
318 first_level
, last_level
, depth0
, mt
);
320 if (target
== GL_TEXTURE_1D_ARRAY
) {
321 /* For a 1D Array texture the OpenGL API will treat the height0
322 * parameter as the number of array slices. For Intel hardware, we treat
323 * the 1D array as a 2D Array with a height of 1.
325 * So, when we first come through this path to create a 1D Array
326 * texture, height0 stores the number of slices, and depth0 is 1. In
327 * this case, we want to swap height0 and depth0.
329 * Since some miptrees will be created based on the base miptree, we may
330 * come through this path and see height0 as 1 and depth0 being the
331 * number of slices. In this case we don't need to do the swap.
333 assert(height0
== 1 || depth0
== 1);
342 mt
->first_level
= first_level
;
343 mt
->last_level
= last_level
;
344 mt
->logical_width0
= width0
;
345 mt
->logical_height0
= height0
;
346 mt
->logical_depth0
= depth0
;
347 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
348 mt
->disable_aux_buffers
= (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) != 0;
349 exec_list_make_empty(&mt
->hiz_map
);
350 mt
->cpp
= _mesa_get_format_bytes(format
);
351 mt
->num_samples
= num_samples
;
352 mt
->compressed
= _mesa_is_format_compressed(format
);
353 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
356 if (num_samples
> 1) {
357 /* Adjust width/height/depth for MSAA */
358 mt
->msaa_layout
= compute_msaa_layout(brw
, format
,
359 mt
->disable_aux_buffers
);
360 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
361 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
362 * "If the surface is multisampled and it is a depth or stencil
363 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
364 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
367 * +----------------------------------------------------------------+
368 * | Num Multisamples | W_l = | H_l = |
369 * +----------------------------------------------------------------+
370 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
371 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
372 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
373 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
374 * +----------------------------------------------------------------+
377 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
378 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
379 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
381 * Another more complicated explanation for these adjustments comes
382 * from the Sandybridge PRM, volume 4, part 1, page 31:
384 * "Any of the other messages (sample*, LOD, load4) used with a
385 * (4x) multisampled surface will in-effect sample a surface with
386 * double the height and width as that indicated in the surface
387 * state. Each pixel position on the original-sized surface is
388 * replaced with a 2x2 of samples with the following arrangement:
393 * Thus, when sampling from a multisampled texture, it behaves as
394 * though the layout in memory for (x,y,sample) is:
396 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
397 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
399 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
400 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
402 * However, the actual layout of multisampled data in memory is:
404 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
405 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
407 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
408 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
410 * This pattern repeats for each 2x2 pixel block.
412 * As a result, when calculating the size of our 4-sample buffer for
413 * an odd width or height, we have to align before scaling up because
414 * sample 3 is in that bottom right 2x2 block.
416 switch (num_samples
) {
418 assert(brw
->gen
>= 8);
419 width0
= ALIGN(width0
, 2) * 2;
420 height0
= ALIGN(height0
, 2);
423 width0
= ALIGN(width0
, 2) * 2;
424 height0
= ALIGN(height0
, 2) * 2;
427 width0
= ALIGN(width0
, 2) * 4;
428 height0
= ALIGN(height0
, 2) * 2;
431 width0
= ALIGN(width0
, 2) * 4;
432 height0
= ALIGN(height0
, 2) * 4;
435 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
438 unreachable("not reached");
441 /* Non-interleaved */
442 depth0
*= num_samples
;
446 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
447 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
448 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
449 * used on Gen8 to make it pick a qpitch value which doesn't include space
450 * for the mipmaps. On Gen9 this is not necessary because it will
451 * automatically pick a packed qpitch value whenever mt->first_level ==
453 * TODO: can we use it elsewhere?
454 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
457 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
459 switch (mt
->msaa_layout
) {
460 case INTEL_MSAA_LAYOUT_NONE
:
461 case INTEL_MSAA_LAYOUT_IMS
:
462 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
464 case INTEL_MSAA_LAYOUT_UMS
:
465 case INTEL_MSAA_LAYOUT_CMS
:
466 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
471 if (target
== GL_TEXTURE_CUBE_MAP
) {
476 mt
->physical_width0
= width0
;
477 mt
->physical_height0
= height0
;
478 mt
->physical_depth0
= depth0
;
480 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
481 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
482 (brw
->must_use_separate_stencil
||
483 (brw
->has_separate_stencil
&&
484 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
485 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
487 stencil_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
|
488 MIPTREE_LAYOUT_TILING_ANY
;
491 mt
->stencil_mt
= intel_miptree_create(brw
,
502 if (!mt
->stencil_mt
) {
503 intel_miptree_release(&mt
);
507 /* Fix up the Z miptree format for how we're splitting out separate
508 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
510 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
513 if (format
== mt
->format
) {
514 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
515 _mesa_get_format_name(mt
->format
));
519 if (layout_flags
& MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
)
520 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
523 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
524 * multisampled or have an AUX buffer attached to it.
526 * GEN | MSRT | AUX_CCS_* or AUX_MCS
527 * -------------------------------------------
528 * 9 | HALIGN_16 | HALIGN_16
529 * 8 | HALIGN_ANY | HALIGN_16
533 if (intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
534 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
535 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
536 } else if (brw
->gen
>= 9 && num_samples
> 1) {
537 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
539 /* For now, nothing else has this requirement */
540 assert((layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
543 brw_miptree_layout(brw
, mt
, layout_flags
);
545 if (mt
->disable_aux_buffers
)
546 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
553 * Choose an appropriate uncompressed format for a requested
554 * compressed format, if unsupported.
557 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
559 /* No need to lower ETC formats on these platforms,
560 * they are supported natively.
562 if (brw
->gen
>= 8 || brw
->is_baytrail
)
566 case MESA_FORMAT_ETC1_RGB8
:
567 return MESA_FORMAT_R8G8B8X8_UNORM
;
568 case MESA_FORMAT_ETC2_RGB8
:
569 return MESA_FORMAT_R8G8B8X8_UNORM
;
570 case MESA_FORMAT_ETC2_SRGB8
:
571 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
572 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
573 return MESA_FORMAT_B8G8R8A8_SRGB
;
574 case MESA_FORMAT_ETC2_RGBA8_EAC
:
575 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
576 return MESA_FORMAT_R8G8B8A8_UNORM
;
577 case MESA_FORMAT_ETC2_R11_EAC
:
578 return MESA_FORMAT_R_UNORM16
;
579 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
580 return MESA_FORMAT_R_SNORM16
;
581 case MESA_FORMAT_ETC2_RG11_EAC
:
582 return MESA_FORMAT_R16G16_UNORM
;
583 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
584 return MESA_FORMAT_R16G16_SNORM
;
586 /* Non ETC1 / ETC2 format */
591 /* This function computes Yf/Ys tiled bo size, alignment and pitch. */
593 intel_get_yf_ys_bo_size(struct intel_mipmap_tree
*mt
, unsigned *alignment
,
594 unsigned long *pitch
)
596 uint32_t tile_width
, tile_height
;
597 unsigned long stride
, size
, aligned_y
;
599 assert(mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
);
600 intel_get_tile_dims(mt
->tiling
, mt
->tr_mode
, mt
->cpp
,
601 &tile_width
, &tile_height
);
603 aligned_y
= ALIGN(mt
->total_height
, tile_height
);
604 stride
= mt
->total_width
* mt
->cpp
;
605 stride
= ALIGN(stride
, tile_width
);
606 size
= stride
* aligned_y
;
608 if (mt
->tr_mode
== INTEL_MIPTREE_TRMODE_YF
) {
609 assert(size
% 4096 == 0);
612 assert(size
% (64 * 1024) == 0);
613 *alignment
= 64 * 1024;
619 struct intel_mipmap_tree
*
620 intel_miptree_create(struct brw_context
*brw
,
629 uint32_t layout_flags
)
631 struct intel_mipmap_tree
*mt
;
632 mesa_format tex_format
= format
;
633 mesa_format etc_format
= MESA_FORMAT_NONE
;
634 GLuint total_width
, total_height
;
635 uint32_t alloc_flags
= 0;
637 format
= intel_lower_compressed_format(brw
, format
);
639 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
641 assert((layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) == 0);
642 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
643 mt
= intel_miptree_create_layout(brw
, target
, format
,
644 first_level
, last_level
, width0
,
645 height0
, depth0
, num_samples
,
648 * pitch == 0 || height == 0 indicates the null texture
650 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
651 intel_miptree_release(&mt
);
655 total_width
= mt
->total_width
;
656 total_height
= mt
->total_height
;
658 if (format
== MESA_FORMAT_S_UINT8
) {
659 /* Align to size of W tile, 64x64. */
660 total_width
= ALIGN(total_width
, 64);
661 total_height
= ALIGN(total_height
, 64);
666 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
)) {
668 mt
->tiling
= I915_TILING_Y
;
671 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
672 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
675 mt
->etc_format
= etc_format
;
677 if (mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) {
678 unsigned alignment
= 0;
680 size
= intel_get_yf_ys_bo_size(mt
, &alignment
, &pitch
);
682 mt
->bo
= drm_intel_bo_alloc_for_render(brw
->bufmgr
, "miptree",
685 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
686 total_width
, total_height
, mt
->cpp
,
693 /* If the BO is too large to fit in the aperture, we need to use the
694 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
695 * handle Y-tiling, so we need to fall back to X.
697 if (brw
->gen
< 6 && y_or_x
&& mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
698 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
699 mt
->total_width
, mt
->total_height
);
701 mt
->tiling
= I915_TILING_X
;
702 drm_intel_bo_unreference(mt
->bo
);
703 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
704 total_width
, total_height
, mt
->cpp
,
705 &mt
->tiling
, &pitch
, alloc_flags
);
712 intel_miptree_release(&mt
);
717 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
718 assert(mt
->num_samples
> 1);
719 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
720 intel_miptree_release(&mt
);
725 /* If this miptree is capable of supporting fast color clears, set
726 * fast_clear_state appropriately to ensure that fast clears will occur.
727 * Allocation of the MCS miptree will be deferred until the first fast
728 * clear actually occurs.
730 if (intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) &&
731 intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
732 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
733 assert(brw
->gen
< 8 || mt
->halign
== 16 || num_samples
<= 1);
739 struct intel_mipmap_tree
*
740 intel_miptree_create_for_bo(struct brw_context
*brw
,
748 uint32_t layout_flags
)
750 struct intel_mipmap_tree
*mt
;
751 uint32_t tiling
, swizzle
;
754 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
756 /* Nothing will be able to use this miptree with the BO if the offset isn't
759 if (tiling
!= I915_TILING_NONE
)
760 assert(offset
% 4096 == 0);
762 /* miptrees can't handle negative pitch. If you need flipping of images,
763 * that's outside of the scope of the mt.
767 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
769 /* The BO already has a tiling format and we shouldn't confuse the lower
770 * layers by making it try to find a tiling format again.
772 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
773 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
775 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
776 mt
= intel_miptree_create_layout(brw
, target
, format
,
778 width
, height
, depth
, 0,
783 drm_intel_bo_reference(bo
);
793 * For a singlesample renderbuffer, this simply wraps the given BO with a
796 * For a multisample renderbuffer, this wraps the window system's
797 * (singlesample) BO with a singlesample miptree attached to the
798 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
799 * that will contain the actual rendering (which is lazily resolved to
800 * irb->singlesample_mt).
803 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
804 struct intel_renderbuffer
*irb
,
806 uint32_t width
, uint32_t height
,
809 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
810 struct intel_mipmap_tree
*multisample_mt
= NULL
;
811 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
812 mesa_format format
= rb
->Format
;
813 int num_samples
= rb
->NumSamples
;
815 /* Only the front and back buffers, which are color buffers, are allocated
816 * through the image loader.
818 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
819 _mesa_get_format_base_format(format
) == GL_RGBA
);
821 singlesample_mt
= intel_miptree_create_for_bo(intel
,
830 if (!singlesample_mt
)
833 /* If this miptree is capable of supporting fast color clears, set
834 * mcs_state appropriately to ensure that fast clears will occur.
835 * Allocation of the MCS miptree will be deferred until the first fast
836 * clear actually occurs.
838 if (intel_tiling_supports_non_msrt_mcs(intel
, singlesample_mt
->tiling
) &&
839 intel_miptree_supports_non_msrt_fast_clear(intel
, singlesample_mt
)) {
840 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
843 if (num_samples
== 0) {
844 intel_miptree_release(&irb
->mt
);
845 irb
->mt
= singlesample_mt
;
847 assert(!irb
->singlesample_mt
);
849 intel_miptree_release(&irb
->singlesample_mt
);
850 irb
->singlesample_mt
= singlesample_mt
;
853 irb
->mt
->logical_width0
!= width
||
854 irb
->mt
->logical_height0
!= height
) {
855 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
863 irb
->need_downsample
= false;
864 intel_miptree_release(&irb
->mt
);
865 irb
->mt
= multisample_mt
;
871 intel_miptree_release(&irb
->singlesample_mt
);
872 intel_miptree_release(&irb
->mt
);
876 struct intel_mipmap_tree
*
877 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
881 uint32_t num_samples
)
883 struct intel_mipmap_tree
*mt
;
886 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
887 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
888 MIPTREE_LAYOUT_TILING_ANY
;
891 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
892 width
, height
, depth
, num_samples
,
897 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
898 ok
= intel_miptree_alloc_hiz(brw
, mt
);
906 intel_miptree_release(&mt
);
911 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
912 struct intel_mipmap_tree
*src
)
917 intel_miptree_release(dst
);
921 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
929 intel_miptree_release(struct intel_mipmap_tree
**mt
)
934 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
935 if (--(*mt
)->refcount
<= 0) {
938 DBG("%s deleting %p\n", __func__
, *mt
);
940 drm_intel_bo_unreference((*mt
)->bo
);
941 intel_miptree_release(&(*mt
)->stencil_mt
);
942 if ((*mt
)->hiz_buf
) {
943 if ((*mt
)->hiz_buf
->mt
)
944 intel_miptree_release(&(*mt
)->hiz_buf
->mt
);
946 drm_intel_bo_unreference((*mt
)->hiz_buf
->bo
);
947 free((*mt
)->hiz_buf
);
949 intel_miptree_release(&(*mt
)->mcs_mt
);
950 intel_resolve_map_clear(&(*mt
)->hiz_map
);
952 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
953 free((*mt
)->level
[i
].slice
);
963 intel_get_image_dims(struct gl_texture_image
*image
,
964 int *width
, int *height
, int *depth
)
966 switch (image
->TexObject
->Target
) {
967 case GL_TEXTURE_1D_ARRAY
:
968 /* For a 1D Array texture the OpenGL API will treat the image height as
969 * the number of array slices. For Intel hardware, we treat the 1D array
970 * as a 2D Array with a height of 1. So, here we want to swap image
973 *width
= image
->Width
;
975 *depth
= image
->Height
;
978 *width
= image
->Width
;
979 *height
= image
->Height
;
980 *depth
= image
->Depth
;
986 * Can the image be pulled into a unified mipmap tree? This mirrors
987 * the completeness test in a lot of ways.
989 * Not sure whether I want to pass gl_texture_image here.
992 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
993 struct gl_texture_image
*image
)
995 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
996 GLuint level
= intelImage
->base
.Base
.Level
;
997 int width
, height
, depth
;
999 /* glTexImage* choose the texture object based on the target passed in, and
1000 * objects can't change targets over their lifetimes, so this should be
1003 assert(image
->TexObject
->Target
== mt
->target
);
1005 mesa_format mt_format
= mt
->format
;
1006 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1007 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1008 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1009 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1010 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1011 mt_format
= mt
->etc_format
;
1013 if (image
->TexFormat
!= mt_format
)
1016 intel_get_image_dims(image
, &width
, &height
, &depth
);
1018 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1021 int level_depth
= mt
->level
[level
].depth
;
1022 if (mt
->num_samples
> 1) {
1023 switch (mt
->msaa_layout
) {
1024 case INTEL_MSAA_LAYOUT_NONE
:
1025 case INTEL_MSAA_LAYOUT_IMS
:
1027 case INTEL_MSAA_LAYOUT_UMS
:
1028 case INTEL_MSAA_LAYOUT_CMS
:
1029 level_depth
/= mt
->num_samples
;
1034 /* Test image dimensions against the base level image adjusted for
1035 * minification. This will also catch images not present in the
1036 * tree, changed targets, etc.
1038 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1039 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1040 depth
!= level_depth
) {
1044 if (image
->NumSamples
!= mt
->num_samples
)
1052 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1054 GLuint x
, GLuint y
, GLuint d
)
1056 mt
->level
[level
].depth
= d
;
1057 mt
->level
[level
].level_x
= x
;
1058 mt
->level
[level
].level_y
= y
;
1060 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1063 assert(mt
->level
[level
].slice
== NULL
);
1065 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
1066 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1067 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1072 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1073 GLuint level
, GLuint img
,
1076 if (img
== 0 && level
== 0)
1077 assert(x
== 0 && y
== 0);
1079 assert(img
< mt
->level
[level
].depth
);
1081 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1082 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1084 DBG("%s level %d img %d pos %d,%d\n",
1085 __func__
, level
, img
,
1086 mt
->level
[level
].slice
[img
].x_offset
,
1087 mt
->level
[level
].slice
[img
].y_offset
);
1091 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1092 GLuint level
, GLuint slice
,
1093 GLuint
*x
, GLuint
*y
)
1095 assert(slice
< mt
->level
[level
].depth
);
1097 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1098 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1103 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1104 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1105 * and tile_h is set to 1.
1108 intel_get_tile_dims(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1109 uint32_t *tile_w
, uint32_t *tile_h
)
1111 if (tr_mode
== INTEL_MIPTREE_TRMODE_NONE
) {
1121 case I915_TILING_NONE
:
1126 unreachable("not reached");
1129 uint32_t aspect_ratio
= 1;
1130 assert(_mesa_is_pow_two(cpp
));
1145 unreachable("not reached");
1148 if (cpp
== 2 || cpp
== 8)
1151 if (tr_mode
== INTEL_MIPTREE_TRMODE_YS
)
1154 *tile_w
= *tile_h
* aspect_ratio
* cpp
;
1160 * This function computes masks that may be used to select the bits of the X
1161 * and Y coordinates that indicate the offset within a tile. If the BO is
1162 * untiled, the masks are set to 0.
1165 intel_get_tile_masks(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1166 bool map_stencil_as_y_tiled
,
1167 uint32_t *mask_x
, uint32_t *mask_y
)
1169 uint32_t tile_w_bytes
, tile_h
;
1170 if (map_stencil_as_y_tiled
)
1171 tiling
= I915_TILING_Y
;
1173 intel_get_tile_dims(tiling
, tr_mode
, cpp
, &tile_w_bytes
, &tile_h
);
1175 *mask_x
= tile_w_bytes
/ cpp
- 1;
1176 *mask_y
= tile_h
- 1;
1180 * Compute the offset (in bytes) from the start of the BO to the given x
1181 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1182 * multiples of the tile size.
1185 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1186 uint32_t x
, uint32_t y
,
1187 bool map_stencil_as_y_tiled
)
1190 uint32_t pitch
= mt
->pitch
;
1191 uint32_t tiling
= mt
->tiling
;
1193 if (map_stencil_as_y_tiled
) {
1194 tiling
= I915_TILING_Y
;
1196 /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
1197 * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
1198 * the resulting surface is twice the pitch of the original miptree,
1199 * since each row in the Y-tiled view corresponds to two rows in the
1200 * actual W-tiled surface. So we need to correct the pitch before
1201 * computing the offsets.
1208 unreachable("not reached");
1209 case I915_TILING_NONE
:
1210 return y
* pitch
+ x
* cpp
;
1212 assert((x
% (512 / cpp
)) == 0);
1213 assert((y
% 8) == 0);
1214 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1216 assert((x
% (128 / cpp
)) == 0);
1217 assert((y
% 32) == 0);
1218 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1223 * Rendering with tiled buffers requires that the base address of the buffer
1224 * be aligned to a page boundary. For renderbuffers, and sometimes with
1225 * textures, we may want the surface to point at a texture image level that
1226 * isn't at a page boundary.
1228 * This function returns an appropriately-aligned base offset
1229 * according to the tiling restrictions, plus any required x/y offset
1233 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1234 GLuint level
, GLuint slice
,
1239 uint32_t mask_x
, mask_y
;
1241 intel_get_tile_masks(mt
->tiling
, mt
->tr_mode
, mt
->cpp
, false, &mask_x
, &mask_y
);
1242 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1244 *tile_x
= x
& mask_x
;
1245 *tile_y
= y
& mask_y
;
1247 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
, false);
1251 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1252 struct intel_mipmap_tree
*dst_mt
,
1253 struct intel_mipmap_tree
*src_mt
,
1260 ptrdiff_t src_stride
, dst_stride
;
1261 int cpp
= dst_mt
->cpp
;
1263 intel_miptree_map(brw
, src_mt
,
1267 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1270 intel_miptree_map(brw
, dst_mt
,
1274 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1278 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1279 _mesa_get_format_name(src_mt
->format
),
1280 src_mt
, src
, src_stride
,
1281 _mesa_get_format_name(dst_mt
->format
),
1282 dst_mt
, dst
, dst_stride
,
1285 int row_size
= cpp
* width
;
1286 if (src_stride
== row_size
&&
1287 dst_stride
== row_size
) {
1288 memcpy(dst
, src
, row_size
* height
);
1290 for (int i
= 0; i
< height
; i
++) {
1291 memcpy(dst
, src
, row_size
);
1297 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1298 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1300 /* Don't forget to copy the stencil data over, too. We could have skipped
1301 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1302 * shuffling the two data sources in/out of temporary storage instead of
1303 * the direct mapping we get this way.
1305 if (dst_mt
->stencil_mt
) {
1306 assert(src_mt
->stencil_mt
);
1307 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1308 level
, slice
, width
, height
);
1313 intel_miptree_copy_slice(struct brw_context
*brw
,
1314 struct intel_mipmap_tree
*dst_mt
,
1315 struct intel_mipmap_tree
*src_mt
,
1321 mesa_format format
= src_mt
->format
;
1322 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1323 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1331 assert(depth
< src_mt
->level
[level
].depth
);
1332 assert(src_mt
->format
== dst_mt
->format
);
1334 if (dst_mt
->compressed
) {
1336 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1337 height
= ALIGN_NPOT(height
, j
) / j
;
1338 width
= ALIGN_NPOT(width
, i
) / i
;
1341 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1342 * below won't apply since we can't do the depth's Y tiling or the
1343 * stencil's W tiling in the blitter.
1345 if (src_mt
->stencil_mt
) {
1346 intel_miptree_copy_slice_sw(brw
,
1353 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1354 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1355 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1357 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1358 _mesa_get_format_name(src_mt
->format
),
1359 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1360 _mesa_get_format_name(dst_mt
->format
),
1361 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1364 if (!intel_miptree_blit(brw
,
1365 src_mt
, level
, slice
, 0, 0, false,
1366 dst_mt
, level
, slice
, 0, 0, false,
1367 width
, height
, GL_COPY
)) {
1368 perf_debug("miptree validate blit for %s failed\n",
1369 _mesa_get_format_name(format
));
1371 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1377 * Copies the image's current data to the given miptree, and associates that
1378 * miptree with the image.
1380 * If \c invalidate is true, then the actual image data does not need to be
1381 * copied, but the image still needs to be associated to the new miptree (this
1382 * is set to true if we're about to clear the image).
1385 intel_miptree_copy_teximage(struct brw_context
*brw
,
1386 struct intel_texture_image
*intelImage
,
1387 struct intel_mipmap_tree
*dst_mt
,
1390 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1391 struct intel_texture_object
*intel_obj
=
1392 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1393 int level
= intelImage
->base
.Base
.Level
;
1394 int face
= intelImage
->base
.Base
.Face
;
1397 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
)
1398 depth
= intelImage
->base
.Base
.Height
;
1400 depth
= intelImage
->base
.Base
.Depth
;
1403 for (int slice
= 0; slice
< depth
; slice
++) {
1404 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1408 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1409 intel_obj
->needs_validate
= true;
1413 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1414 struct intel_mipmap_tree
*mt
,
1417 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1418 assert(mt
->mcs_mt
== NULL
);
1419 assert(!mt
->disable_aux_buffers
);
1421 /* Choose the correct format for the MCS buffer. All that really matters
1422 * is that we allocate the right buffer size, since we'll always be
1423 * accessing this miptree using MCS-specific hardware mechanisms, which
1424 * infer the correct format based on num_samples.
1427 switch (num_samples
) {
1430 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1433 format
= MESA_FORMAT_R_UNORM8
;
1436 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1437 * for each sample, plus 8 padding bits).
1439 format
= MESA_FORMAT_R_UINT32
;
1442 /* 64 bits/pixel are required for MCS data when using 16x MSAA (4 bits
1445 format
= MESA_FORMAT_RG_UINT32
;
1448 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1451 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1453 * "The MCS surface must be stored as Tile Y."
1455 const uint32_t mcs_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1456 MIPTREE_LAYOUT_TILING_Y
;
1457 mt
->mcs_mt
= intel_miptree_create(brw
,
1463 mt
->logical_height0
,
1465 0 /* num_samples */,
1468 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1470 * When MCS buffer is enabled and bound to MSRT, it is required that it
1471 * is cleared prior to any rendering.
1473 * Since we don't use the MCS buffer for any purpose other than rendering,
1474 * it makes sense to just clear it immediately upon allocation.
1476 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1478 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1479 memset(data
, 0xff, mt
->mcs_mt
->total_height
* mt
->mcs_mt
->pitch
);
1480 intel_miptree_unmap_raw(mt
->mcs_mt
);
1481 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1488 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1489 struct intel_mipmap_tree
*mt
)
1491 assert(mt
->mcs_mt
== NULL
);
1492 assert(!mt
->disable_aux_buffers
);
1494 /* The format of the MCS buffer is opaque to the driver; all that matters
1495 * is that we get its size and pitch right. We'll pretend that the format
1496 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1497 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1498 * the block width and then a further factor of 4. Since an MCS tile
1499 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1500 * we'll need to scale the height down by the block height and then a
1501 * further factor of 8.
1503 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1504 unsigned block_width_px
;
1505 unsigned block_height
;
1506 intel_get_non_msrt_mcs_alignment(mt
, &block_width_px
, &block_height
);
1507 unsigned width_divisor
= block_width_px
* 4;
1508 unsigned height_divisor
= block_height
* 8;
1510 /* The Skylake MCS is twice as tall as the Broadwell MCS.
1512 * In pre-Skylake, each bit in the MCS contained the state of 2 cachelines
1513 * in the main surface. In Skylake, it's two bits. The extra bit
1514 * doubles the MCS height, not width, because in Skylake the MCS is always
1518 height_divisor
/= 2;
1520 unsigned mcs_width
=
1521 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1522 unsigned mcs_height
=
1523 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1524 assert(mt
->logical_depth0
== 1);
1525 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1526 MIPTREE_LAYOUT_TILING_Y
;
1527 if (brw
->gen
>= 8) {
1528 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
1530 mt
->mcs_mt
= intel_miptree_create(brw
,
1538 0 /* num_samples */,
1546 * Helper for intel_miptree_alloc_hiz() that sets
1547 * \c mt->level[level].has_hiz. Return true if and only if
1548 * \c has_hiz was set.
1551 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1552 struct intel_mipmap_tree
*mt
,
1555 assert(mt
->hiz_buf
);
1557 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1558 uint32_t width
= minify(mt
->physical_width0
, level
);
1559 uint32_t height
= minify(mt
->physical_height0
, level
);
1561 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1562 * and the height is 4 aligned. This allows our HiZ support
1563 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1564 * we can grow the width & height to allow the HiZ op to
1565 * force the proper size alignments.
1567 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1568 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1573 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1574 mt
->level
[level
].has_hiz
= true;
1580 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1581 * buffer dimensions and allocates a bo for the hiz buffer.
1583 static struct intel_miptree_aux_buffer
*
1584 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1585 struct intel_mipmap_tree
*mt
)
1587 unsigned z_width
= mt
->logical_width0
;
1588 unsigned z_height
= mt
->logical_height0
;
1589 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1590 unsigned hz_width
, hz_height
;
1591 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1596 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1597 * adjustments required for Z_Height and Z_Width based on multisampling.
1599 switch (mt
->num_samples
) {
1613 unreachable("unsupported sample count");
1616 const unsigned vertical_align
= 8; /* 'j' in the docs */
1617 const unsigned H0
= z_height
;
1618 const unsigned h0
= ALIGN(H0
, vertical_align
);
1619 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1620 const unsigned Z0
= z_depth
;
1622 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1623 hz_width
= ALIGN(z_width
, 16);
1625 if (mt
->target
== GL_TEXTURE_3D
) {
1629 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1630 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1631 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1632 hz_height
+= h_i
* Z_i
;
1633 H_i
= minify(H_i
, 1);
1634 Z_i
= minify(Z_i
, 1);
1637 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1639 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1641 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1642 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1643 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1644 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth * 6/2) /8 ) * 8 */
1645 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
* 6, 2 * 8) * 8;
1647 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1648 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1652 unsigned long pitch
;
1653 uint32_t tiling
= I915_TILING_Y
;
1654 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1655 hz_width
, hz_height
, 1,
1657 BO_ALLOC_FOR_RENDER
);
1661 } else if (tiling
!= I915_TILING_Y
) {
1662 drm_intel_bo_unreference(buf
->bo
);
1674 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1675 * buffer dimensions and allocates a bo for the hiz buffer.
1677 static struct intel_miptree_aux_buffer
*
1678 intel_gen8_hiz_buf_create(struct brw_context
*brw
,
1679 struct intel_mipmap_tree
*mt
)
1681 unsigned z_width
= mt
->logical_width0
;
1682 unsigned z_height
= mt
->logical_height0
;
1683 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1684 unsigned hz_width
, hz_height
;
1685 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1690 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1691 * adjustments required for Z_Height and Z_Width based on multisampling.
1694 switch (mt
->num_samples
) {
1708 unreachable("unsupported sample count");
1712 const unsigned vertical_align
= 8; /* 'j' in the docs */
1713 const unsigned H0
= z_height
;
1714 const unsigned h0
= ALIGN(H0
, vertical_align
);
1715 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1716 const unsigned Z0
= z_depth
;
1718 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1719 hz_width
= ALIGN(z_width
, 16);
1723 unsigned sum_h_i
= 0;
1724 unsigned hz_height_3d_sum
= 0;
1725 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1726 unsigned i
= level
- mt
->first_level
;
1727 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1728 /* sum(i=2 to m; h_i) */
1732 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1733 hz_height_3d_sum
+= h_i
* Z_i
;
1734 H_i
= minify(H_i
, 1);
1735 Z_i
= minify(Z_i
, 1);
1737 /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
1738 buf
->qpitch
= h0
+ MAX2(h1
, sum_h_i
);
1740 if (mt
->target
== GL_TEXTURE_3D
) {
1741 /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1742 hz_height
= DIV_ROUND_UP(hz_height_3d_sum
, 2);
1744 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
1745 hz_height
= DIV_ROUND_UP(buf
->qpitch
, 2 * 8) * 8 * Z0
;
1746 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1747 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1748 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * 6 * Z_Depth
1750 * We can can just take our hz_height calculation from above, and
1751 * multiply by 6 for the cube map and cube map array types.
1757 unsigned long pitch
;
1758 uint32_t tiling
= I915_TILING_Y
;
1759 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1760 hz_width
, hz_height
, 1,
1762 BO_ALLOC_FOR_RENDER
);
1766 } else if (tiling
!= I915_TILING_Y
) {
1767 drm_intel_bo_unreference(buf
->bo
);
1778 static struct intel_miptree_aux_buffer
*
1779 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
1780 struct intel_mipmap_tree
*mt
)
1782 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1783 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1786 layout_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
;
1791 layout_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
1792 buf
->mt
= intel_miptree_create(brw
,
1798 mt
->logical_height0
,
1807 buf
->bo
= buf
->mt
->bo
;
1808 buf
->pitch
= buf
->mt
->pitch
;
1809 buf
->qpitch
= buf
->mt
->qpitch
;
1815 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
1816 struct intel_mipmap_tree
*mt
)
1821 if (mt
->hiz_buf
!= NULL
)
1824 if (mt
->disable_aux_buffers
)
1827 switch (mt
->format
) {
1828 case MESA_FORMAT_Z_FLOAT32
:
1829 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
1830 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
1831 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
1832 case MESA_FORMAT_Z_UNORM16
:
1840 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1841 struct intel_mipmap_tree
*mt
)
1843 assert(mt
->hiz_buf
== NULL
);
1844 assert(!mt
->disable_aux_buffers
);
1846 if (brw
->gen
== 7) {
1847 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
1848 } else if (brw
->gen
>= 8) {
1849 mt
->hiz_buf
= intel_gen8_hiz_buf_create(brw
, mt
);
1851 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
1857 /* Mark that all slices need a HiZ resolve. */
1858 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1859 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
1862 for (unsigned layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1863 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
1864 exec_node_init(&m
->link
);
1867 m
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1869 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
1877 * Does the miptree slice have hiz enabled?
1880 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
1882 intel_miptree_check_level_layer(mt
, level
, 0);
1883 return mt
->level
[level
].has_hiz
;
1887 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1891 if (!intel_miptree_level_has_hiz(mt
, level
))
1894 intel_resolve_map_set(&mt
->hiz_map
,
1895 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1900 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1904 if (!intel_miptree_level_has_hiz(mt
, level
))
1907 intel_resolve_map_set(&mt
->hiz_map
,
1908 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1912 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1916 uint32_t end_layer
= mt
->level
[level
].depth
;
1918 for (layer
= 0; layer
< end_layer
; layer
++) {
1919 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
1924 intel_miptree_slice_resolve(struct brw_context
*brw
,
1925 struct intel_mipmap_tree
*mt
,
1928 enum gen6_hiz_op need
)
1930 intel_miptree_check_level_layer(mt
, level
, layer
);
1932 struct intel_resolve_map
*item
=
1933 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1935 if (!item
|| item
->need
!= need
)
1938 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
1939 intel_resolve_map_remove(item
);
1944 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
1945 struct intel_mipmap_tree
*mt
,
1949 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1950 GEN6_HIZ_OP_HIZ_RESOLVE
);
1954 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
1955 struct intel_mipmap_tree
*mt
,
1959 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1960 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1964 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
1965 struct intel_mipmap_tree
*mt
,
1966 enum gen6_hiz_op need
)
1968 bool did_resolve
= false;
1970 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
1971 if (map
->need
!= need
)
1974 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
1975 intel_resolve_map_remove(map
);
1983 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
1984 struct intel_mipmap_tree
*mt
)
1986 return intel_miptree_all_slices_resolve(brw
, mt
,
1987 GEN6_HIZ_OP_HIZ_RESOLVE
);
1991 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
1992 struct intel_mipmap_tree
*mt
)
1994 return intel_miptree_all_slices_resolve(brw
, mt
,
1995 GEN6_HIZ_OP_DEPTH_RESOLVE
);
2000 intel_miptree_resolve_color(struct brw_context
*brw
,
2001 struct intel_mipmap_tree
*mt
)
2003 switch (mt
->fast_clear_state
) {
2004 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
2005 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
2006 /* No resolve needed */
2008 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
2009 case INTEL_FAST_CLEAR_STATE_CLEAR
:
2010 /* Fast color clear resolves only make sense for non-MSAA buffers. */
2011 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
)
2012 brw_meta_resolve_color(brw
, mt
);
2019 * Make it possible to share the BO backing the given miptree with another
2020 * process or another miptree.
2022 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2023 * then discard the MCS buffer, if present. We also set the fast_clear_state
2024 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
2025 * allocated in the future.
2028 intel_miptree_make_shareable(struct brw_context
*brw
,
2029 struct intel_mipmap_tree
*mt
)
2031 /* MCS buffers are also used for multisample buffers, but we can't resolve
2032 * away a multisample MCS buffer because it's an integral part of how the
2033 * pixel data is stored. Fortunately this code path should never be
2034 * reached for multisample buffers.
2036 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
2039 intel_miptree_resolve_color(brw
, mt
);
2040 intel_miptree_release(&mt
->mcs_mt
);
2041 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
2047 * \brief Get pointer offset into stencil buffer.
2049 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2050 * must decode the tile's layout in software.
2053 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2055 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2057 * Even though the returned offset is always positive, the return type is
2059 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2060 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2063 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2065 uint32_t tile_size
= 4096;
2066 uint32_t tile_width
= 64;
2067 uint32_t tile_height
= 64;
2068 uint32_t row_size
= 64 * stride
;
2070 uint32_t tile_x
= x
/ tile_width
;
2071 uint32_t tile_y
= y
/ tile_height
;
2073 /* The byte's address relative to the tile's base addres. */
2074 uint32_t byte_x
= x
% tile_width
;
2075 uint32_t byte_y
= y
% tile_height
;
2077 uintptr_t u
= tile_y
* row_size
2078 + tile_x
* tile_size
2079 + 512 * (byte_x
/ 8)
2081 + 32 * ((byte_y
/ 4) % 2)
2082 + 16 * ((byte_x
/ 4) % 2)
2083 + 8 * ((byte_y
/ 2) % 2)
2084 + 4 * ((byte_x
/ 2) % 2)
2089 /* adjust for bit6 swizzling */
2090 if (((byte_x
/ 8) % 2) == 1) {
2091 if (((byte_y
/ 8) % 2) == 0) {
2103 intel_miptree_updownsample(struct brw_context
*brw
,
2104 struct intel_mipmap_tree
*src
,
2105 struct intel_mipmap_tree
*dst
)
2108 brw_blorp_blit_miptrees(brw
,
2109 src
, 0 /* level */, 0 /* layer */, src
->format
,
2110 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2112 src
->logical_width0
, src
->logical_height0
,
2114 dst
->logical_width0
, dst
->logical_height0
,
2115 GL_NEAREST
, false, false /*mirror x, y*/);
2116 } else if (src
->format
== MESA_FORMAT_S_UINT8
) {
2117 brw_meta_stencil_updownsample(brw
, src
, dst
);
2119 brw_meta_updownsample(brw
, src
, dst
);
2122 if (src
->stencil_mt
) {
2123 if (brw
->gen
>= 8) {
2124 brw_meta_stencil_updownsample(brw
, src
->stencil_mt
, dst
);
2128 brw_blorp_blit_miptrees(brw
,
2129 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2130 src
->stencil_mt
->format
,
2131 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2132 dst
->stencil_mt
->format
,
2134 src
->logical_width0
, src
->logical_height0
,
2136 dst
->logical_width0
, dst
->logical_height0
,
2137 GL_NEAREST
, false, false /*mirror x, y*/);
2142 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
2144 /* CPU accesses to color buffers don't understand fast color clears, so
2145 * resolve any pending fast color clears before we map.
2147 intel_miptree_resolve_color(brw
, mt
);
2149 drm_intel_bo
*bo
= mt
->bo
;
2151 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
2152 intel_batchbuffer_flush(brw
);
2154 if (mt
->tiling
!= I915_TILING_NONE
)
2155 brw_bo_map_gtt(brw
, bo
, "miptree");
2157 brw_bo_map(brw
, bo
, true, "miptree");
2163 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2165 drm_intel_bo_unmap(mt
->bo
);
2169 intel_miptree_map_gtt(struct brw_context
*brw
,
2170 struct intel_mipmap_tree
*mt
,
2171 struct intel_miptree_map
*map
,
2172 unsigned int level
, unsigned int slice
)
2174 unsigned int bw
, bh
;
2176 unsigned int image_x
, image_y
;
2177 intptr_t x
= map
->x
;
2178 intptr_t y
= map
->y
;
2180 /* For compressed formats, the stride is the number of bytes per
2181 * row of blocks. intel_miptree_get_image_offset() already does
2184 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2185 assert(y
% bh
== 0);
2186 assert(x
% bw
== 0);
2190 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
2195 /* Note that in the case of cube maps, the caller must have passed the
2196 * slice number referencing the face.
2198 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2202 map
->stride
= mt
->pitch
;
2203 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2206 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2207 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2208 map
->x
, map
->y
, map
->w
, map
->h
,
2209 mt
, _mesa_get_format_name(mt
->format
),
2210 x
, y
, map
->ptr
, map
->stride
);
2214 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2216 intel_miptree_unmap_raw(mt
);
2220 intel_miptree_map_blit(struct brw_context
*brw
,
2221 struct intel_mipmap_tree
*mt
,
2222 struct intel_miptree_map
*map
,
2223 unsigned int level
, unsigned int slice
)
2225 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2226 /* first_level */ 0,
2230 MIPTREE_LAYOUT_TILING_NONE
);
2232 if (!map
->linear_mt
) {
2233 fprintf(stderr
, "Failed to allocate blit temporary\n");
2236 map
->stride
= map
->linear_mt
->pitch
;
2238 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2239 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2240 * invalidate is set, since we'll be writing the whole rectangle from our
2241 * temporary buffer back out.
2243 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2244 if (!intel_miptree_blit(brw
,
2246 map
->x
, map
->y
, false,
2247 map
->linear_mt
, 0, 0,
2249 map
->w
, map
->h
, GL_COPY
)) {
2250 fprintf(stderr
, "Failed to blit\n");
2255 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
);
2257 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2258 map
->x
, map
->y
, map
->w
, map
->h
,
2259 mt
, _mesa_get_format_name(mt
->format
),
2260 level
, slice
, map
->ptr
, map
->stride
);
2265 intel_miptree_release(&map
->linear_mt
);
2271 intel_miptree_unmap_blit(struct brw_context
*brw
,
2272 struct intel_mipmap_tree
*mt
,
2273 struct intel_miptree_map
*map
,
2277 struct gl_context
*ctx
= &brw
->ctx
;
2279 intel_miptree_unmap_raw(map
->linear_mt
);
2281 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2282 bool ok
= intel_miptree_blit(brw
,
2283 map
->linear_mt
, 0, 0,
2286 map
->x
, map
->y
, false,
2287 map
->w
, map
->h
, GL_COPY
);
2288 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2291 intel_miptree_release(&map
->linear_mt
);
2295 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2297 #if defined(USE_SSE41)
2299 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2300 struct intel_mipmap_tree
*mt
,
2301 struct intel_miptree_map
*map
,
2302 unsigned int level
, unsigned int slice
)
2304 assert(map
->mode
& GL_MAP_READ_BIT
);
2305 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2307 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2308 map
->x
, map
->y
, map
->w
, map
->h
,
2309 mt
, _mesa_get_format_name(mt
->format
),
2310 level
, slice
, map
->ptr
, map
->stride
);
2312 /* Map the original image */
2315 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2319 void *src
= intel_miptree_map_raw(brw
, mt
);
2322 src
+= image_y
* mt
->pitch
;
2323 src
+= image_x
* mt
->cpp
;
2325 /* Due to the pixel offsets for the particular image being mapped, our
2326 * src pointer may not be 16-byte aligned. However, if the pitch is
2327 * divisible by 16, then the amount by which it's misaligned will remain
2328 * consistent from row to row.
2330 assert((mt
->pitch
% 16) == 0);
2331 const int misalignment
= ((uintptr_t) src
) & 15;
2333 /* Create an untiled temporary buffer for the mapping. */
2334 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
2336 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
2338 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
2339 /* Offset the destination so it has the same misalignment as src. */
2340 map
->ptr
= map
->buffer
+ misalignment
;
2342 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
2344 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2345 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
2346 void *src_ptr
= src
+ y
* mt
->pitch
;
2348 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
2351 intel_miptree_unmap_raw(mt
);
2355 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
2356 struct intel_mipmap_tree
*mt
,
2357 struct intel_miptree_map
*map
,
2361 _mesa_align_free(map
->buffer
);
2368 intel_miptree_map_s8(struct brw_context
*brw
,
2369 struct intel_mipmap_tree
*mt
,
2370 struct intel_miptree_map
*map
,
2371 unsigned int level
, unsigned int slice
)
2373 map
->stride
= map
->w
;
2374 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2378 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2379 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2380 * invalidate is set, since we'll be writing the whole rectangle from our
2381 * temporary buffer back out.
2383 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2384 uint8_t *untiled_s8_map
= map
->ptr
;
2385 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2386 unsigned int image_x
, image_y
;
2388 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2390 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2391 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2392 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2393 x
+ image_x
+ map
->x
,
2394 y
+ image_y
+ map
->y
,
2395 brw
->has_swizzling
);
2396 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
2400 intel_miptree_unmap_raw(mt
);
2402 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
2403 map
->x
, map
->y
, map
->w
, map
->h
,
2404 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
2406 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2407 map
->x
, map
->y
, map
->w
, map
->h
,
2408 mt
, map
->ptr
, map
->stride
);
2413 intel_miptree_unmap_s8(struct brw_context
*brw
,
2414 struct intel_mipmap_tree
*mt
,
2415 struct intel_miptree_map
*map
,
2419 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2420 unsigned int image_x
, image_y
;
2421 uint8_t *untiled_s8_map
= map
->ptr
;
2422 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2424 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2426 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2427 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2428 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2431 brw
->has_swizzling
);
2432 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
2436 intel_miptree_unmap_raw(mt
);
2443 intel_miptree_map_etc(struct brw_context
*brw
,
2444 struct intel_mipmap_tree
*mt
,
2445 struct intel_miptree_map
*map
,
2449 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
2450 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
2451 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2454 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2455 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2457 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2458 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2459 map
->w
, map
->h
, 1));
2460 map
->ptr
= map
->buffer
;
2464 intel_miptree_unmap_etc(struct brw_context
*brw
,
2465 struct intel_mipmap_tree
*mt
,
2466 struct intel_miptree_map
*map
,
2472 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2477 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2478 + image_y
* mt
->pitch
2479 + image_x
* mt
->cpp
;
2481 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2482 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2483 map
->ptr
, map
->stride
,
2486 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2487 map
->ptr
, map
->stride
,
2488 map
->w
, map
->h
, mt
->etc_format
);
2490 intel_miptree_unmap_raw(mt
);
2495 * Mapping function for packed depth/stencil miptrees backed by real separate
2496 * miptrees for depth and stencil.
2498 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2499 * separate from the depth buffer. Yet at the GL API level, we have to expose
2500 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2501 * be able to map that memory for texture storage and glReadPixels-type
2502 * operations. We give Mesa core that access by mallocing a temporary and
2503 * copying the data between the actual backing store and the temporary.
2506 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2507 struct intel_mipmap_tree
*mt
,
2508 struct intel_miptree_map
*map
,
2509 unsigned int level
, unsigned int slice
)
2511 struct intel_mipmap_tree
*z_mt
= mt
;
2512 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2513 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2514 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2516 map
->stride
= map
->w
* packed_bpp
;
2517 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2521 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2522 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2523 * invalidate is set, since we'll be writing the whole rectangle from our
2524 * temporary buffer back out.
2526 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2527 uint32_t *packed_map
= map
->ptr
;
2528 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2529 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2530 unsigned int s_image_x
, s_image_y
;
2531 unsigned int z_image_x
, z_image_y
;
2533 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2534 &s_image_x
, &s_image_y
);
2535 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2536 &z_image_x
, &z_image_y
);
2538 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2539 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2540 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2541 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2544 brw
->has_swizzling
);
2545 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2547 (map_x
+ z_image_x
));
2548 uint8_t s
= s_map
[s_offset
];
2549 uint32_t z
= z_map
[z_offset
];
2551 if (map_z32f_x24s8
) {
2552 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2553 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2555 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2560 intel_miptree_unmap_raw(s_mt
);
2561 intel_miptree_unmap_raw(z_mt
);
2563 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2565 map
->x
, map
->y
, map
->w
, map
->h
,
2566 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2567 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2568 map
->ptr
, map
->stride
);
2570 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2571 map
->x
, map
->y
, map
->w
, map
->h
,
2572 mt
, map
->ptr
, map
->stride
);
2577 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2578 struct intel_mipmap_tree
*mt
,
2579 struct intel_miptree_map
*map
,
2583 struct intel_mipmap_tree
*z_mt
= mt
;
2584 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2585 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2587 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2588 uint32_t *packed_map
= map
->ptr
;
2589 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2590 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2591 unsigned int s_image_x
, s_image_y
;
2592 unsigned int z_image_x
, z_image_y
;
2594 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2595 &s_image_x
, &s_image_y
);
2596 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2597 &z_image_x
, &z_image_y
);
2599 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2600 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2601 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2602 x
+ s_image_x
+ map
->x
,
2603 y
+ s_image_y
+ map
->y
,
2604 brw
->has_swizzling
);
2605 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2607 (x
+ z_image_x
+ map
->x
));
2609 if (map_z32f_x24s8
) {
2610 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2611 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2613 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2614 s_map
[s_offset
] = packed
>> 24;
2615 z_map
[z_offset
] = packed
;
2620 intel_miptree_unmap_raw(s_mt
);
2621 intel_miptree_unmap_raw(z_mt
);
2623 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2625 map
->x
, map
->y
, map
->w
, map
->h
,
2626 z_mt
, _mesa_get_format_name(z_mt
->format
),
2627 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2628 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2629 map
->ptr
, map
->stride
);
2636 * Create and attach a map to the miptree at (level, slice). Return the
2639 static struct intel_miptree_map
*
2640 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2649 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2654 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2655 mt
->level
[level
].slice
[slice
].map
= map
;
2667 * Release the map at (level, slice).
2670 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2674 struct intel_miptree_map
**map
;
2676 map
= &mt
->level
[level
].slice
[slice
].map
;
2682 can_blit_slice(struct intel_mipmap_tree
*mt
,
2683 unsigned int level
, unsigned int slice
)
2687 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2688 if (image_x
>= 32768 || image_y
>= 32768)
2691 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2692 if (mt
->pitch
>= 32768)
2699 use_intel_mipree_map_blit(struct brw_context
*brw
,
2700 struct intel_mipmap_tree
*mt
,
2706 /* It's probably not worth swapping to the blit ring because of
2707 * all the overhead involved.
2709 !(mode
& GL_MAP_WRITE_BIT
) &&
2711 (mt
->tiling
== I915_TILING_X
||
2712 /* Prior to Sandybridge, the blitter can't handle Y tiling */
2713 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
)) &&
2714 can_blit_slice(mt
, level
, slice
))
2717 if (mt
->tiling
!= I915_TILING_NONE
&&
2718 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2719 assert(can_blit_slice(mt
, level
, slice
));
2727 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
2728 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
2729 * arithmetic overflow.
2731 * If you call this function and use \a out_stride, then you're doing pointer
2732 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
2733 * bugs. The caller must still take care to avoid 32-bit overflow errors in
2734 * all arithmetic expressions that contain buffer offsets and pixel sizes,
2735 * which usually have type uint32_t or GLuint.
2738 intel_miptree_map(struct brw_context
*brw
,
2739 struct intel_mipmap_tree
*mt
,
2748 ptrdiff_t *out_stride
)
2750 struct intel_miptree_map
*map
;
2752 assert(mt
->num_samples
<= 1);
2754 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2761 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2762 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2763 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2766 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2767 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2768 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2769 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2770 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2771 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2772 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2773 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
2774 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2775 #if defined(USE_SSE41)
2776 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
2777 !mt
->compressed
&& cpu_has_sse4_1
&&
2778 (mt
->pitch
% 16 == 0)) {
2779 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2782 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2785 *out_ptr
= map
->ptr
;
2786 *out_stride
= map
->stride
;
2788 if (map
->ptr
== NULL
)
2789 intel_miptree_release_map(mt
, level
, slice
);
2793 intel_miptree_unmap(struct brw_context
*brw
,
2794 struct intel_mipmap_tree
*mt
,
2798 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2800 assert(mt
->num_samples
<= 1);
2805 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
2806 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2808 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2809 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2810 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2811 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2812 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2813 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2814 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2815 } else if (map
->linear_mt
) {
2816 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2817 #if defined(USE_SSE41)
2818 } else if (map
->buffer
&& cpu_has_sse4_1
) {
2819 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2822 intel_miptree_unmap_gtt(mt
);
2825 intel_miptree_release_map(mt
, level
, slice
);