2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_mipmap_tree.h"
31 #include "intel_resolve_map.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
);
54 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
57 intel_miptree_alloc_mcs(struct brw_context
*brw
,
58 struct intel_mipmap_tree
*mt
,
62 * Determine which MSAA layout should be used by the MSAA surface being
63 * created, based on the chip generation and the surface type.
65 static enum intel_msaa_layout
66 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
67 bool disable_aux_buffers
)
69 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
71 return INTEL_MSAA_LAYOUT_IMS
;
73 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
74 switch (_mesa_get_format_base_format(format
)) {
75 case GL_DEPTH_COMPONENT
:
76 case GL_STENCIL_INDEX
:
77 case GL_DEPTH_STENCIL
:
78 return INTEL_MSAA_LAYOUT_IMS
;
80 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
82 * This field must be set to 0 for all SINT MSRTs when all RT channels
85 * In practice this means that we have to disable MCS for all signed
86 * integer MSAA buffers. The alternative, to disable MCS only when one
87 * of the render target channels is disabled, is impractical because it
88 * would require converting between CMS and UMS MSAA layouts on the fly,
91 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
92 return INTEL_MSAA_LAYOUT_UMS
;
93 } else if (disable_aux_buffers
) {
94 /* We can't use the CMS layout because it uses an aux buffer, the MCS
95 * buffer. So fallback to UMS, which is identical to CMS without the
97 return INTEL_MSAA_LAYOUT_UMS
;
99 return INTEL_MSAA_LAYOUT_CMS
;
106 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
107 * scaled-down bitfield representation of the color buffer which is capable of
108 * recording when blocks of the color buffer are equal to the clear value.
109 * This function returns the block size that will be used by the MCS buffer
110 * corresponding to a certain color miptree.
112 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
113 * beneath the "Fast Color Clear" bullet (p327):
115 * The following table describes the RT alignment
129 * This alignment has the following uses:
131 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
132 * buffer contains 128 blocks horizontally and 256 blocks vertically.
134 * - For figuring out alignment restrictions for a fast clear operation. Fast
135 * clear operations must always clear aligned multiples of 16 blocks
136 * horizontally and 32 blocks vertically.
138 * - For scaling down the coordinates sent through the render pipeline during
139 * a fast clear. X coordinates must be scaled down by 8 times the block
140 * width, and Y coordinates by 16 times the block height.
142 * - For scaling down the coordinates sent through the render pipeline during
143 * a "Render Target Resolve" operation. X coordinates must be scaled down
144 * by half the block width, and Y coordinates by half the block height.
147 intel_get_non_msrt_mcs_alignment(const struct intel_mipmap_tree
*mt
,
148 unsigned *width_px
, unsigned *height
)
150 switch (mt
->tiling
) {
152 unreachable("Non-MSRT MCS requires X or Y tiling");
153 /* In release builds, fall through */
155 *width_px
= 32 / mt
->cpp
;
159 *width_px
= 64 / mt
->cpp
;
165 intel_tiling_supports_non_msrt_mcs(const struct brw_context
*brw
,
168 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
169 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
171 * - Support is limited to tiled render targets.
173 * Gen9 changes the restriction to Y-tile only.
176 return tiling
== I915_TILING_Y
;
177 else if (brw
->gen
>= 7)
178 return tiling
!= I915_TILING_NONE
;
184 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
185 * can be used. This doesn't (and should not) inspect any of the properties of
188 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
189 * beneath the "Fast Color Clear" bullet (p326):
191 * - Support is for non-mip-mapped and non-array surface types only.
193 * And then later, on p327:
195 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
198 * From the Skylake documentation, it is made clear that X-tiling is no longer
201 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
205 intel_miptree_supports_non_msrt_fast_clear(struct brw_context
*brw
,
206 const struct intel_mipmap_tree
*mt
)
208 /* MCS support does not exist prior to Gen7 */
212 if (mt
->disable_aux_buffers
)
215 /* This function applies only to non-multisampled render targets. */
216 if (mt
->num_samples
> 1)
219 /* MCS is only supported for color buffers */
220 switch (_mesa_get_format_base_format(mt
->format
)) {
221 case GL_DEPTH_COMPONENT
:
222 case GL_DEPTH_STENCIL
:
223 case GL_STENCIL_INDEX
:
227 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
229 if (mt
->first_level
!= 0 || mt
->last_level
!= 0) {
231 perf_debug("Multi-LOD fast clear - giving up (%dx%dx%d).\n",
232 mt
->logical_width0
, mt
->logical_height0
, mt
->last_level
);
238 /* Check for layered surfaces. */
239 if (mt
->physical_depth0
!= 1) {
240 /* Multisample surfaces with the CMS layout are not layered surfaces,
241 * yet still have physical_depth0 > 1. Assert that we don't
242 * accidentally reject a multisampled surface here. We should have
243 * rejected it earlier by explicitly checking the sample count.
245 assert(mt
->num_samples
<= 1);
248 perf_debug("Layered fast clear - giving up. (%dx%d%d)\n",
249 mt
->logical_width0
, mt
->logical_height0
,
250 mt
->physical_depth0
);
256 /* There's no point in using an MCS buffer if the surface isn't in a
259 if (!brw
->format_supported_as_render_target
[mt
->format
])
263 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
264 const uint32_t brw_format
= brw_format_for_mesa_format(linear_format
);
265 return brw_losslessly_compressible_format(brw
, brw_format
);
270 /* On Gen9 support for color buffer compression was extended to single
271 * sampled surfaces. This is a helper considering both auxiliary buffer
272 * type and number of samples telling if the given miptree represents
273 * the new single sampled case - also called lossless compression.
276 intel_miptree_is_lossless_compressed(const struct brw_context
*brw
,
277 const struct intel_mipmap_tree
*mt
)
279 /* Only available from Gen9 onwards. */
283 /* Compression always requires auxiliary buffer. */
287 /* Single sample compression is represented re-using msaa compression
288 * layout type: "Compressed Multisampled Surfaces".
290 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
)
293 /* And finally distinguish between msaa and single sample case. */
294 return mt
->num_samples
<= 1;
298 intel_miptree_supports_lossless_compressed(struct brw_context
*brw
,
299 const struct intel_mipmap_tree
*mt
)
301 /* For now compression is only enabled for integer formats even though
302 * there exist supported floating point formats also. This is a heuristic
303 * decision based on current public benchmarks. In none of the cases these
304 * formats provided any improvement but a few cases were seen to regress.
305 * Hence these are left to to be enabled in the future when they are known
308 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
311 /* Fast clear mechanism and lossless compression go hand in hand. */
312 if (!intel_miptree_supports_non_msrt_fast_clear(brw
, mt
))
315 /* Fast clear can be also used to clear srgb surfaces by using equivalent
316 * linear format. This trick, however, can't be extended to be used with
317 * lossless compression and therefore a check is needed to see if the format
320 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
324 * Determine depth format corresponding to a depth+stencil format,
325 * for separate stencil.
328 intel_depth_format_for_depthstencil_format(mesa_format format
) {
330 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
331 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
332 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
333 return MESA_FORMAT_Z_FLOAT32
;
341 * @param for_bo Indicates that the caller is
342 * intel_miptree_create_for_bo(). If true, then do not create
345 static struct intel_mipmap_tree
*
346 intel_miptree_create_layout(struct brw_context
*brw
,
355 uint32_t layout_flags
)
357 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
361 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
362 _mesa_enum_to_string(target
),
363 _mesa_get_format_name(format
),
364 first_level
, last_level
, depth0
, mt
);
366 if (target
== GL_TEXTURE_1D_ARRAY
) {
367 /* For a 1D Array texture the OpenGL API will treat the height0
368 * parameter as the number of array slices. For Intel hardware, we treat
369 * the 1D array as a 2D Array with a height of 1.
371 * So, when we first come through this path to create a 1D Array
372 * texture, height0 stores the number of slices, and depth0 is 1. In
373 * this case, we want to swap height0 and depth0.
375 * Since some miptrees will be created based on the base miptree, we may
376 * come through this path and see height0 as 1 and depth0 being the
377 * number of slices. In this case we don't need to do the swap.
379 assert(height0
== 1 || depth0
== 1);
388 mt
->first_level
= first_level
;
389 mt
->last_level
= last_level
;
390 mt
->logical_width0
= width0
;
391 mt
->logical_height0
= height0
;
392 mt
->logical_depth0
= depth0
;
393 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
394 mt
->disable_aux_buffers
= (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) != 0;
395 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
396 exec_list_make_empty(&mt
->hiz_map
);
397 mt
->cpp
= _mesa_get_format_bytes(format
);
398 mt
->num_samples
= num_samples
;
399 mt
->compressed
= _mesa_is_format_compressed(format
);
400 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
403 if (num_samples
> 1) {
404 /* Adjust width/height/depth for MSAA */
405 mt
->msaa_layout
= compute_msaa_layout(brw
, format
,
406 mt
->disable_aux_buffers
);
407 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
408 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
409 * "If the surface is multisampled and it is a depth or stencil
410 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
411 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
414 * +----------------------------------------------------------------+
415 * | Num Multisamples | W_l = | H_l = |
416 * +----------------------------------------------------------------+
417 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
418 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
419 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
420 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
421 * +----------------------------------------------------------------+
424 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
425 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
426 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
428 * Another more complicated explanation for these adjustments comes
429 * from the Sandybridge PRM, volume 4, part 1, page 31:
431 * "Any of the other messages (sample*, LOD, load4) used with a
432 * (4x) multisampled surface will in-effect sample a surface with
433 * double the height and width as that indicated in the surface
434 * state. Each pixel position on the original-sized surface is
435 * replaced with a 2x2 of samples with the following arrangement:
440 * Thus, when sampling from a multisampled texture, it behaves as
441 * though the layout in memory for (x,y,sample) is:
443 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
444 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
446 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
447 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
449 * However, the actual layout of multisampled data in memory is:
451 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
452 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
454 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
455 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
457 * This pattern repeats for each 2x2 pixel block.
459 * As a result, when calculating the size of our 4-sample buffer for
460 * an odd width or height, we have to align before scaling up because
461 * sample 3 is in that bottom right 2x2 block.
463 switch (num_samples
) {
465 assert(brw
->gen
>= 8);
466 width0
= ALIGN(width0
, 2) * 2;
467 height0
= ALIGN(height0
, 2);
470 width0
= ALIGN(width0
, 2) * 2;
471 height0
= ALIGN(height0
, 2) * 2;
474 width0
= ALIGN(width0
, 2) * 4;
475 height0
= ALIGN(height0
, 2) * 2;
478 width0
= ALIGN(width0
, 2) * 4;
479 height0
= ALIGN(height0
, 2) * 4;
482 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
485 unreachable("not reached");
488 /* Non-interleaved */
489 depth0
*= num_samples
;
493 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
494 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
495 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
496 * used on Gen8 to make it pick a qpitch value which doesn't include space
497 * for the mipmaps. On Gen9 this is not necessary because it will
498 * automatically pick a packed qpitch value whenever mt->first_level ==
500 * TODO: can we use it elsewhere?
501 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
504 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
506 switch (mt
->msaa_layout
) {
507 case INTEL_MSAA_LAYOUT_NONE
:
508 case INTEL_MSAA_LAYOUT_IMS
:
509 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
511 case INTEL_MSAA_LAYOUT_UMS
:
512 case INTEL_MSAA_LAYOUT_CMS
:
513 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
518 if (target
== GL_TEXTURE_CUBE_MAP
) {
523 mt
->physical_width0
= width0
;
524 mt
->physical_height0
= height0
;
525 mt
->physical_depth0
= depth0
;
527 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
528 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
529 (brw
->must_use_separate_stencil
||
530 (brw
->has_separate_stencil
&&
531 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
532 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
534 stencil_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
|
535 MIPTREE_LAYOUT_TILING_ANY
;
538 mt
->stencil_mt
= intel_miptree_create(brw
,
549 if (!mt
->stencil_mt
) {
550 intel_miptree_release(&mt
);
554 /* Fix up the Z miptree format for how we're splitting out separate
555 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
557 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
560 if (format
== mt
->format
) {
561 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
562 _mesa_get_format_name(mt
->format
));
566 if (layout_flags
& MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
)
567 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
570 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
571 * multisampled or have an AUX buffer attached to it.
573 * GEN | MSRT | AUX_CCS_* or AUX_MCS
574 * -------------------------------------------
575 * 9 | HALIGN_16 | HALIGN_16
576 * 8 | HALIGN_ANY | HALIGN_16
580 if (intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
581 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
582 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
583 } else if (brw
->gen
>= 9 && num_samples
> 1) {
584 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
586 const bool is_lossless_compressed_aux
=
587 brw
->gen
>= 9 && num_samples
== 1 &&
588 mt
->format
== MESA_FORMAT_R_UINT32
;
590 /* For now, nothing else has this requirement */
591 assert(is_lossless_compressed_aux
||
592 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
595 brw_miptree_layout(brw
, mt
, layout_flags
);
597 if (mt
->disable_aux_buffers
)
598 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
605 * Choose an appropriate uncompressed format for a requested
606 * compressed format, if unsupported.
609 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
611 /* No need to lower ETC formats on these platforms,
612 * they are supported natively.
614 if (brw
->gen
>= 8 || brw
->is_baytrail
)
618 case MESA_FORMAT_ETC1_RGB8
:
619 return MESA_FORMAT_R8G8B8X8_UNORM
;
620 case MESA_FORMAT_ETC2_RGB8
:
621 return MESA_FORMAT_R8G8B8X8_UNORM
;
622 case MESA_FORMAT_ETC2_SRGB8
:
623 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
624 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
625 return MESA_FORMAT_B8G8R8A8_SRGB
;
626 case MESA_FORMAT_ETC2_RGBA8_EAC
:
627 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
628 return MESA_FORMAT_R8G8B8A8_UNORM
;
629 case MESA_FORMAT_ETC2_R11_EAC
:
630 return MESA_FORMAT_R_UNORM16
;
631 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
632 return MESA_FORMAT_R_SNORM16
;
633 case MESA_FORMAT_ETC2_RG11_EAC
:
634 return MESA_FORMAT_R16G16_UNORM
;
635 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
636 return MESA_FORMAT_R16G16_SNORM
;
638 /* Non ETC1 / ETC2 format */
643 /* This function computes Yf/Ys tiled bo size, alignment and pitch. */
645 intel_get_yf_ys_bo_size(struct intel_mipmap_tree
*mt
, unsigned *alignment
,
646 unsigned long *pitch
)
648 uint32_t tile_width
, tile_height
;
649 unsigned long stride
, size
, aligned_y
;
651 assert(mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
);
652 intel_get_tile_dims(mt
->tiling
, mt
->tr_mode
, mt
->cpp
,
653 &tile_width
, &tile_height
);
655 aligned_y
= ALIGN(mt
->total_height
, tile_height
);
656 stride
= mt
->total_width
* mt
->cpp
;
657 stride
= ALIGN(stride
, tile_width
);
658 size
= stride
* aligned_y
;
660 if (mt
->tr_mode
== INTEL_MIPTREE_TRMODE_YF
) {
661 assert(size
% 4096 == 0);
664 assert(size
% (64 * 1024) == 0);
665 *alignment
= 64 * 1024;
671 static struct intel_mipmap_tree
*
672 miptree_create(struct brw_context
*brw
,
681 uint32_t layout_flags
)
683 struct intel_mipmap_tree
*mt
;
684 mesa_format tex_format
= format
;
685 mesa_format etc_format
= MESA_FORMAT_NONE
;
686 uint32_t alloc_flags
= 0;
688 format
= intel_lower_compressed_format(brw
, format
);
690 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
692 assert((layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) == 0);
693 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
694 mt
= intel_miptree_create_layout(brw
, target
, format
,
695 first_level
, last_level
, width0
,
696 height0
, depth0
, num_samples
,
699 * pitch == 0 || height == 0 indicates the null texture
701 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
702 intel_miptree_release(&mt
);
706 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
))
707 mt
->tiling
= I915_TILING_Y
;
709 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
710 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
713 mt
->etc_format
= etc_format
;
715 if (mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) {
716 unsigned alignment
= 0;
718 size
= intel_get_yf_ys_bo_size(mt
, &alignment
, &pitch
);
720 mt
->bo
= drm_intel_bo_alloc_for_render(brw
->bufmgr
, "miptree",
723 if (format
== MESA_FORMAT_S_UINT8
) {
724 /* Align to size of W tile, 64x64. */
725 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
726 ALIGN(mt
->total_width
, 64),
727 ALIGN(mt
->total_height
, 64),
728 mt
->cpp
, &mt
->tiling
, &pitch
,
731 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
732 mt
->total_width
, mt
->total_height
,
733 mt
->cpp
, &mt
->tiling
, &pitch
,
743 struct intel_mipmap_tree
*
744 intel_miptree_create(struct brw_context
*brw
,
753 uint32_t layout_flags
)
755 struct intel_mipmap_tree
*mt
= miptree_create(
757 first_level
, last_level
,
758 width0
, height0
, depth0
, num_samples
,
761 /* If the BO is too large to fit in the aperture, we need to use the
762 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
763 * handle Y-tiling, so we need to fall back to X.
765 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
766 mt
->tiling
== I915_TILING_Y
) {
767 unsigned long pitch
= mt
->pitch
;
768 const uint32_t alloc_flags
=
769 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
770 BO_ALLOC_FOR_RENDER
: 0;
771 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
772 mt
->total_width
, mt
->total_height
);
774 mt
->tiling
= I915_TILING_X
;
775 drm_intel_bo_unreference(mt
->bo
);
776 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
777 mt
->total_width
, mt
->total_height
, mt
->cpp
,
778 &mt
->tiling
, &pitch
, alloc_flags
);
785 intel_miptree_release(&mt
);
790 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
791 assert(mt
->num_samples
> 1);
792 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
793 intel_miptree_release(&mt
);
798 /* If this miptree is capable of supporting fast color clears, set
799 * fast_clear_state appropriately to ensure that fast clears will occur.
800 * Allocation of the MCS miptree will be deferred until the first fast
801 * clear actually occurs.
803 if (intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) &&
804 intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
805 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
806 assert(brw
->gen
< 8 || mt
->halign
== 16 || num_samples
<= 1);
812 struct intel_mipmap_tree
*
813 intel_miptree_create_for_bo(struct brw_context
*brw
,
821 uint32_t layout_flags
)
823 struct intel_mipmap_tree
*mt
;
824 uint32_t tiling
, swizzle
;
827 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
829 /* Nothing will be able to use this miptree with the BO if the offset isn't
832 if (tiling
!= I915_TILING_NONE
)
833 assert(offset
% 4096 == 0);
835 /* miptrees can't handle negative pitch. If you need flipping of images,
836 * that's outside of the scope of the mt.
840 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
842 /* The BO already has a tiling format and we shouldn't confuse the lower
843 * layers by making it try to find a tiling format again.
845 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
846 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
848 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
849 mt
= intel_miptree_create_layout(brw
, target
, format
,
851 width
, height
, depth
, 0,
856 drm_intel_bo_reference(bo
);
866 * For a singlesample renderbuffer, this simply wraps the given BO with a
869 * For a multisample renderbuffer, this wraps the window system's
870 * (singlesample) BO with a singlesample miptree attached to the
871 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
872 * that will contain the actual rendering (which is lazily resolved to
873 * irb->singlesample_mt).
876 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
877 struct intel_renderbuffer
*irb
,
879 uint32_t width
, uint32_t height
,
882 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
883 struct intel_mipmap_tree
*multisample_mt
= NULL
;
884 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
885 mesa_format format
= rb
->Format
;
886 int num_samples
= rb
->NumSamples
;
888 /* Only the front and back buffers, which are color buffers, are allocated
889 * through the image loader.
891 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
892 _mesa_get_format_base_format(format
) == GL_RGBA
);
894 singlesample_mt
= intel_miptree_create_for_bo(intel
,
902 MIPTREE_LAYOUT_FOR_SCANOUT
);
903 if (!singlesample_mt
)
906 /* If this miptree is capable of supporting fast color clears, set
907 * mcs_state appropriately to ensure that fast clears will occur.
908 * Allocation of the MCS miptree will be deferred until the first fast
909 * clear actually occurs.
911 if (intel_tiling_supports_non_msrt_mcs(intel
, singlesample_mt
->tiling
) &&
912 intel_miptree_supports_non_msrt_fast_clear(intel
, singlesample_mt
)) {
913 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
916 if (num_samples
== 0) {
917 intel_miptree_release(&irb
->mt
);
918 irb
->mt
= singlesample_mt
;
920 assert(!irb
->singlesample_mt
);
922 intel_miptree_release(&irb
->singlesample_mt
);
923 irb
->singlesample_mt
= singlesample_mt
;
926 irb
->mt
->logical_width0
!= width
||
927 irb
->mt
->logical_height0
!= height
) {
928 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
936 irb
->need_downsample
= false;
937 intel_miptree_release(&irb
->mt
);
938 irb
->mt
= multisample_mt
;
944 intel_miptree_release(&irb
->singlesample_mt
);
945 intel_miptree_release(&irb
->mt
);
949 struct intel_mipmap_tree
*
950 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
954 uint32_t num_samples
)
956 struct intel_mipmap_tree
*mt
;
959 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
960 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
961 MIPTREE_LAYOUT_TILING_ANY
|
962 MIPTREE_LAYOUT_FOR_SCANOUT
;
964 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
965 width
, height
, depth
, num_samples
,
970 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
971 ok
= intel_miptree_alloc_hiz(brw
, mt
);
979 intel_miptree_release(&mt
);
984 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
985 struct intel_mipmap_tree
*src
)
990 intel_miptree_release(dst
);
994 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1002 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1007 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1008 if (--(*mt
)->refcount
<= 0) {
1011 DBG("%s deleting %p\n", __func__
, *mt
);
1013 drm_intel_bo_unreference((*mt
)->bo
);
1014 intel_miptree_release(&(*mt
)->stencil_mt
);
1015 if ((*mt
)->hiz_buf
) {
1016 if ((*mt
)->hiz_buf
->mt
)
1017 intel_miptree_release(&(*mt
)->hiz_buf
->mt
);
1019 drm_intel_bo_unreference((*mt
)->hiz_buf
->bo
);
1020 free((*mt
)->hiz_buf
);
1022 intel_miptree_release(&(*mt
)->mcs_mt
);
1023 intel_resolve_map_clear(&(*mt
)->hiz_map
);
1025 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1026 free((*mt
)->level
[i
].slice
);
1036 intel_get_image_dims(struct gl_texture_image
*image
,
1037 int *width
, int *height
, int *depth
)
1039 switch (image
->TexObject
->Target
) {
1040 case GL_TEXTURE_1D_ARRAY
:
1041 /* For a 1D Array texture the OpenGL API will treat the image height as
1042 * the number of array slices. For Intel hardware, we treat the 1D array
1043 * as a 2D Array with a height of 1. So, here we want to swap image
1046 *width
= image
->Width
;
1048 *depth
= image
->Height
;
1051 *width
= image
->Width
;
1052 *height
= image
->Height
;
1053 *depth
= image
->Depth
;
1059 * Can the image be pulled into a unified mipmap tree? This mirrors
1060 * the completeness test in a lot of ways.
1062 * Not sure whether I want to pass gl_texture_image here.
1065 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1066 struct gl_texture_image
*image
)
1068 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1069 GLuint level
= intelImage
->base
.Base
.Level
;
1070 int width
, height
, depth
;
1072 /* glTexImage* choose the texture object based on the target passed in, and
1073 * objects can't change targets over their lifetimes, so this should be
1076 assert(image
->TexObject
->Target
== mt
->target
);
1078 mesa_format mt_format
= mt
->format
;
1079 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1080 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1081 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1082 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1083 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1084 mt_format
= mt
->etc_format
;
1086 if (image
->TexFormat
!= mt_format
)
1089 intel_get_image_dims(image
, &width
, &height
, &depth
);
1091 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1094 int level_depth
= mt
->level
[level
].depth
;
1095 if (mt
->num_samples
> 1) {
1096 switch (mt
->msaa_layout
) {
1097 case INTEL_MSAA_LAYOUT_NONE
:
1098 case INTEL_MSAA_LAYOUT_IMS
:
1100 case INTEL_MSAA_LAYOUT_UMS
:
1101 case INTEL_MSAA_LAYOUT_CMS
:
1102 level_depth
/= mt
->num_samples
;
1107 /* Test image dimensions against the base level image adjusted for
1108 * minification. This will also catch images not present in the
1109 * tree, changed targets, etc.
1111 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1112 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1113 depth
!= level_depth
) {
1117 if (image
->NumSamples
!= mt
->num_samples
)
1125 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1127 GLuint x
, GLuint y
, GLuint d
)
1129 mt
->level
[level
].depth
= d
;
1130 mt
->level
[level
].level_x
= x
;
1131 mt
->level
[level
].level_y
= y
;
1133 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1136 assert(mt
->level
[level
].slice
== NULL
);
1138 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
1139 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1140 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1145 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1146 GLuint level
, GLuint img
,
1149 if (img
== 0 && level
== 0)
1150 assert(x
== 0 && y
== 0);
1152 assert(img
< mt
->level
[level
].depth
);
1154 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1155 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1157 DBG("%s level %d img %d pos %d,%d\n",
1158 __func__
, level
, img
,
1159 mt
->level
[level
].slice
[img
].x_offset
,
1160 mt
->level
[level
].slice
[img
].y_offset
);
1164 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1165 GLuint level
, GLuint slice
,
1166 GLuint
*x
, GLuint
*y
)
1168 assert(slice
< mt
->level
[level
].depth
);
1170 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1171 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1176 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1177 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1178 * and tile_h is set to 1.
1181 intel_get_tile_dims(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1182 uint32_t *tile_w
, uint32_t *tile_h
)
1184 if (tr_mode
== INTEL_MIPTREE_TRMODE_NONE
) {
1194 case I915_TILING_NONE
:
1199 unreachable("not reached");
1202 uint32_t aspect_ratio
= 1;
1203 assert(_mesa_is_pow_two(cpp
));
1218 unreachable("not reached");
1221 if (cpp
== 2 || cpp
== 8)
1224 if (tr_mode
== INTEL_MIPTREE_TRMODE_YS
)
1227 *tile_w
= *tile_h
* aspect_ratio
* cpp
;
1233 * This function computes masks that may be used to select the bits of the X
1234 * and Y coordinates that indicate the offset within a tile. If the BO is
1235 * untiled, the masks are set to 0.
1238 intel_get_tile_masks(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1239 bool map_stencil_as_y_tiled
,
1240 uint32_t *mask_x
, uint32_t *mask_y
)
1242 uint32_t tile_w_bytes
, tile_h
;
1243 if (map_stencil_as_y_tiled
)
1244 tiling
= I915_TILING_Y
;
1246 intel_get_tile_dims(tiling
, tr_mode
, cpp
, &tile_w_bytes
, &tile_h
);
1248 *mask_x
= tile_w_bytes
/ cpp
- 1;
1249 *mask_y
= tile_h
- 1;
1253 * Compute the offset (in bytes) from the start of the BO to the given x
1254 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1255 * multiples of the tile size.
1258 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1259 uint32_t x
, uint32_t y
,
1260 bool map_stencil_as_y_tiled
)
1263 uint32_t pitch
= mt
->pitch
;
1264 uint32_t tiling
= mt
->tiling
;
1266 if (map_stencil_as_y_tiled
) {
1267 tiling
= I915_TILING_Y
;
1269 /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
1270 * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
1271 * the resulting surface is twice the pitch of the original miptree,
1272 * since each row in the Y-tiled view corresponds to two rows in the
1273 * actual W-tiled surface. So we need to correct the pitch before
1274 * computing the offsets.
1281 unreachable("not reached");
1282 case I915_TILING_NONE
:
1283 return y
* pitch
+ x
* cpp
;
1285 assert((x
% (512 / cpp
)) == 0);
1286 assert((y
% 8) == 0);
1287 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1289 assert((x
% (128 / cpp
)) == 0);
1290 assert((y
% 32) == 0);
1291 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1296 * Rendering with tiled buffers requires that the base address of the buffer
1297 * be aligned to a page boundary. For renderbuffers, and sometimes with
1298 * textures, we may want the surface to point at a texture image level that
1299 * isn't at a page boundary.
1301 * This function returns an appropriately-aligned base offset
1302 * according to the tiling restrictions, plus any required x/y offset
1306 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1307 GLuint level
, GLuint slice
,
1312 uint32_t mask_x
, mask_y
;
1314 intel_get_tile_masks(mt
->tiling
, mt
->tr_mode
, mt
->cpp
, false, &mask_x
, &mask_y
);
1315 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1317 *tile_x
= x
& mask_x
;
1318 *tile_y
= y
& mask_y
;
1320 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
, false);
1324 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1325 struct intel_mipmap_tree
*dst_mt
,
1326 struct intel_mipmap_tree
*src_mt
,
1333 ptrdiff_t src_stride
, dst_stride
;
1334 int cpp
= dst_mt
->cpp
;
1336 intel_miptree_map(brw
, src_mt
,
1340 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1343 intel_miptree_map(brw
, dst_mt
,
1347 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1351 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1352 _mesa_get_format_name(src_mt
->format
),
1353 src_mt
, src
, src_stride
,
1354 _mesa_get_format_name(dst_mt
->format
),
1355 dst_mt
, dst
, dst_stride
,
1358 int row_size
= cpp
* width
;
1359 if (src_stride
== row_size
&&
1360 dst_stride
== row_size
) {
1361 memcpy(dst
, src
, row_size
* height
);
1363 for (int i
= 0; i
< height
; i
++) {
1364 memcpy(dst
, src
, row_size
);
1370 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1371 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1373 /* Don't forget to copy the stencil data over, too. We could have skipped
1374 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1375 * shuffling the two data sources in/out of temporary storage instead of
1376 * the direct mapping we get this way.
1378 if (dst_mt
->stencil_mt
) {
1379 assert(src_mt
->stencil_mt
);
1380 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1381 level
, slice
, width
, height
);
1386 intel_miptree_copy_slice(struct brw_context
*brw
,
1387 struct intel_mipmap_tree
*dst_mt
,
1388 struct intel_mipmap_tree
*src_mt
,
1394 mesa_format format
= src_mt
->format
;
1395 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1396 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1404 assert(depth
< src_mt
->level
[level
].depth
);
1405 assert(src_mt
->format
== dst_mt
->format
);
1407 if (dst_mt
->compressed
) {
1409 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1410 height
= ALIGN_NPOT(height
, j
) / j
;
1411 width
= ALIGN_NPOT(width
, i
) / i
;
1414 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1415 * below won't apply since we can't do the depth's Y tiling or the
1416 * stencil's W tiling in the blitter.
1418 if (src_mt
->stencil_mt
) {
1419 intel_miptree_copy_slice_sw(brw
,
1426 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1427 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1428 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1430 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1431 _mesa_get_format_name(src_mt
->format
),
1432 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1433 _mesa_get_format_name(dst_mt
->format
),
1434 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1437 if (!intel_miptree_blit(brw
,
1438 src_mt
, level
, slice
, 0, 0, false,
1439 dst_mt
, level
, slice
, 0, 0, false,
1440 width
, height
, GL_COPY
)) {
1441 perf_debug("miptree validate blit for %s failed\n",
1442 _mesa_get_format_name(format
));
1444 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1450 * Copies the image's current data to the given miptree, and associates that
1451 * miptree with the image.
1453 * If \c invalidate is true, then the actual image data does not need to be
1454 * copied, but the image still needs to be associated to the new miptree (this
1455 * is set to true if we're about to clear the image).
1458 intel_miptree_copy_teximage(struct brw_context
*brw
,
1459 struct intel_texture_image
*intelImage
,
1460 struct intel_mipmap_tree
*dst_mt
,
1463 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1464 struct intel_texture_object
*intel_obj
=
1465 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1466 int level
= intelImage
->base
.Base
.Level
;
1467 int face
= intelImage
->base
.Base
.Face
;
1470 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
)
1471 depth
= intelImage
->base
.Base
.Height
;
1473 depth
= intelImage
->base
.Base
.Depth
;
1476 for (int slice
= 0; slice
< depth
; slice
++) {
1477 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1481 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1482 intel_obj
->needs_validate
= true;
1486 intel_miptree_init_mcs(struct brw_context
*brw
,
1487 struct intel_mipmap_tree
*mt
,
1490 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1492 * When MCS buffer is enabled and bound to MSRT, it is required that it
1493 * is cleared prior to any rendering.
1495 * Since we don't use the MCS buffer for any purpose other than rendering,
1496 * it makes sense to just clear it immediately upon allocation.
1498 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1500 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1501 memset(data
, init_value
, mt
->mcs_mt
->total_height
* mt
->mcs_mt
->pitch
);
1502 intel_miptree_unmap_raw(mt
->mcs_mt
);
1503 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1507 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1508 struct intel_mipmap_tree
*mt
,
1511 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1512 assert(mt
->mcs_mt
== NULL
);
1513 assert(!mt
->disable_aux_buffers
);
1515 /* Choose the correct format for the MCS buffer. All that really matters
1516 * is that we allocate the right buffer size, since we'll always be
1517 * accessing this miptree using MCS-specific hardware mechanisms, which
1518 * infer the correct format based on num_samples.
1521 switch (num_samples
) {
1524 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1527 format
= MESA_FORMAT_R_UNORM8
;
1530 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1531 * for each sample, plus 8 padding bits).
1533 format
= MESA_FORMAT_R_UINT32
;
1536 /* 64 bits/pixel are required for MCS data when using 16x MSAA (4 bits
1539 format
= MESA_FORMAT_RG_UINT32
;
1542 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1545 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1547 * "The MCS surface must be stored as Tile Y."
1549 const uint32_t mcs_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1550 MIPTREE_LAYOUT_TILING_Y
;
1551 mt
->mcs_mt
= miptree_create(brw
,
1557 mt
->logical_height0
,
1559 0 /* num_samples */,
1562 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1569 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1570 struct intel_mipmap_tree
*mt
)
1572 assert(mt
->mcs_mt
== NULL
);
1573 assert(!mt
->disable_aux_buffers
);
1575 /* The format of the MCS buffer is opaque to the driver; all that matters
1576 * is that we get its size and pitch right. We'll pretend that the format
1577 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1578 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1579 * the block width and then a further factor of 4. Since an MCS tile
1580 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1581 * we'll need to scale the height down by the block height and then a
1582 * further factor of 8.
1584 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1585 unsigned block_width_px
;
1586 unsigned block_height
;
1587 intel_get_non_msrt_mcs_alignment(mt
, &block_width_px
, &block_height
);
1588 unsigned width_divisor
= block_width_px
* 4;
1589 unsigned height_divisor
= block_height
* 8;
1591 /* The Skylake MCS is twice as tall as the Broadwell MCS.
1593 * In pre-Skylake, each bit in the MCS contained the state of 2 cachelines
1594 * in the main surface. In Skylake, it's two bits. The extra bit
1595 * doubles the MCS height, not width, because in Skylake the MCS is always
1599 height_divisor
/= 2;
1601 unsigned mcs_width
=
1602 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1603 unsigned mcs_height
=
1604 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1605 assert(mt
->logical_depth0
== 1);
1606 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1607 MIPTREE_LAYOUT_TILING_Y
;
1608 if (brw
->gen
>= 8) {
1609 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
1611 mt
->mcs_mt
= miptree_create(brw
,
1619 0 /* num_samples */,
1626 intel_miptree_prepare_mcs(struct brw_context
*brw
,
1627 struct intel_mipmap_tree
*mt
)
1635 /* Single sample compression is represented re-using msaa compression
1636 * layout type: "Compressed Multisampled Surfaces".
1638 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
|| mt
->num_samples
> 1)
1641 /* Clients are not currently capable of consuming compressed
1642 * single-sampled buffers.
1647 assert(intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) ||
1648 intel_miptree_supports_lossless_compressed(brw
, mt
));
1650 /* Consider if lossless compression is supported but the needed
1651 * auxiliary buffer doesn't exist yet.
1653 * Failing to allocate the auxiliary buffer means running out of
1654 * memory. The pointer to the aux miptree is left NULL which should
1655 * signal non-compressed behavior.
1657 if (!intel_miptree_alloc_non_msrt_mcs(brw
, mt
)) {
1659 "Failed to allocated aux buffer for lossless"
1660 " compressed %p %u:%u %s\n",
1661 mt
, mt
->logical_width0
, mt
->logical_height0
,
1662 _mesa_get_format_name(mt
->format
));
1667 * Helper for intel_miptree_alloc_hiz() that sets
1668 * \c mt->level[level].has_hiz. Return true if and only if
1669 * \c has_hiz was set.
1672 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1673 struct intel_mipmap_tree
*mt
,
1676 assert(mt
->hiz_buf
);
1678 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1679 uint32_t width
= minify(mt
->physical_width0
, level
);
1680 uint32_t height
= minify(mt
->physical_height0
, level
);
1682 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1683 * and the height is 4 aligned. This allows our HiZ support
1684 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1685 * we can grow the width & height to allow the HiZ op to
1686 * force the proper size alignments.
1688 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1689 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1694 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1695 mt
->level
[level
].has_hiz
= true;
1701 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1702 * buffer dimensions and allocates a bo for the hiz buffer.
1704 static struct intel_miptree_aux_buffer
*
1705 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1706 struct intel_mipmap_tree
*mt
)
1708 unsigned z_width
= mt
->logical_width0
;
1709 unsigned z_height
= mt
->logical_height0
;
1710 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1711 unsigned hz_width
, hz_height
;
1712 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1717 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1718 * adjustments required for Z_Height and Z_Width based on multisampling.
1720 switch (mt
->num_samples
) {
1734 unreachable("unsupported sample count");
1737 const unsigned vertical_align
= 8; /* 'j' in the docs */
1738 const unsigned H0
= z_height
;
1739 const unsigned h0
= ALIGN(H0
, vertical_align
);
1740 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1741 const unsigned Z0
= z_depth
;
1743 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1744 hz_width
= ALIGN(z_width
, 16);
1746 if (mt
->target
== GL_TEXTURE_3D
) {
1750 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1751 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1752 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1753 hz_height
+= h_i
* Z_i
;
1754 H_i
= minify(H_i
, 1);
1755 Z_i
= minify(Z_i
, 1);
1758 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1760 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1762 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1763 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1764 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1765 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth * 6/2) /8 ) * 8 */
1766 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
* 6, 2 * 8) * 8;
1768 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1769 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1773 unsigned long pitch
;
1774 uint32_t tiling
= I915_TILING_Y
;
1775 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1776 hz_width
, hz_height
, 1,
1778 BO_ALLOC_FOR_RENDER
);
1782 } else if (tiling
!= I915_TILING_Y
) {
1783 drm_intel_bo_unreference(buf
->bo
);
1795 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1796 * buffer dimensions and allocates a bo for the hiz buffer.
1798 static struct intel_miptree_aux_buffer
*
1799 intel_gen8_hiz_buf_create(struct brw_context
*brw
,
1800 struct intel_mipmap_tree
*mt
)
1802 unsigned z_width
= mt
->logical_width0
;
1803 unsigned z_height
= mt
->logical_height0
;
1804 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1805 unsigned hz_width
, hz_height
;
1806 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1811 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1812 * adjustments required for Z_Height and Z_Width based on multisampling.
1815 switch (mt
->num_samples
) {
1829 unreachable("unsupported sample count");
1833 const unsigned vertical_align
= 8; /* 'j' in the docs */
1834 const unsigned H0
= z_height
;
1835 const unsigned h0
= ALIGN(H0
, vertical_align
);
1836 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1837 const unsigned Z0
= z_depth
;
1839 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1840 hz_width
= ALIGN(z_width
, 16);
1844 unsigned sum_h_i
= 0;
1845 unsigned hz_height_3d_sum
= 0;
1846 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1847 unsigned i
= level
- mt
->first_level
;
1848 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1849 /* sum(i=2 to m; h_i) */
1853 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1854 hz_height_3d_sum
+= h_i
* Z_i
;
1855 H_i
= minify(H_i
, 1);
1856 Z_i
= minify(Z_i
, 1);
1858 /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
1859 buf
->qpitch
= h0
+ MAX2(h1
, sum_h_i
);
1861 if (mt
->target
== GL_TEXTURE_3D
) {
1862 /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1863 hz_height
= DIV_ROUND_UP(hz_height_3d_sum
, 2);
1865 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
1866 hz_height
= DIV_ROUND_UP(buf
->qpitch
, 2 * 8) * 8 * Z0
;
1867 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1868 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1869 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * 6 * Z_Depth
1871 * We can can just take our hz_height calculation from above, and
1872 * multiply by 6 for the cube map and cube map array types.
1878 unsigned long pitch
;
1879 uint32_t tiling
= I915_TILING_Y
;
1880 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1881 hz_width
, hz_height
, 1,
1883 BO_ALLOC_FOR_RENDER
);
1887 } else if (tiling
!= I915_TILING_Y
) {
1888 drm_intel_bo_unreference(buf
->bo
);
1899 static struct intel_miptree_aux_buffer
*
1900 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
1901 struct intel_mipmap_tree
*mt
)
1903 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1904 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1907 layout_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
;
1912 layout_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
1913 buf
->mt
= intel_miptree_create(brw
,
1919 mt
->logical_height0
,
1928 buf
->bo
= buf
->mt
->bo
;
1929 buf
->pitch
= buf
->mt
->pitch
;
1930 buf
->qpitch
= buf
->mt
->qpitch
;
1936 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
1937 struct intel_mipmap_tree
*mt
)
1942 if (mt
->hiz_buf
!= NULL
)
1945 if (mt
->disable_aux_buffers
)
1948 switch (mt
->format
) {
1949 case MESA_FORMAT_Z_FLOAT32
:
1950 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
1951 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
1952 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
1953 case MESA_FORMAT_Z_UNORM16
:
1961 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1962 struct intel_mipmap_tree
*mt
)
1964 assert(mt
->hiz_buf
== NULL
);
1965 assert(!mt
->disable_aux_buffers
);
1967 if (brw
->gen
== 7) {
1968 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
1969 } else if (brw
->gen
>= 8) {
1970 mt
->hiz_buf
= intel_gen8_hiz_buf_create(brw
, mt
);
1972 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
1978 /* Mark that all slices need a HiZ resolve. */
1979 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1980 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
1983 for (unsigned layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1984 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
1985 exec_node_init(&m
->link
);
1988 m
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1990 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
1998 * Does the miptree slice have hiz enabled?
2001 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
2003 intel_miptree_check_level_layer(mt
, level
, 0);
2004 return mt
->level
[level
].has_hiz
;
2008 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
2012 if (!intel_miptree_level_has_hiz(mt
, level
))
2015 intel_resolve_map_set(&mt
->hiz_map
,
2016 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
2021 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
2025 if (!intel_miptree_level_has_hiz(mt
, level
))
2028 intel_resolve_map_set(&mt
->hiz_map
,
2029 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
2033 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
2037 uint32_t end_layer
= mt
->level
[level
].depth
;
2039 for (layer
= 0; layer
< end_layer
; layer
++) {
2040 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
2045 intel_miptree_slice_resolve(struct brw_context
*brw
,
2046 struct intel_mipmap_tree
*mt
,
2049 enum gen6_hiz_op need
)
2051 intel_miptree_check_level_layer(mt
, level
, layer
);
2053 struct intel_resolve_map
*item
=
2054 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
2056 if (!item
|| item
->need
!= need
)
2059 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
2060 intel_resolve_map_remove(item
);
2065 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
2066 struct intel_mipmap_tree
*mt
,
2070 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
2071 GEN6_HIZ_OP_HIZ_RESOLVE
);
2075 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
2076 struct intel_mipmap_tree
*mt
,
2080 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
2081 GEN6_HIZ_OP_DEPTH_RESOLVE
);
2085 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
2086 struct intel_mipmap_tree
*mt
,
2087 enum gen6_hiz_op need
)
2089 bool did_resolve
= false;
2091 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
2092 if (map
->need
!= need
)
2095 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
2096 intel_resolve_map_remove(map
);
2104 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
2105 struct intel_mipmap_tree
*mt
)
2107 return intel_miptree_all_slices_resolve(brw
, mt
,
2108 GEN6_HIZ_OP_HIZ_RESOLVE
);
2112 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
2113 struct intel_mipmap_tree
*mt
)
2115 return intel_miptree_all_slices_resolve(brw
, mt
,
2116 GEN6_HIZ_OP_DEPTH_RESOLVE
);
2121 intel_miptree_resolve_color(struct brw_context
*brw
,
2122 struct intel_mipmap_tree
*mt
,
2125 /* From gen9 onwards there is new compression scheme for single sampled
2126 * surfaces called "lossless compressed". These don't need to be always
2129 if ((flags
& INTEL_MIPTREE_IGNORE_CCS_E
) &&
2130 intel_miptree_is_lossless_compressed(brw
, mt
))
2133 switch (mt
->fast_clear_state
) {
2134 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
2135 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
2136 /* No resolve needed */
2138 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
2139 case INTEL_FAST_CLEAR_STATE_CLEAR
:
2140 /* Fast color clear resolves only make sense for non-MSAA buffers. */
2141 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
||
2142 intel_miptree_is_lossless_compressed(brw
, mt
)) {
2143 brw_blorp_resolve_color(brw
, mt
);
2151 * Make it possible to share the BO backing the given miptree with another
2152 * process or another miptree.
2154 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2155 * then discard the MCS buffer, if present. We also set the fast_clear_state
2156 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
2157 * allocated in the future.
2160 intel_miptree_make_shareable(struct brw_context
*brw
,
2161 struct intel_mipmap_tree
*mt
)
2163 /* MCS buffers are also used for multisample buffers, but we can't resolve
2164 * away a multisample MCS buffer because it's an integral part of how the
2165 * pixel data is stored. Fortunately this code path should never be
2166 * reached for multisample buffers.
2168 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
2171 intel_miptree_resolve_color(brw
, mt
, 0);
2172 intel_miptree_release(&mt
->mcs_mt
);
2173 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
2179 * \brief Get pointer offset into stencil buffer.
2181 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2182 * must decode the tile's layout in software.
2185 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2187 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2189 * Even though the returned offset is always positive, the return type is
2191 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2192 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2195 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2197 uint32_t tile_size
= 4096;
2198 uint32_t tile_width
= 64;
2199 uint32_t tile_height
= 64;
2200 uint32_t row_size
= 64 * stride
;
2202 uint32_t tile_x
= x
/ tile_width
;
2203 uint32_t tile_y
= y
/ tile_height
;
2205 /* The byte's address relative to the tile's base addres. */
2206 uint32_t byte_x
= x
% tile_width
;
2207 uint32_t byte_y
= y
% tile_height
;
2209 uintptr_t u
= tile_y
* row_size
2210 + tile_x
* tile_size
2211 + 512 * (byte_x
/ 8)
2213 + 32 * ((byte_y
/ 4) % 2)
2214 + 16 * ((byte_x
/ 4) % 2)
2215 + 8 * ((byte_y
/ 2) % 2)
2216 + 4 * ((byte_x
/ 2) % 2)
2221 /* adjust for bit6 swizzling */
2222 if (((byte_x
/ 8) % 2) == 1) {
2223 if (((byte_y
/ 8) % 2) == 0) {
2235 intel_miptree_updownsample(struct brw_context
*brw
,
2236 struct intel_mipmap_tree
*src
,
2237 struct intel_mipmap_tree
*dst
)
2239 /* There is support for only up to eight samples. */
2240 const bool use_blorp
= src
->num_samples
<= 8 && dst
->num_samples
<= 8;
2243 brw_blorp_blit_miptrees(brw
,
2244 src
, 0 /* level */, 0 /* layer */,
2245 src
->format
, SWIZZLE_XYZW
,
2246 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2248 src
->logical_width0
, src
->logical_height0
,
2250 dst
->logical_width0
, dst
->logical_height0
,
2251 GL_NEAREST
, false, false /*mirror x, y*/,
2253 } else if (src
->format
== MESA_FORMAT_S_UINT8
) {
2254 brw_meta_stencil_updownsample(brw
, src
, dst
);
2256 brw_meta_updownsample(brw
, src
, dst
);
2259 if (src
->stencil_mt
) {
2261 brw_meta_stencil_updownsample(brw
, src
->stencil_mt
, dst
);
2265 brw_blorp_blit_miptrees(brw
,
2266 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2267 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2268 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2269 dst
->stencil_mt
->format
,
2271 src
->logical_width0
, src
->logical_height0
,
2273 dst
->logical_width0
, dst
->logical_height0
,
2274 GL_NEAREST
, false, false /*mirror x, y*/,
2275 false, false /* decode/encode srgb */);
2280 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
2282 /* CPU accesses to color buffers don't understand fast color clears, so
2283 * resolve any pending fast color clears before we map.
2285 intel_miptree_resolve_color(brw
, mt
, 0);
2287 drm_intel_bo
*bo
= mt
->bo
;
2289 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
2290 intel_batchbuffer_flush(brw
);
2292 if (mt
->tiling
!= I915_TILING_NONE
)
2293 brw_bo_map_gtt(brw
, bo
, "miptree");
2295 brw_bo_map(brw
, bo
, true, "miptree");
2301 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2303 drm_intel_bo_unmap(mt
->bo
);
2307 intel_miptree_map_gtt(struct brw_context
*brw
,
2308 struct intel_mipmap_tree
*mt
,
2309 struct intel_miptree_map
*map
,
2310 unsigned int level
, unsigned int slice
)
2312 unsigned int bw
, bh
;
2314 unsigned int image_x
, image_y
;
2315 intptr_t x
= map
->x
;
2316 intptr_t y
= map
->y
;
2318 /* For compressed formats, the stride is the number of bytes per
2319 * row of blocks. intel_miptree_get_image_offset() already does
2322 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2323 assert(y
% bh
== 0);
2324 assert(x
% bw
== 0);
2328 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
2333 /* Note that in the case of cube maps, the caller must have passed the
2334 * slice number referencing the face.
2336 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2340 map
->stride
= mt
->pitch
;
2341 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2344 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2345 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2346 map
->x
, map
->y
, map
->w
, map
->h
,
2347 mt
, _mesa_get_format_name(mt
->format
),
2348 x
, y
, map
->ptr
, map
->stride
);
2352 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2354 intel_miptree_unmap_raw(mt
);
2358 intel_miptree_map_blit(struct brw_context
*brw
,
2359 struct intel_mipmap_tree
*mt
,
2360 struct intel_miptree_map
*map
,
2361 unsigned int level
, unsigned int slice
)
2363 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2364 /* first_level */ 0,
2368 MIPTREE_LAYOUT_TILING_NONE
);
2370 if (!map
->linear_mt
) {
2371 fprintf(stderr
, "Failed to allocate blit temporary\n");
2374 map
->stride
= map
->linear_mt
->pitch
;
2376 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2377 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2378 * invalidate is set, since we'll be writing the whole rectangle from our
2379 * temporary buffer back out.
2381 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2382 if (!intel_miptree_blit(brw
,
2384 map
->x
, map
->y
, false,
2385 map
->linear_mt
, 0, 0,
2387 map
->w
, map
->h
, GL_COPY
)) {
2388 fprintf(stderr
, "Failed to blit\n");
2393 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
);
2395 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2396 map
->x
, map
->y
, map
->w
, map
->h
,
2397 mt
, _mesa_get_format_name(mt
->format
),
2398 level
, slice
, map
->ptr
, map
->stride
);
2403 intel_miptree_release(&map
->linear_mt
);
2409 intel_miptree_unmap_blit(struct brw_context
*brw
,
2410 struct intel_mipmap_tree
*mt
,
2411 struct intel_miptree_map
*map
,
2415 struct gl_context
*ctx
= &brw
->ctx
;
2417 intel_miptree_unmap_raw(map
->linear_mt
);
2419 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2420 bool ok
= intel_miptree_blit(brw
,
2421 map
->linear_mt
, 0, 0,
2424 map
->x
, map
->y
, false,
2425 map
->w
, map
->h
, GL_COPY
);
2426 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2429 intel_miptree_release(&map
->linear_mt
);
2433 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2435 #if defined(USE_SSE41)
2437 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2438 struct intel_mipmap_tree
*mt
,
2439 struct intel_miptree_map
*map
,
2440 unsigned int level
, unsigned int slice
)
2442 assert(map
->mode
& GL_MAP_READ_BIT
);
2443 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2445 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2446 map
->x
, map
->y
, map
->w
, map
->h
,
2447 mt
, _mesa_get_format_name(mt
->format
),
2448 level
, slice
, map
->ptr
, map
->stride
);
2450 /* Map the original image */
2453 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2457 void *src
= intel_miptree_map_raw(brw
, mt
);
2460 src
+= image_y
* mt
->pitch
;
2461 src
+= image_x
* mt
->cpp
;
2463 /* Due to the pixel offsets for the particular image being mapped, our
2464 * src pointer may not be 16-byte aligned. However, if the pitch is
2465 * divisible by 16, then the amount by which it's misaligned will remain
2466 * consistent from row to row.
2468 assert((mt
->pitch
% 16) == 0);
2469 const int misalignment
= ((uintptr_t) src
) & 15;
2471 /* Create an untiled temporary buffer for the mapping. */
2472 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
2474 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
2476 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
2477 /* Offset the destination so it has the same misalignment as src. */
2478 map
->ptr
= map
->buffer
+ misalignment
;
2480 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
2482 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2483 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
2484 void *src_ptr
= src
+ y
* mt
->pitch
;
2486 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
2489 intel_miptree_unmap_raw(mt
);
2493 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
2494 struct intel_mipmap_tree
*mt
,
2495 struct intel_miptree_map
*map
,
2499 _mesa_align_free(map
->buffer
);
2506 intel_miptree_map_s8(struct brw_context
*brw
,
2507 struct intel_mipmap_tree
*mt
,
2508 struct intel_miptree_map
*map
,
2509 unsigned int level
, unsigned int slice
)
2511 map
->stride
= map
->w
;
2512 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2516 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2517 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2518 * invalidate is set, since we'll be writing the whole rectangle from our
2519 * temporary buffer back out.
2521 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2522 uint8_t *untiled_s8_map
= map
->ptr
;
2523 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2524 unsigned int image_x
, image_y
;
2526 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2528 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2529 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2530 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2531 x
+ image_x
+ map
->x
,
2532 y
+ image_y
+ map
->y
,
2533 brw
->has_swizzling
);
2534 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
2538 intel_miptree_unmap_raw(mt
);
2540 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
2541 map
->x
, map
->y
, map
->w
, map
->h
,
2542 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
2544 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2545 map
->x
, map
->y
, map
->w
, map
->h
,
2546 mt
, map
->ptr
, map
->stride
);
2551 intel_miptree_unmap_s8(struct brw_context
*brw
,
2552 struct intel_mipmap_tree
*mt
,
2553 struct intel_miptree_map
*map
,
2557 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2558 unsigned int image_x
, image_y
;
2559 uint8_t *untiled_s8_map
= map
->ptr
;
2560 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2562 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2564 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2565 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2566 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2567 image_x
+ x
+ map
->x
,
2568 image_y
+ y
+ map
->y
,
2569 brw
->has_swizzling
);
2570 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
2574 intel_miptree_unmap_raw(mt
);
2581 intel_miptree_map_etc(struct brw_context
*brw
,
2582 struct intel_mipmap_tree
*mt
,
2583 struct intel_miptree_map
*map
,
2587 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
2588 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
2589 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2592 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2593 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2595 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2596 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2597 map
->w
, map
->h
, 1));
2598 map
->ptr
= map
->buffer
;
2602 intel_miptree_unmap_etc(struct brw_context
*brw
,
2603 struct intel_mipmap_tree
*mt
,
2604 struct intel_miptree_map
*map
,
2610 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2615 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2616 + image_y
* mt
->pitch
2617 + image_x
* mt
->cpp
;
2619 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2620 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2621 map
->ptr
, map
->stride
,
2624 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2625 map
->ptr
, map
->stride
,
2626 map
->w
, map
->h
, mt
->etc_format
);
2628 intel_miptree_unmap_raw(mt
);
2633 * Mapping function for packed depth/stencil miptrees backed by real separate
2634 * miptrees for depth and stencil.
2636 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2637 * separate from the depth buffer. Yet at the GL API level, we have to expose
2638 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2639 * be able to map that memory for texture storage and glReadPixels-type
2640 * operations. We give Mesa core that access by mallocing a temporary and
2641 * copying the data between the actual backing store and the temporary.
2644 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2645 struct intel_mipmap_tree
*mt
,
2646 struct intel_miptree_map
*map
,
2647 unsigned int level
, unsigned int slice
)
2649 struct intel_mipmap_tree
*z_mt
= mt
;
2650 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2651 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2652 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2654 map
->stride
= map
->w
* packed_bpp
;
2655 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2659 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2660 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2661 * invalidate is set, since we'll be writing the whole rectangle from our
2662 * temporary buffer back out.
2664 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2665 uint32_t *packed_map
= map
->ptr
;
2666 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2667 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2668 unsigned int s_image_x
, s_image_y
;
2669 unsigned int z_image_x
, z_image_y
;
2671 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2672 &s_image_x
, &s_image_y
);
2673 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2674 &z_image_x
, &z_image_y
);
2676 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2677 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2678 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2679 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2682 brw
->has_swizzling
);
2683 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2685 (map_x
+ z_image_x
));
2686 uint8_t s
= s_map
[s_offset
];
2687 uint32_t z
= z_map
[z_offset
];
2689 if (map_z32f_x24s8
) {
2690 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2691 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2693 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2698 intel_miptree_unmap_raw(s_mt
);
2699 intel_miptree_unmap_raw(z_mt
);
2701 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2703 map
->x
, map
->y
, map
->w
, map
->h
,
2704 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2705 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2706 map
->ptr
, map
->stride
);
2708 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2709 map
->x
, map
->y
, map
->w
, map
->h
,
2710 mt
, map
->ptr
, map
->stride
);
2715 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2716 struct intel_mipmap_tree
*mt
,
2717 struct intel_miptree_map
*map
,
2721 struct intel_mipmap_tree
*z_mt
= mt
;
2722 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2723 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2725 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2726 uint32_t *packed_map
= map
->ptr
;
2727 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2728 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2729 unsigned int s_image_x
, s_image_y
;
2730 unsigned int z_image_x
, z_image_y
;
2732 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2733 &s_image_x
, &s_image_y
);
2734 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2735 &z_image_x
, &z_image_y
);
2737 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2738 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2739 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2740 x
+ s_image_x
+ map
->x
,
2741 y
+ s_image_y
+ map
->y
,
2742 brw
->has_swizzling
);
2743 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2745 (x
+ z_image_x
+ map
->x
));
2747 if (map_z32f_x24s8
) {
2748 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2749 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2751 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2752 s_map
[s_offset
] = packed
>> 24;
2753 z_map
[z_offset
] = packed
;
2758 intel_miptree_unmap_raw(s_mt
);
2759 intel_miptree_unmap_raw(z_mt
);
2761 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2763 map
->x
, map
->y
, map
->w
, map
->h
,
2764 z_mt
, _mesa_get_format_name(z_mt
->format
),
2765 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2766 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2767 map
->ptr
, map
->stride
);
2774 * Create and attach a map to the miptree at (level, slice). Return the
2777 static struct intel_miptree_map
*
2778 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2787 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2792 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2793 mt
->level
[level
].slice
[slice
].map
= map
;
2805 * Release the map at (level, slice).
2808 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2812 struct intel_miptree_map
**map
;
2814 map
= &mt
->level
[level
].slice
[slice
].map
;
2820 can_blit_slice(struct intel_mipmap_tree
*mt
,
2821 unsigned int level
, unsigned int slice
)
2825 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2826 if (image_x
>= 32768 || image_y
>= 32768)
2829 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2830 if (mt
->pitch
>= 32768)
2837 use_intel_mipree_map_blit(struct brw_context
*brw
,
2838 struct intel_mipmap_tree
*mt
,
2844 /* It's probably not worth swapping to the blit ring because of
2845 * all the overhead involved. But, we must use blitter for the
2846 * surfaces with INTEL_MIPTREE_TRMODE_{YF,YS}.
2848 (!(mode
& GL_MAP_WRITE_BIT
) ||
2849 mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) &&
2851 (mt
->tiling
== I915_TILING_X
||
2852 /* Prior to Sandybridge, the blitter can't handle Y tiling */
2853 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
) ||
2854 /* Fast copy blit on skl+ supports all tiling formats. */
2856 can_blit_slice(mt
, level
, slice
))
2859 if (mt
->tiling
!= I915_TILING_NONE
&&
2860 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2861 assert(can_blit_slice(mt
, level
, slice
));
2869 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
2870 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
2871 * arithmetic overflow.
2873 * If you call this function and use \a out_stride, then you're doing pointer
2874 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
2875 * bugs. The caller must still take care to avoid 32-bit overflow errors in
2876 * all arithmetic expressions that contain buffer offsets and pixel sizes,
2877 * which usually have type uint32_t or GLuint.
2880 intel_miptree_map(struct brw_context
*brw
,
2881 struct intel_mipmap_tree
*mt
,
2890 ptrdiff_t *out_stride
)
2892 struct intel_miptree_map
*map
;
2894 assert(mt
->num_samples
<= 1);
2896 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2903 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2904 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2905 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2908 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2909 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2910 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2911 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2912 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2913 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2914 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2915 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
2916 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2917 #if defined(USE_SSE41)
2918 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
2919 !mt
->compressed
&& cpu_has_sse4_1
&&
2920 (mt
->pitch
% 16 == 0)) {
2921 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2924 /* intel_miptree_map_gtt() doesn't support surfaces with Yf/Ys tiling. */
2925 assert(mt
->tr_mode
== INTEL_MIPTREE_TRMODE_NONE
);
2926 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2929 *out_ptr
= map
->ptr
;
2930 *out_stride
= map
->stride
;
2932 if (map
->ptr
== NULL
)
2933 intel_miptree_release_map(mt
, level
, slice
);
2937 intel_miptree_unmap(struct brw_context
*brw
,
2938 struct intel_mipmap_tree
*mt
,
2942 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2944 assert(mt
->num_samples
<= 1);
2949 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
2950 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2952 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2953 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2954 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2955 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2956 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2957 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2958 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2959 } else if (map
->linear_mt
) {
2960 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2961 #if defined(USE_SSE41)
2962 } else if (map
->buffer
&& cpu_has_sse4_1
) {
2963 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2966 intel_miptree_unmap_gtt(mt
);
2969 intel_miptree_release_map(mt
, level
, slice
);