2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
28 #include <drm_fourcc.h>
30 #include "intel_batchbuffer.h"
31 #include "intel_image.h"
32 #include "intel_mipmap_tree.h"
33 #include "intel_tex.h"
34 #include "intel_blit.h"
35 #include "intel_fbo.h"
37 #include "brw_blorp.h"
38 #include "brw_context.h"
39 #include "brw_meta_util.h"
40 #include "brw_state.h"
42 #include "main/enums.h"
43 #include "main/fbobject.h"
44 #include "main/formats.h"
45 #include "main/glformats.h"
46 #include "main/texcompress_etc.h"
47 #include "main/teximage.h"
48 #include "main/streaming-load-memcpy.h"
49 #include "x86/common_x86_asm.h"
51 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
53 static void *intel_miptree_map_raw(struct brw_context
*brw
,
54 struct intel_mipmap_tree
*mt
,
57 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
60 intel_miptree_alloc_aux(struct brw_context
*brw
,
61 struct intel_mipmap_tree
*mt
);
64 intel_miptree_supports_mcs(struct brw_context
*brw
,
65 const struct intel_mipmap_tree
*mt
)
67 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
69 /* MCS compression only applies to multisampled miptrees */
70 if (mt
->surf
.samples
<= 1)
73 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
77 /* See isl_surf_get_mcs_surf for details. */
78 if (mt
->surf
.samples
== 16 && mt
->surf
.logical_level0_px
.width
> 8192)
81 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
82 switch (_mesa_get_format_base_format(mt
->format
)) {
83 case GL_DEPTH_COMPONENT
:
84 case GL_STENCIL_INDEX
:
85 case GL_DEPTH_STENCIL
:
88 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
90 * This field must be set to 0 for all SINT MSRTs when all RT channels
93 * In practice this means that we have to disable MCS for all signed
94 * integer MSAA buffers. The alternative, to disable MCS only when one
95 * of the render target channels is disabled, is impractical because it
96 * would require converting between CMS and UMS MSAA layouts on the fly,
99 if (devinfo
->gen
== 7 && _mesa_get_format_datatype(mt
->format
) == GL_INT
) {
108 intel_tiling_supports_ccs(const struct brw_context
*brw
,
109 enum isl_tiling tiling
)
111 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
113 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
114 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
116 * - Support is limited to tiled render targets.
118 * Gen9 changes the restriction to Y-tile only.
120 if (devinfo
->gen
>= 9)
121 return tiling
== ISL_TILING_Y0
;
122 else if (devinfo
->gen
>= 7)
123 return tiling
!= ISL_TILING_LINEAR
;
129 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
130 * can be used. This doesn't (and should not) inspect any of the properties of
133 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
134 * beneath the "Fast Color Clear" bullet (p326):
136 * - Support is for non-mip-mapped and non-array surface types only.
138 * And then later, on p327:
140 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
143 * From the Skylake documentation, it is made clear that X-tiling is no longer
146 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
150 intel_miptree_supports_ccs(struct brw_context
*brw
,
151 const struct intel_mipmap_tree
*mt
)
153 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
155 /* MCS support does not exist prior to Gen7 */
156 if (devinfo
->gen
< 7)
159 /* This function applies only to non-multisampled render targets. */
160 if (mt
->surf
.samples
> 1)
163 /* MCS is only supported for color buffers */
164 switch (_mesa_get_format_base_format(mt
->format
)) {
165 case GL_DEPTH_COMPONENT
:
166 case GL_DEPTH_STENCIL
:
167 case GL_STENCIL_INDEX
:
171 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
174 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
175 const bool arrayed
= mt
->surf
.logical_level0_px
.array_len
> 1 ||
176 mt
->surf
.logical_level0_px
.depth
> 1;
179 /* Multisample surfaces with the CMS layout are not layered surfaces,
180 * yet still have physical_depth0 > 1. Assert that we don't
181 * accidentally reject a multisampled surface here. We should have
182 * rejected it earlier by explicitly checking the sample count.
184 assert(mt
->surf
.samples
== 1);
187 /* Handle the hardware restrictions...
189 * All GENs have the following restriction: "MCS buffer for non-MSRT is
190 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
192 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
193 * Non-MultiSampler Render Target Restrictions) Support is for
194 * non-mip-mapped and non-array surface types only.
196 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
197 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
198 * surfaces are supported with MCS buffer layout with these alignments in
199 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
201 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
202 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
203 * surfaces are supported with MCS buffer layout with these alignments in
204 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
206 if (devinfo
->gen
< 8 && (mip_mapped
|| arrayed
))
209 /* There's no point in using an MCS buffer if the surface isn't in a
212 if (!brw
->mesa_format_supports_render
[mt
->format
])
219 intel_tiling_supports_hiz(const struct brw_context
*brw
,
220 enum isl_tiling tiling
)
222 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
224 if (devinfo
->gen
< 6)
227 return tiling
== ISL_TILING_Y0
;
231 intel_miptree_supports_hiz(const struct brw_context
*brw
,
232 const struct intel_mipmap_tree
*mt
)
237 switch (mt
->format
) {
238 case MESA_FORMAT_Z_FLOAT32
:
239 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
240 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
241 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
242 case MESA_FORMAT_Z_UNORM16
:
250 * Return true if the format that will be used to access the miptree is
251 * CCS_E-compatible with the miptree's linear/non-sRGB format.
253 * Why use the linear format? Well, although the miptree may be specified with
254 * an sRGB format, the usage of that color space/format can be toggled. Since
255 * our HW tends to support more linear formats than sRGB ones, we use this
256 * format variant for check for CCS_E compatibility.
259 format_ccs_e_compat_with_miptree(const struct gen_device_info
*devinfo
,
260 const struct intel_mipmap_tree
*mt
,
261 enum isl_format access_format
)
263 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
265 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
266 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
267 return isl_formats_are_ccs_e_compatible(devinfo
, isl_format
, access_format
);
271 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
272 const struct intel_mipmap_tree
*mt
)
274 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
276 if (devinfo
->gen
< 9)
279 /* For now compression is only enabled for integer formats even though
280 * there exist supported floating point formats also. This is a heuristic
281 * decision based on current public benchmarks. In none of the cases these
282 * formats provided any improvement but a few cases were seen to regress.
283 * Hence these are left to to be enabled in the future when they are known
286 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
289 if (!intel_miptree_supports_ccs(brw
, mt
))
292 /* Many window system buffers are sRGB even if they are never rendered as
293 * sRGB. For those, we want CCS_E for when sRGBEncode is false. When the
294 * surface is used as sRGB, we fall back to CCS_D.
296 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
297 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
298 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
302 * Determine depth format corresponding to a depth+stencil format,
303 * for separate stencil.
306 intel_depth_format_for_depthstencil_format(mesa_format format
) {
308 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
309 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
310 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
311 return MESA_FORMAT_Z_FLOAT32
;
318 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
319 unsigned depth0
, struct intel_mipmap_level
*table
)
321 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
323 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
325 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
326 if (!table
[level
].slice
)
333 for (unsigned level
= first_level
; level
<= last_level
; level
++)
334 free(table
[level
].slice
);
340 needs_separate_stencil(const struct brw_context
*brw
,
341 struct intel_mipmap_tree
*mt
,
344 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
346 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
349 if (devinfo
->must_use_separate_stencil
)
352 return brw
->has_separate_stencil
&&
353 intel_miptree_supports_hiz(brw
, mt
);
357 * Choose the aux usage for this miptree. This function must be called fairly
358 * late in the miptree create process after we have a tiling.
361 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
362 struct intel_mipmap_tree
*mt
)
364 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
366 if (intel_miptree_supports_mcs(brw
, mt
)) {
367 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
368 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
369 } else if (intel_tiling_supports_ccs(brw
, mt
->surf
.tiling
) &&
370 intel_miptree_supports_ccs(brw
, mt
)) {
371 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
372 intel_miptree_supports_ccs_e(brw
, mt
)) {
373 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
375 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
377 } else if (intel_tiling_supports_hiz(brw
, mt
->surf
.tiling
) &&
378 intel_miptree_supports_hiz(brw
, mt
)) {
379 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
382 /* We can do fast-clear on all auxiliary surface types that are
383 * allocated through the normal texture creation paths.
385 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
386 mt
->supports_fast_clear
= true;
391 * Choose an appropriate uncompressed format for a requested
392 * compressed format, if unsupported.
395 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
397 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
399 /* No need to lower ETC formats on these platforms,
400 * they are supported natively.
402 if (devinfo
->gen
>= 8 || devinfo
->is_baytrail
)
406 case MESA_FORMAT_ETC1_RGB8
:
407 return MESA_FORMAT_R8G8B8X8_UNORM
;
408 case MESA_FORMAT_ETC2_RGB8
:
409 return MESA_FORMAT_R8G8B8X8_UNORM
;
410 case MESA_FORMAT_ETC2_SRGB8
:
411 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
412 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
413 return MESA_FORMAT_B8G8R8A8_SRGB
;
414 case MESA_FORMAT_ETC2_RGBA8_EAC
:
415 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
416 return MESA_FORMAT_R8G8B8A8_UNORM
;
417 case MESA_FORMAT_ETC2_R11_EAC
:
418 return MESA_FORMAT_R_UNORM16
;
419 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
420 return MESA_FORMAT_R_SNORM16
;
421 case MESA_FORMAT_ETC2_RG11_EAC
:
422 return MESA_FORMAT_R16G16_UNORM
;
423 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
424 return MESA_FORMAT_R16G16_SNORM
;
426 /* Non ETC1 / ETC2 format */
432 brw_get_num_logical_layers(const struct intel_mipmap_tree
*mt
, unsigned level
)
434 if (mt
->surf
.dim
== ISL_SURF_DIM_3D
)
435 return minify(mt
->surf
.logical_level0_px
.depth
, level
);
437 return mt
->surf
.logical_level0_px
.array_len
;
440 UNUSED
static unsigned
441 get_num_phys_layers(const struct isl_surf
*surf
, unsigned level
)
443 /* In case of physical dimensions one needs to consider also the layout.
444 * See isl_calc_phys_level0_extent_sa().
446 if (surf
->dim
!= ISL_SURF_DIM_3D
)
447 return surf
->phys_level0_sa
.array_len
;
449 if (surf
->dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
)
450 return minify(surf
->phys_level0_sa
.array_len
, level
);
452 return minify(surf
->phys_level0_sa
.depth
, level
);
455 /** \brief Assert that the level and layer are valid for the miptree. */
457 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
465 assert(level
>= mt
->first_level
);
466 assert(level
<= mt
->last_level
);
467 assert(layer
< get_num_phys_layers(&mt
->surf
, level
));
470 static enum isl_aux_state
**
471 create_aux_state_map(struct intel_mipmap_tree
*mt
,
472 enum isl_aux_state initial
)
474 const uint32_t levels
= mt
->last_level
+ 1;
476 uint32_t total_slices
= 0;
477 for (uint32_t level
= 0; level
< levels
; level
++)
478 total_slices
+= brw_get_num_logical_layers(mt
, level
);
480 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
482 /* We're going to allocate a single chunk of data for both the per-level
483 * reference array and the arrays of aux_state. This makes cleanup
484 * significantly easier.
486 const size_t total_size
= per_level_array_size
+
487 total_slices
* sizeof(enum isl_aux_state
);
488 void *data
= malloc(total_size
);
492 enum isl_aux_state
**per_level_arr
= data
;
493 enum isl_aux_state
*s
= data
+ per_level_array_size
;
494 for (uint32_t level
= 0; level
< levels
; level
++) {
495 per_level_arr
[level
] = s
;
496 const unsigned level_layers
= brw_get_num_logical_layers(mt
, level
);
497 for (uint32_t a
= 0; a
< level_layers
; a
++)
500 assert((void *)s
== data
+ total_size
);
502 return per_level_arr
;
506 free_aux_state_map(enum isl_aux_state
**state
)
512 need_to_retile_as_linear(struct brw_context
*brw
, unsigned row_pitch
,
513 enum isl_tiling tiling
, unsigned samples
)
518 if (tiling
== ISL_TILING_LINEAR
)
521 /* If the width is much smaller than a tile, don't bother tiling. */
525 if (ALIGN(row_pitch
, 512) >= 32768) {
526 perf_debug("row pitch %u too large to blit, falling back to untiled",
535 need_to_retile_as_x(const struct brw_context
*brw
, uint64_t size
,
536 enum isl_tiling tiling
)
538 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
540 /* If the BO is too large to fit in the aperture, we need to use the
541 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
542 * handle Y-tiling, so we need to fall back to X.
544 if (devinfo
->gen
< 6 && size
>= brw
->max_gtt_map_object_size
&&
545 tiling
== ISL_TILING_Y0
)
551 static struct intel_mipmap_tree
*
552 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
553 unsigned first_level
, unsigned last_level
,
554 unsigned width0
, unsigned height0
, unsigned depth0
,
555 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
556 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
557 unsigned row_pitch
, struct brw_bo
*bo
)
559 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
563 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
571 if (target
== GL_TEXTURE_CUBE_MAP
||
572 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
573 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
575 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
577 _mesa_enum_to_string(target
),
578 _mesa_get_format_name(format
),
579 num_samples
, width0
, height0
, depth0
,
580 first_level
, last_level
, mt
);
582 struct isl_surf_init_info init_info
= {
583 .dim
= get_isl_surf_dim(target
),
584 .format
= translate_tex_format(brw
, format
, false),
587 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
588 .levels
= last_level
- first_level
+ 1,
589 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
590 .samples
= num_samples
,
591 .row_pitch
= row_pitch
,
592 .usage
= isl_usage_flags
,
593 .tiling_flags
= tiling_flags
,
596 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
599 /* Depth surfaces are always Y-tiled and stencil is always W-tiled, although
600 * on gen7 platforms we also need to create Y-tiled copies of stencil for
601 * texturing since the hardware can't sample from W-tiled surfaces. For
602 * everything else, check for corner cases needing special treatment.
604 bool is_depth_stencil
=
605 mt
->surf
.usage
& (ISL_SURF_USAGE_STENCIL_BIT
| ISL_SURF_USAGE_DEPTH_BIT
);
606 if (!is_depth_stencil
) {
607 if (need_to_retile_as_linear(brw
, mt
->surf
.row_pitch
,
608 mt
->surf
.tiling
, mt
->surf
.samples
)) {
609 init_info
.tiling_flags
= 1u << ISL_TILING_LINEAR
;
610 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
612 } else if (need_to_retile_as_x(brw
, mt
->surf
.size
, mt
->surf
.tiling
)) {
613 init_info
.tiling_flags
= 1u << ISL_TILING_X
;
614 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
619 /* In case of linear the buffer gets padded by fixed 64 bytes and therefore
620 * the size may not be multiple of row_pitch.
621 * See isl_apply_surface_padding().
623 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
)
624 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
627 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
629 isl_tiling_to_i915_tiling(
631 mt
->surf
.row_pitch
, alloc_flags
);
638 mt
->first_level
= first_level
;
639 mt
->last_level
= last_level
;
642 mt
->aux_state
= NULL
;
643 mt
->cpp
= isl_format_get_layout(mt
->surf
.format
)->bpb
/ 8;
644 mt
->compressed
= _mesa_is_format_compressed(format
);
645 mt
->drm_modifier
= DRM_FORMAT_MOD_INVALID
;
650 intel_miptree_release(&mt
);
655 make_separate_stencil_surface(struct brw_context
*brw
,
656 struct intel_mipmap_tree
*mt
)
658 mt
->stencil_mt
= make_surface(brw
, mt
->target
, MESA_FORMAT_S_UINT8
,
659 0, mt
->surf
.levels
- 1,
660 mt
->surf
.logical_level0_px
.width
,
661 mt
->surf
.logical_level0_px
.height
,
662 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
663 mt
->surf
.logical_level0_px
.depth
:
664 mt
->surf
.logical_level0_px
.array_len
,
665 mt
->surf
.samples
, ISL_TILING_W_BIT
,
666 ISL_SURF_USAGE_STENCIL_BIT
|
667 ISL_SURF_USAGE_TEXTURE_BIT
,
668 BO_ALLOC_BUSY
, 0, NULL
);
673 mt
->stencil_mt
->r8stencil_needs_update
= true;
678 static struct intel_mipmap_tree
*
679 miptree_create(struct brw_context
*brw
,
688 enum intel_miptree_create_flags flags
)
690 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
692 if (format
== MESA_FORMAT_S_UINT8
)
693 return make_surface(brw
, target
, format
, first_level
, last_level
,
694 width0
, height0
, depth0
, num_samples
,
696 ISL_SURF_USAGE_STENCIL_BIT
|
697 ISL_SURF_USAGE_TEXTURE_BIT
,
702 const GLenum base_format
= _mesa_get_format_base_format(format
);
703 if ((base_format
== GL_DEPTH_COMPONENT
||
704 base_format
== GL_DEPTH_STENCIL
) &&
705 !(flags
& MIPTREE_CREATE_LINEAR
)) {
706 /* Fix up the Z miptree format for how we're splitting out separate
707 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
709 const mesa_format depth_only_format
=
710 intel_depth_format_for_depthstencil_format(format
);
711 struct intel_mipmap_tree
*mt
= make_surface(
712 brw
, target
, devinfo
->gen
>= 6 ? depth_only_format
: format
,
713 first_level
, last_level
,
714 width0
, height0
, depth0
, num_samples
, ISL_TILING_Y0_BIT
,
715 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
716 BO_ALLOC_BUSY
, 0, NULL
);
718 if (needs_separate_stencil(brw
, mt
, format
) &&
719 !make_separate_stencil_surface(brw
, mt
)) {
720 intel_miptree_release(&mt
);
724 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
725 intel_miptree_choose_aux_usage(brw
, mt
);
730 mesa_format tex_format
= format
;
731 mesa_format etc_format
= MESA_FORMAT_NONE
;
732 uint32_t alloc_flags
= 0;
734 format
= intel_lower_compressed_format(brw
, format
);
736 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
738 if (flags
& MIPTREE_CREATE_BUSY
)
739 alloc_flags
|= BO_ALLOC_BUSY
;
741 isl_tiling_flags_t tiling_flags
= (flags
& MIPTREE_CREATE_LINEAR
) ?
742 ISL_TILING_LINEAR_BIT
: ISL_TILING_ANY_MASK
;
744 /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
745 if (devinfo
->gen
< 6)
746 tiling_flags
&= ~ISL_TILING_Y0_BIT
;
748 struct intel_mipmap_tree
*mt
= make_surface(
750 first_level
, last_level
,
751 width0
, height0
, depth0
,
752 num_samples
, tiling_flags
,
753 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
754 ISL_SURF_USAGE_TEXTURE_BIT
,
755 alloc_flags
, 0, NULL
);
759 mt
->etc_format
= etc_format
;
761 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
762 intel_miptree_choose_aux_usage(brw
, mt
);
767 struct intel_mipmap_tree
*
768 intel_miptree_create(struct brw_context
*brw
,
777 enum intel_miptree_create_flags flags
)
779 assert(num_samples
> 0);
781 struct intel_mipmap_tree
*mt
= miptree_create(
783 first_level
, last_level
,
784 width0
, height0
, depth0
, num_samples
,
791 if (!intel_miptree_alloc_aux(brw
, mt
)) {
792 intel_miptree_release(&mt
);
799 struct intel_mipmap_tree
*
800 intel_miptree_create_for_bo(struct brw_context
*brw
,
808 enum isl_tiling tiling
,
809 enum intel_miptree_create_flags flags
)
811 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
812 struct intel_mipmap_tree
*mt
;
813 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
814 const GLenum base_format
= _mesa_get_format_base_format(format
);
816 if ((base_format
== GL_DEPTH_COMPONENT
||
817 base_format
== GL_DEPTH_STENCIL
)) {
818 const mesa_format depth_only_format
=
819 intel_depth_format_for_depthstencil_format(format
);
820 mt
= make_surface(brw
, target
,
821 devinfo
->gen
>= 6 ? depth_only_format
: format
,
822 0, 0, width
, height
, depth
, 1, ISL_TILING_Y0_BIT
,
823 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
828 brw_bo_reference(bo
);
830 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
831 intel_miptree_choose_aux_usage(brw
, mt
);
834 } else if (format
== MESA_FORMAT_S_UINT8
) {
835 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
836 0, 0, width
, height
, depth
, 1,
838 ISL_SURF_USAGE_STENCIL_BIT
|
839 ISL_SURF_USAGE_TEXTURE_BIT
,
844 assert(bo
->size
>= mt
->surf
.size
);
846 brw_bo_reference(bo
);
850 /* Nothing will be able to use this miptree with the BO if the offset isn't
853 if (tiling
!= ISL_TILING_LINEAR
)
854 assert(offset
% 4096 == 0);
856 /* miptrees can't handle negative pitch. If you need flipping of images,
857 * that's outside of the scope of the mt.
861 /* The BO already has a tiling format and we shouldn't confuse the lower
862 * layers by making it try to find a tiling format again.
864 assert((flags
& MIPTREE_CREATE_LINEAR
) == 0);
866 mt
= make_surface(brw
, target
, format
,
867 0, 0, width
, height
, depth
, 1,
869 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
870 ISL_SURF_USAGE_TEXTURE_BIT
,
875 brw_bo_reference(bo
);
879 if (!(flags
& MIPTREE_CREATE_NO_AUX
)) {
880 intel_miptree_choose_aux_usage(brw
, mt
);
882 if (!intel_miptree_alloc_aux(brw
, mt
)) {
883 intel_miptree_release(&mt
);
891 static struct intel_mipmap_tree
*
892 miptree_create_for_planar_image(struct brw_context
*brw
,
893 __DRIimage
*image
, GLenum target
,
894 enum isl_tiling tiling
)
896 const struct intel_image_format
*f
= image
->planar_format
;
897 struct intel_mipmap_tree
*planar_mt
= NULL
;
899 for (int i
= 0; i
< f
->nplanes
; i
++) {
900 const int index
= f
->planes
[i
].buffer_index
;
901 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
902 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
903 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
904 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
906 /* Disable creation of the texture's aux buffers because the driver
907 * exposes no EGL API to manage them. That is, there is no API for
908 * resolving the aux buffer's content to the main buffer nor for
909 * invalidating the aux buffer's content.
911 struct intel_mipmap_tree
*mt
=
912 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
913 image
->offsets
[index
],
915 image
->strides
[index
],
917 MIPTREE_CREATE_NO_AUX
);
926 planar_mt
->plane
[i
- 1] = mt
;
929 planar_mt
->drm_modifier
= image
->modifier
;
935 create_ccs_buf_for_image(struct brw_context
*brw
,
937 struct intel_mipmap_tree
*mt
,
938 enum isl_aux_state initial_state
)
940 struct isl_surf temp_ccs_surf
;
942 /* CCS is only supported for very simple miptrees */
943 assert(image
->aux_offset
!= 0 && image
->aux_pitch
!= 0);
944 assert(image
->tile_x
== 0 && image
->tile_y
== 0);
945 assert(mt
->surf
.samples
== 1);
946 assert(mt
->surf
.levels
== 1);
947 assert(mt
->surf
.logical_level0_px
.depth
== 1);
948 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
949 assert(mt
->first_level
== 0);
950 assert(mt
->last_level
== 0);
952 /* We shouldn't already have a CCS */
953 assert(!mt
->aux_buf
);
955 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
,
959 assert(image
->aux_offset
< image
->bo
->size
);
960 assert(temp_ccs_surf
.size
<= image
->bo
->size
- image
->aux_offset
);
962 mt
->aux_buf
= calloc(sizeof(*mt
->aux_buf
), 1);
963 if (mt
->aux_buf
== NULL
)
966 mt
->aux_state
= create_aux_state_map(mt
, initial_state
);
967 if (!mt
->aux_state
) {
973 /* On gen10+ we start using an extra space in the aux buffer to store the
974 * indirect clear color. However, if we imported an image from the window
975 * system with CCS, we don't have the extra space at the end of the aux
976 * buffer. So create a new bo here that will store that clear color.
978 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
979 if (devinfo
->gen
>= 10) {
980 mt
->aux_buf
->clear_color_bo
=
981 brw_bo_alloc(brw
->bufmgr
, "clear_color_bo",
982 brw
->isl_dev
.ss
.clear_color_state_size
);
983 if (!mt
->aux_buf
->clear_color_bo
) {
990 mt
->aux_buf
->bo
= image
->bo
;
991 brw_bo_reference(image
->bo
);
993 mt
->aux_buf
->offset
= image
->aux_offset
;
994 mt
->aux_buf
->size
= image
->bo
->size
- image
->aux_offset
;
995 mt
->aux_buf
->pitch
= image
->aux_pitch
;
996 mt
->aux_buf
->qpitch
= 0;
997 mt
->aux_buf
->surf
= temp_ccs_surf
;
1002 struct intel_mipmap_tree
*
1003 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
1004 __DRIimage
*image
, GLenum target
,
1006 bool is_winsys_image
)
1008 uint32_t bo_tiling
, bo_swizzle
;
1009 brw_bo_get_tiling(image
->bo
, &bo_tiling
, &bo_swizzle
);
1011 const struct isl_drm_modifier_info
*mod_info
=
1012 isl_drm_modifier_get_info(image
->modifier
);
1014 const enum isl_tiling tiling
=
1015 mod_info
? mod_info
->tiling
: isl_tiling_from_i915_tiling(bo_tiling
);
1017 if (image
->planar_format
&& image
->planar_format
->nplanes
> 1)
1018 return miptree_create_for_planar_image(brw
, image
, target
, tiling
);
1020 if (image
->planar_format
)
1021 assert(image
->planar_format
->planes
[0].dri_format
== image
->dri_format
);
1023 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
1024 /* The texture storage paths in core Mesa detect if the driver does not
1025 * support the user-requested format, and then searches for a
1026 * fallback format. The DRIimage code bypasses core Mesa, though. So we
1027 * do the fallbacks here for important formats.
1029 * We must support DRM_FOURCC_XBGR8888 textures because the Android
1030 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
1031 * the Chrome OS compositor consumes as dma_buf EGLImages.
1033 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1036 if (!brw
->ctx
.TextureFormatSupported
[format
])
1039 enum intel_miptree_create_flags mt_create_flags
= 0;
1041 /* If this image comes in from a window system, we have different
1042 * requirements than if it comes in via an EGL import operation. Window
1043 * system images can use any form of auxiliary compression we wish because
1044 * they get "flushed" before being handed off to the window system and we
1045 * have the opportunity to do resolves. Non window-system images, on the
1046 * other hand, have no resolve point so we can't have aux without a
1049 if (!is_winsys_image
)
1050 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1052 /* If we have a modifier which specifies aux, don't create one yet */
1053 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)
1054 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1056 /* Disable creation of the texture's aux buffers because the driver exposes
1057 * no EGL API to manage them. That is, there is no API for resolving the aux
1058 * buffer's content to the main buffer nor for invalidating the aux buffer's
1061 struct intel_mipmap_tree
*mt
=
1062 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1063 image
->offset
, image
->width
, image
->height
, 1,
1064 image
->pitch
, tiling
, mt_create_flags
);
1068 mt
->target
= target
;
1069 mt
->level
[0].level_x
= image
->tile_x
;
1070 mt
->level
[0].level_y
= image
->tile_y
;
1071 mt
->drm_modifier
= image
->modifier
;
1073 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1074 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1075 * trouble resolving back to destination image due to alignment issues.
1077 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1078 if (!devinfo
->has_surface_tile_offset
) {
1079 uint32_t draw_x
, draw_y
;
1080 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1082 if (draw_x
!= 0 || draw_y
!= 0) {
1083 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1084 intel_miptree_release(&mt
);
1089 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
1090 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
1092 mt
->aux_usage
= mod_info
->aux_usage
;
1093 /* If we are a window system buffer, then we can support fast-clears
1094 * even if the modifier doesn't support them by doing a partial resolve
1095 * as part of the flush operation.
1097 mt
->supports_fast_clear
=
1098 is_winsys_image
|| mod_info
->supports_clear_color
;
1100 /* We don't know the actual state of the surface when we get it but we
1101 * can make a pretty good guess based on the modifier. What we do know
1102 * for sure is that it isn't in the AUX_INVALID state, so we just assume
1103 * a worst case of compression.
1105 enum isl_aux_state initial_state
=
1106 isl_drm_modifier_get_default_aux_state(image
->modifier
);
1108 if (!create_ccs_buf_for_image(brw
, image
, mt
, initial_state
)) {
1109 intel_miptree_release(&mt
);
1114 /* Don't assume coherency for imported EGLimages. We don't know what
1115 * external clients are going to do with it. They may scan it out.
1117 image
->bo
->cache_coherent
= false;
1123 * For a singlesample renderbuffer, this simply wraps the given BO with a
1126 * For a multisample renderbuffer, this wraps the window system's
1127 * (singlesample) BO with a singlesample miptree attached to the
1128 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1129 * that will contain the actual rendering (which is lazily resolved to
1130 * irb->singlesample_mt).
1133 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1134 struct intel_renderbuffer
*irb
,
1135 struct intel_mipmap_tree
*singlesample_mt
,
1136 uint32_t width
, uint32_t height
,
1139 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1140 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1141 mesa_format format
= rb
->Format
;
1142 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1144 /* Only the front and back buffers, which are color buffers, are allocated
1145 * through the image loader.
1147 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1148 _mesa_get_format_base_format(format
) == GL_RGBA
);
1150 assert(singlesample_mt
);
1152 if (num_samples
== 1) {
1153 intel_miptree_release(&irb
->mt
);
1154 irb
->mt
= singlesample_mt
;
1156 assert(!irb
->singlesample_mt
);
1158 intel_miptree_release(&irb
->singlesample_mt
);
1159 irb
->singlesample_mt
= singlesample_mt
;
1162 irb
->mt
->surf
.logical_level0_px
.width
!= width
||
1163 irb
->mt
->surf
.logical_level0_px
.height
!= height
) {
1164 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1169 if (!multisample_mt
)
1172 irb
->need_downsample
= false;
1173 intel_miptree_release(&irb
->mt
);
1174 irb
->mt
= multisample_mt
;
1180 intel_miptree_release(&irb
->mt
);
1184 struct intel_mipmap_tree
*
1185 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1189 uint32_t num_samples
)
1191 struct intel_mipmap_tree
*mt
;
1193 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1195 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1196 width
, height
, depth
, num_samples
,
1197 MIPTREE_CREATE_BUSY
);
1204 intel_miptree_release(&mt
);
1209 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1210 struct intel_mipmap_tree
*src
)
1215 intel_miptree_release(dst
);
1219 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1226 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1228 if (aux_buf
== NULL
)
1231 brw_bo_unreference(aux_buf
->bo
);
1232 brw_bo_unreference(aux_buf
->clear_color_bo
);
1238 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1243 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1244 if (--(*mt
)->refcount
<= 0) {
1247 DBG("%s deleting %p\n", __func__
, *mt
);
1249 brw_bo_unreference((*mt
)->bo
);
1250 intel_miptree_release(&(*mt
)->stencil_mt
);
1251 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1252 intel_miptree_aux_buffer_free((*mt
)->aux_buf
);
1253 free_aux_state_map((*mt
)->aux_state
);
1255 intel_miptree_release(&(*mt
)->plane
[0]);
1256 intel_miptree_release(&(*mt
)->plane
[1]);
1258 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1259 free((*mt
)->level
[i
].slice
);
1269 intel_get_image_dims(struct gl_texture_image
*image
,
1270 int *width
, int *height
, int *depth
)
1272 switch (image
->TexObject
->Target
) {
1273 case GL_TEXTURE_1D_ARRAY
:
1274 /* For a 1D Array texture the OpenGL API will treat the image height as
1275 * the number of array slices. For Intel hardware, we treat the 1D array
1276 * as a 2D Array with a height of 1. So, here we want to swap image
1279 assert(image
->Depth
== 1);
1280 *width
= image
->Width
;
1282 *depth
= image
->Height
;
1284 case GL_TEXTURE_CUBE_MAP
:
1285 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1286 * though we really have 6 slices.
1288 assert(image
->Depth
== 1);
1289 *width
= image
->Width
;
1290 *height
= image
->Height
;
1294 *width
= image
->Width
;
1295 *height
= image
->Height
;
1296 *depth
= image
->Depth
;
1302 * Can the image be pulled into a unified mipmap tree? This mirrors
1303 * the completeness test in a lot of ways.
1305 * Not sure whether I want to pass gl_texture_image here.
1308 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1309 struct gl_texture_image
*image
)
1311 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1312 GLuint level
= intelImage
->base
.Base
.Level
;
1313 int width
, height
, depth
;
1315 /* glTexImage* choose the texture object based on the target passed in, and
1316 * objects can't change targets over their lifetimes, so this should be
1319 assert(image
->TexObject
->Target
== mt
->target
);
1321 mesa_format mt_format
= mt
->format
;
1322 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1323 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1324 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1325 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1326 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1327 mt_format
= mt
->etc_format
;
1329 if (_mesa_get_srgb_format_linear(image
->TexFormat
) !=
1330 _mesa_get_srgb_format_linear(mt_format
))
1333 intel_get_image_dims(image
, &width
, &height
, &depth
);
1335 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1338 if (level
>= mt
->surf
.levels
)
1341 const unsigned level_depth
=
1342 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1343 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1344 mt
->surf
.logical_level0_px
.array_len
;
1346 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1347 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1348 depth
== level_depth
&&
1349 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1353 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1354 GLuint level
, GLuint slice
,
1355 GLuint
*x
, GLuint
*y
)
1357 if (level
== 0 && slice
== 0) {
1358 *x
= mt
->level
[0].level_x
;
1359 *y
= mt
->level
[0].level_y
;
1363 uint32_t x_offset_sa
, y_offset_sa
;
1365 /* Miptree itself can have an offset only if it represents a single
1366 * slice in an imported buffer object.
1367 * See intel_miptree_create_for_dri_image().
1369 assert(mt
->level
[0].level_x
== 0);
1370 assert(mt
->level
[0].level_y
== 0);
1372 /* Given level is relative to level zero while the miptree may be
1373 * represent just a subset of all levels starting from 'first_level'.
1375 assert(level
>= mt
->first_level
);
1376 level
-= mt
->first_level
;
1378 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1379 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1380 isl_surf_get_image_offset_el(&mt
->surf
, level
, slice
, z
,
1381 &x_offset_sa
, &y_offset_sa
);
1389 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1390 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1391 * and tile_h is set to 1.
1394 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1395 uint32_t *tile_w
, uint32_t *tile_h
)
1406 case ISL_TILING_LINEAR
:
1411 unreachable("not reached");
1417 * This function computes masks that may be used to select the bits of the X
1418 * and Y coordinates that indicate the offset within a tile. If the BO is
1419 * untiled, the masks are set to 0.
1422 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1423 uint32_t *mask_x
, uint32_t *mask_y
)
1425 uint32_t tile_w_bytes
, tile_h
;
1427 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1429 *mask_x
= tile_w_bytes
/ cpp
- 1;
1430 *mask_y
= tile_h
- 1;
1434 * Compute the offset (in bytes) from the start of the BO to the given x
1435 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1436 * multiples of the tile size.
1439 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1440 uint32_t x
, uint32_t y
)
1443 uint32_t pitch
= mt
->surf
.row_pitch
;
1445 switch (mt
->surf
.tiling
) {
1447 unreachable("not reached");
1448 case ISL_TILING_LINEAR
:
1449 return y
* pitch
+ x
* cpp
;
1451 assert((x
% (512 / cpp
)) == 0);
1452 assert((y
% 8) == 0);
1453 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1455 assert((x
% (128 / cpp
)) == 0);
1456 assert((y
% 32) == 0);
1457 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1462 * Rendering with tiled buffers requires that the base address of the buffer
1463 * be aligned to a page boundary. For renderbuffers, and sometimes with
1464 * textures, we may want the surface to point at a texture image level that
1465 * isn't at a page boundary.
1467 * This function returns an appropriately-aligned base offset
1468 * according to the tiling restrictions, plus any required x/y offset
1472 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1473 GLuint level
, GLuint slice
,
1478 uint32_t mask_x
, mask_y
;
1480 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1481 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1483 *tile_x
= x
& mask_x
;
1484 *tile_y
= y
& mask_y
;
1486 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1490 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1491 struct intel_mipmap_tree
*src_mt
,
1492 unsigned src_level
, unsigned src_layer
,
1493 struct intel_mipmap_tree
*dst_mt
,
1494 unsigned dst_level
, unsigned dst_layer
,
1495 unsigned width
, unsigned height
)
1498 ptrdiff_t src_stride
, dst_stride
;
1499 const unsigned cpp
= (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8);
1501 intel_miptree_map(brw
, src_mt
,
1502 src_level
, src_layer
,
1505 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1508 intel_miptree_map(brw
, dst_mt
,
1509 dst_level
, dst_layer
,
1512 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1516 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1517 _mesa_get_format_name(src_mt
->format
),
1518 src_mt
, src
, src_stride
,
1519 _mesa_get_format_name(dst_mt
->format
),
1520 dst_mt
, dst
, dst_stride
,
1523 int row_size
= cpp
* width
;
1524 if (src_stride
== row_size
&&
1525 dst_stride
== row_size
) {
1526 memcpy(dst
, src
, row_size
* height
);
1528 for (int i
= 0; i
< height
; i
++) {
1529 memcpy(dst
, src
, row_size
);
1535 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1536 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1538 /* Don't forget to copy the stencil data over, too. We could have skipped
1539 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1540 * shuffling the two data sources in/out of temporary storage instead of
1541 * the direct mapping we get this way.
1543 if (dst_mt
->stencil_mt
) {
1544 assert(src_mt
->stencil_mt
);
1545 intel_miptree_copy_slice_sw(brw
,
1546 src_mt
->stencil_mt
, src_level
, src_layer
,
1547 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1553 intel_miptree_copy_slice(struct brw_context
*brw
,
1554 struct intel_mipmap_tree
*src_mt
,
1555 unsigned src_level
, unsigned src_layer
,
1556 struct intel_mipmap_tree
*dst_mt
,
1557 unsigned dst_level
, unsigned dst_layer
)
1560 mesa_format format
= src_mt
->format
;
1561 unsigned width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1562 src_level
- src_mt
->first_level
);
1563 unsigned height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1564 src_level
- src_mt
->first_level
);
1566 assert(src_layer
< get_num_phys_layers(&src_mt
->surf
,
1567 src_level
- src_mt
->first_level
));
1569 assert(_mesa_get_srgb_format_linear(src_mt
->format
) ==
1570 _mesa_get_srgb_format_linear(dst_mt
->format
));
1572 if (dst_mt
->compressed
) {
1574 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1575 height
= ALIGN_NPOT(height
, j
) / j
;
1576 width
= ALIGN_NPOT(width
, i
) / i
;
1579 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1580 * below won't apply since we can't do the depth's Y tiling or the
1581 * stencil's W tiling in the blitter.
1583 if (src_mt
->stencil_mt
) {
1584 intel_miptree_copy_slice_sw(brw
,
1585 src_mt
, src_level
, src_layer
,
1586 dst_mt
, dst_level
, dst_layer
,
1591 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1592 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1594 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1597 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1598 _mesa_get_format_name(src_mt
->format
),
1599 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch
,
1600 _mesa_get_format_name(dst_mt
->format
),
1601 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch
,
1604 if (!intel_miptree_blit(brw
,
1605 src_mt
, src_level
, src_layer
, 0, 0, false,
1606 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1607 width
, height
, COLOR_LOGICOP_COPY
)) {
1608 perf_debug("miptree validate blit for %s failed\n",
1609 _mesa_get_format_name(format
));
1611 intel_miptree_copy_slice_sw(brw
,
1612 src_mt
, src_level
, src_layer
,
1613 dst_mt
, dst_level
, dst_layer
,
1619 * Copies the image's current data to the given miptree, and associates that
1620 * miptree with the image.
1623 intel_miptree_copy_teximage(struct brw_context
*brw
,
1624 struct intel_texture_image
*intelImage
,
1625 struct intel_mipmap_tree
*dst_mt
)
1627 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1628 struct intel_texture_object
*intel_obj
=
1629 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1630 int level
= intelImage
->base
.Base
.Level
;
1631 const unsigned face
= intelImage
->base
.Base
.Face
;
1632 unsigned start_layer
, end_layer
;
1634 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1636 assert(intelImage
->base
.Base
.Height
);
1638 end_layer
= intelImage
->base
.Base
.Height
- 1;
1639 } else if (face
> 0) {
1643 assert(intelImage
->base
.Base
.Depth
);
1645 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1648 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1649 intel_miptree_copy_slice(brw
,
1654 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1655 intel_obj
->needs_validate
= true;
1659 intel_miptree_init_mcs(struct brw_context
*brw
,
1660 struct intel_mipmap_tree
*mt
,
1663 assert(mt
->aux_buf
!= NULL
);
1665 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1667 * When MCS buffer is enabled and bound to MSRT, it is required that it
1668 * is cleared prior to any rendering.
1670 * Since we don't use the MCS buffer for any purpose other than rendering,
1671 * it makes sense to just clear it immediately upon allocation.
1673 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1675 void *map
= brw_bo_map(brw
, mt
->aux_buf
->bo
, MAP_WRITE
| MAP_RAW
);
1676 if (unlikely(map
== NULL
)) {
1677 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1678 brw_bo_unreference(mt
->aux_buf
->bo
);
1683 memset(data
, init_value
, mt
->aux_buf
->size
);
1684 brw_bo_unmap(mt
->aux_buf
->bo
);
1687 static struct intel_miptree_aux_buffer
*
1688 intel_alloc_aux_buffer(struct brw_context
*brw
,
1690 const struct isl_surf
*aux_surf
,
1691 uint32_t alloc_flags
,
1692 struct intel_mipmap_tree
*mt
)
1694 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1698 buf
->size
= aux_surf
->size
;
1700 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1701 if (devinfo
->gen
>= 10) {
1702 /* On CNL, instead of setting the clear color in the SURFACE_STATE, we
1703 * will set a pointer to a dword somewhere that contains the color. So,
1704 * allocate the space for the clear color value here on the aux buffer.
1706 buf
->clear_color_offset
= buf
->size
;
1707 buf
->size
+= brw
->isl_dev
.ss
.clear_color_state_size
;
1710 buf
->pitch
= aux_surf
->row_pitch
;
1711 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1713 /* ISL has stricter set of alignment rules then the drm allocator.
1714 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1715 * trying to recalculate based on different format block sizes.
1717 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1718 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1724 if (devinfo
->gen
>= 10) {
1725 buf
->clear_color_bo
= buf
->bo
;
1726 brw_bo_reference(buf
->clear_color_bo
);
1729 buf
->surf
= *aux_surf
;
1735 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1736 struct intel_mipmap_tree
*mt
,
1739 assert(brw
->screen
->devinfo
.gen
>= 7); /* MCS only used on Gen7+ */
1740 assert(mt
->aux_buf
== NULL
);
1741 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1743 /* Multisampled miptrees are only supported for single level. */
1744 assert(mt
->first_level
== 0);
1745 enum isl_aux_state
**aux_state
=
1746 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1750 struct isl_surf temp_mcs_surf
;
1752 MAYBE_UNUSED
bool ok
=
1753 isl_surf_get_mcs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_mcs_surf
);
1756 /* Buffer needs to be initialised requiring the buffer to be immediately
1757 * mapped to cpu space for writing. Therefore do not use the gpu access
1758 * flag which can cause an unnecessary delay if the backing pages happened
1759 * to be just used by the GPU.
1761 const uint32_t alloc_flags
= 0;
1762 mt
->aux_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1763 &temp_mcs_surf
, alloc_flags
, mt
);
1769 mt
->aux_state
= aux_state
;
1771 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1777 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1778 struct intel_mipmap_tree
*mt
)
1780 assert(mt
->aux_buf
== NULL
);
1781 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1782 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1784 struct isl_surf temp_ccs_surf
;
1786 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
, 0))
1789 assert(temp_ccs_surf
.size
&&
1790 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1792 enum isl_aux_state
**aux_state
=
1793 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1797 /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
1798 * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
1800 * "If Software wants to enable Color Compression without Fast clear,
1801 * Software needs to initialize MCS with zeros."
1803 * A CCS value of 0 indicates that the corresponding block is in the
1804 * pass-through state which is what we want.
1806 * For CCS_D, on the other hand, we don't care as we're about to perform a
1807 * fast-clear operation. In that case, being hot in caches more useful.
1809 const uint32_t alloc_flags
= mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
?
1810 BO_ALLOC_ZEROED
: BO_ALLOC_BUSY
;
1811 mt
->aux_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
1812 &temp_ccs_surf
, alloc_flags
, mt
);
1818 mt
->aux_state
= aux_state
;
1824 * Helper for intel_miptree_alloc_hiz() that sets
1825 * \c mt->level[level].has_hiz. Return true if and only if
1826 * \c has_hiz was set.
1829 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1830 struct intel_mipmap_tree
*mt
,
1833 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1835 assert(mt
->aux_buf
);
1836 assert(mt
->surf
.size
> 0);
1838 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
1839 uint32_t width
= minify(mt
->surf
.phys_level0_sa
.width
, level
);
1840 uint32_t height
= minify(mt
->surf
.phys_level0_sa
.height
, level
);
1842 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1843 * and the height is 4 aligned. This allows our HiZ support
1844 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1845 * we can grow the width & height to allow the HiZ op to
1846 * force the proper size alignments.
1848 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1849 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1854 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1855 mt
->level
[level
].has_hiz
= true;
1860 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1861 struct intel_mipmap_tree
*mt
)
1863 assert(mt
->aux_buf
== NULL
);
1864 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
1866 enum isl_aux_state
**aux_state
=
1867 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1871 struct isl_surf temp_hiz_surf
;
1873 MAYBE_UNUSED
bool ok
=
1874 isl_surf_get_hiz_surf(&brw
->isl_dev
, &mt
->surf
, &temp_hiz_surf
);
1877 const uint32_t alloc_flags
= BO_ALLOC_BUSY
;
1878 mt
->aux_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
1879 &temp_hiz_surf
, alloc_flags
, mt
);
1886 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1887 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1889 mt
->aux_state
= aux_state
;
1896 * Allocate the initial aux surface for a miptree based on mt->aux_usage
1898 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
1899 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
1900 * compress clear color so we wait until an actual fast-clear to allocate it.
1903 intel_miptree_alloc_aux(struct brw_context
*brw
,
1904 struct intel_mipmap_tree
*mt
)
1906 switch (mt
->aux_usage
) {
1907 case ISL_AUX_USAGE_NONE
:
1910 case ISL_AUX_USAGE_HIZ
:
1911 assert(!_mesa_is_format_color_format(mt
->format
));
1912 if (!intel_miptree_alloc_hiz(brw
, mt
))
1916 case ISL_AUX_USAGE_MCS
:
1917 assert(_mesa_is_format_color_format(mt
->format
));
1918 assert(mt
->surf
.samples
> 1);
1919 if (!intel_miptree_alloc_mcs(brw
, mt
, mt
->surf
.samples
))
1923 case ISL_AUX_USAGE_CCS_D
:
1924 /* Since CCS_D can only compress clear color so we wait until an actual
1925 * fast-clear to allocate it.
1929 case ISL_AUX_USAGE_CCS_E
:
1930 assert(_mesa_is_format_color_format(mt
->format
));
1931 assert(mt
->surf
.samples
== 1);
1932 if (!intel_miptree_alloc_ccs(brw
, mt
))
1937 unreachable("Invalid aux usage");
1942 * Can the miptree sample using the hiz buffer?
1945 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1946 struct intel_mipmap_tree
*mt
)
1948 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1950 if (!devinfo
->has_sample_with_hiz
) {
1958 /* It seems the hardware won't fallback to the depth buffer if some of the
1959 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1960 * of the texture to be HiZ enabled.
1962 for (unsigned level
= 0; level
< mt
->surf
.levels
; ++level
) {
1963 if (!intel_miptree_level_has_hiz(mt
, level
))
1967 /* If compressed multisampling is enabled, then we use it for the auxiliary
1970 * From the BDW PRM (Volume 2d: Command Reference: Structures
1971 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1973 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1974 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1976 * There is no such blurb for 1D textures, but there is sufficient evidence
1977 * that this is broken on SKL+.
1979 return (mt
->surf
.samples
== 1 &&
1980 mt
->target
!= GL_TEXTURE_3D
&&
1981 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1985 * Does the miptree slice have hiz enabled?
1988 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
1990 intel_miptree_check_level_layer(mt
, level
, 0);
1991 return mt
->level
[level
].has_hiz
;
1994 static inline uint32_t
1995 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
1996 uint32_t start_level
, uint32_t num_levels
)
1998 assert(start_level
>= mt
->first_level
);
1999 assert(start_level
<= mt
->last_level
);
2001 if (num_levels
== INTEL_REMAINING_LAYERS
)
2002 num_levels
= mt
->last_level
- start_level
+ 1;
2003 /* Check for overflow */
2004 assert(start_level
+ num_levels
>= start_level
);
2005 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
2010 static inline uint32_t
2011 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
2012 uint32_t start_layer
, uint32_t num_layers
)
2014 assert(level
<= mt
->last_level
);
2016 const uint32_t total_num_layers
= brw_get_num_logical_layers(mt
, level
);
2017 assert(start_layer
< total_num_layers
);
2018 if (num_layers
== INTEL_REMAINING_LAYERS
)
2019 num_layers
= total_num_layers
- start_layer
;
2020 /* Check for overflow */
2021 assert(start_layer
+ num_layers
>= start_layer
);
2022 assert(start_layer
+ num_layers
<= total_num_layers
);
2028 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
2029 unsigned start_level
, unsigned num_levels
,
2030 unsigned start_layer
, unsigned num_layers
)
2032 assert(_mesa_is_format_color_format(mt
->format
));
2037 /* Clamp the level range to fit the miptree */
2038 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2040 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2041 const uint32_t level
= start_level
+ l
;
2042 const uint32_t level_layers
=
2043 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2044 for (unsigned a
= 0; a
< level_layers
; a
++) {
2045 enum isl_aux_state aux_state
=
2046 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
2047 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
2048 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2057 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2058 const struct intel_mipmap_tree
*mt
,
2059 unsigned level
, unsigned layer
)
2064 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2065 assert(brw
->screen
->devinfo
.gen
>= 8 ||
2066 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2068 /* Compression of arrayed msaa surfaces is supported. */
2069 if (mt
->surf
.samples
> 1)
2072 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2073 assert(brw
->screen
->devinfo
.gen
>= 8 ||
2075 mt
->surf
.logical_level0_px
.depth
== 1 &&
2076 mt
->surf
.logical_level0_px
.array_len
== 1));
2082 static enum isl_aux_op
2083 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2084 enum isl_aux_usage aux_usage
,
2085 bool fast_clear_supported
)
2087 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
2089 const bool ccs_supported
= aux_usage
== ISL_AUX_USAGE_CCS_D
;
2091 assert(ccs_supported
== fast_clear_supported
);
2093 switch (aux_state
) {
2094 case ISL_AUX_STATE_CLEAR
:
2095 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2097 return ISL_AUX_OP_FULL_RESOLVE
;
2099 return ISL_AUX_OP_NONE
;
2101 case ISL_AUX_STATE_PASS_THROUGH
:
2102 return ISL_AUX_OP_NONE
;
2104 case ISL_AUX_STATE_RESOLVED
:
2105 case ISL_AUX_STATE_AUX_INVALID
:
2106 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2107 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2111 unreachable("Invalid aux state for CCS_D");
2114 static enum isl_aux_op
2115 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2116 enum isl_aux_usage aux_usage
,
2117 bool fast_clear_supported
)
2119 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
2120 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2121 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2122 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2124 if (aux_usage
== ISL_AUX_USAGE_CCS_D
)
2125 assert(fast_clear_supported
);
2127 switch (aux_state
) {
2128 case ISL_AUX_STATE_CLEAR
:
2129 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2130 if (fast_clear_supported
)
2131 return ISL_AUX_OP_NONE
;
2132 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
2133 return ISL_AUX_OP_PARTIAL_RESOLVE
;
2135 return ISL_AUX_OP_FULL_RESOLVE
;
2137 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2138 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2139 return ISL_AUX_OP_FULL_RESOLVE
;
2140 else if (!fast_clear_supported
)
2141 return ISL_AUX_OP_PARTIAL_RESOLVE
;
2143 return ISL_AUX_OP_NONE
;
2145 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2146 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2147 return ISL_AUX_OP_FULL_RESOLVE
;
2149 return ISL_AUX_OP_NONE
;
2151 case ISL_AUX_STATE_PASS_THROUGH
:
2152 return ISL_AUX_OP_NONE
;
2154 case ISL_AUX_STATE_RESOLVED
:
2155 case ISL_AUX_STATE_AUX_INVALID
:
2159 unreachable("Invalid aux state for CCS_E");
2163 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2164 struct intel_mipmap_tree
*mt
,
2165 uint32_t level
, uint32_t layer
,
2166 enum isl_aux_usage aux_usage
,
2167 bool fast_clear_supported
)
2169 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2171 enum isl_aux_op resolve_op
;
2172 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2173 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
2174 fast_clear_supported
);
2176 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2177 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
2178 fast_clear_supported
);
2181 if (resolve_op
!= ISL_AUX_OP_NONE
) {
2182 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2183 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2185 switch (resolve_op
) {
2186 case ISL_AUX_OP_FULL_RESOLVE
:
2187 /* The CCS full resolve operation destroys the CCS and sets it to the
2188 * pass-through state. (You can also think of this as being both a
2189 * resolve and an ambiguate in one operation.)
2191 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2192 ISL_AUX_STATE_PASS_THROUGH
);
2195 case ISL_AUX_OP_PARTIAL_RESOLVE
:
2196 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2197 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2201 unreachable("Invalid resolve op");
2207 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2208 struct intel_mipmap_tree
*mt
,
2209 uint32_t level
, uint32_t layer
,
2210 enum isl_aux_usage aux_usage
)
2212 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2213 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2214 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2216 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2218 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2219 switch (aux_state
) {
2220 case ISL_AUX_STATE_CLEAR
:
2221 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2222 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
2223 aux_usage
== ISL_AUX_USAGE_CCS_D
);
2225 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2226 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2227 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2228 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
2229 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2230 ISL_AUX_STATE_PARTIAL_CLEAR
);
2234 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2235 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2236 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
2237 break; /* Nothing to do */
2239 case ISL_AUX_STATE_PASS_THROUGH
:
2240 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2241 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2242 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2248 case ISL_AUX_STATE_RESOLVED
:
2249 case ISL_AUX_STATE_AUX_INVALID
:
2250 unreachable("Invalid aux state for CCS_E");
2253 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2254 /* CCS_D is a bit simpler */
2255 switch (aux_state
) {
2256 case ISL_AUX_STATE_CLEAR
:
2257 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2258 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2259 ISL_AUX_STATE_PARTIAL_CLEAR
);
2262 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2263 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2264 break; /* Nothing to do */
2266 case ISL_AUX_STATE_PASS_THROUGH
:
2270 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2271 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2272 case ISL_AUX_STATE_RESOLVED
:
2273 case ISL_AUX_STATE_AUX_INVALID
:
2274 unreachable("Invalid aux state for CCS_D");
2280 intel_miptree_prepare_mcs_access(struct brw_context
*brw
,
2281 struct intel_mipmap_tree
*mt
,
2283 enum isl_aux_usage aux_usage
,
2284 bool fast_clear_supported
)
2286 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2288 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2289 case ISL_AUX_STATE_CLEAR
:
2290 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2291 if (!fast_clear_supported
) {
2292 brw_blorp_mcs_partial_resolve(brw
, mt
, layer
, 1);
2293 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2294 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2298 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2299 break; /* Nothing to do */
2301 case ISL_AUX_STATE_RESOLVED
:
2302 case ISL_AUX_STATE_PASS_THROUGH
:
2303 case ISL_AUX_STATE_AUX_INVALID
:
2304 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2305 unreachable("Invalid aux state for MCS");
2310 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2311 struct intel_mipmap_tree
*mt
,
2313 enum isl_aux_usage aux_usage
)
2315 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2317 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2318 case ISL_AUX_STATE_CLEAR
:
2319 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2320 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2323 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2324 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2325 break; /* Nothing to do */
2327 case ISL_AUX_STATE_RESOLVED
:
2328 case ISL_AUX_STATE_PASS_THROUGH
:
2329 case ISL_AUX_STATE_AUX_INVALID
:
2330 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2331 unreachable("Invalid aux state for MCS");
2336 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2337 struct intel_mipmap_tree
*mt
,
2338 uint32_t level
, uint32_t layer
,
2339 enum isl_aux_usage aux_usage
,
2340 bool fast_clear_supported
)
2342 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2344 enum isl_aux_op hiz_op
= ISL_AUX_OP_NONE
;
2345 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2346 case ISL_AUX_STATE_CLEAR
:
2347 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2348 if (aux_usage
!= ISL_AUX_USAGE_HIZ
|| !fast_clear_supported
)
2349 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
2352 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2353 if (aux_usage
!= ISL_AUX_USAGE_HIZ
)
2354 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
2357 case ISL_AUX_STATE_PASS_THROUGH
:
2358 case ISL_AUX_STATE_RESOLVED
:
2361 case ISL_AUX_STATE_AUX_INVALID
:
2362 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
2363 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
2366 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2367 unreachable("Invalid HiZ state");
2370 if (hiz_op
!= ISL_AUX_OP_NONE
) {
2371 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2374 case ISL_AUX_OP_FULL_RESOLVE
:
2375 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2376 ISL_AUX_STATE_RESOLVED
);
2379 case ISL_AUX_OP_AMBIGUATE
:
2380 /* The HiZ resolve operation is actually an ambiguate */
2381 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2382 ISL_AUX_STATE_PASS_THROUGH
);
2386 unreachable("Invalid HiZ op");
2392 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2393 struct intel_mipmap_tree
*mt
,
2394 uint32_t level
, uint32_t layer
,
2395 enum isl_aux_usage aux_usage
)
2397 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2399 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2400 case ISL_AUX_STATE_CLEAR
:
2401 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2402 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2403 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2406 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2407 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2408 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2409 break; /* Nothing to do */
2411 case ISL_AUX_STATE_RESOLVED
:
2412 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2413 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2414 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2416 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2417 ISL_AUX_STATE_AUX_INVALID
);
2421 case ISL_AUX_STATE_PASS_THROUGH
:
2422 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2423 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2424 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2428 case ISL_AUX_STATE_AUX_INVALID
:
2429 assert(aux_usage
!= ISL_AUX_USAGE_HIZ
);
2432 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2433 unreachable("Invalid HiZ state");
2438 intel_miptree_prepare_access(struct brw_context
*brw
,
2439 struct intel_mipmap_tree
*mt
,
2440 uint32_t start_level
, uint32_t num_levels
,
2441 uint32_t start_layer
, uint32_t num_layers
,
2442 enum isl_aux_usage aux_usage
,
2443 bool fast_clear_supported
)
2445 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2447 switch (mt
->aux_usage
) {
2448 case ISL_AUX_USAGE_NONE
:
2452 case ISL_AUX_USAGE_MCS
:
2453 assert(mt
->aux_buf
);
2454 assert(start_level
== 0 && num_levels
== 1);
2455 const uint32_t level_layers
=
2456 miptree_layer_range_length(mt
, 0, start_layer
, num_layers
);
2457 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2458 intel_miptree_prepare_mcs_access(brw
, mt
, start_layer
+ a
,
2459 aux_usage
, fast_clear_supported
);
2463 case ISL_AUX_USAGE_CCS_D
:
2464 case ISL_AUX_USAGE_CCS_E
:
2468 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2469 const uint32_t level
= start_level
+ l
;
2470 const uint32_t level_layers
=
2471 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2472 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2473 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2475 aux_usage
, fast_clear_supported
);
2480 case ISL_AUX_USAGE_HIZ
:
2481 assert(mt
->aux_buf
);
2482 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2483 const uint32_t level
= start_level
+ l
;
2484 if (!intel_miptree_level_has_hiz(mt
, level
))
2487 const uint32_t level_layers
=
2488 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2489 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2490 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2491 aux_usage
, fast_clear_supported
);
2497 unreachable("Invalid aux usage");
2502 intel_miptree_finish_write(struct brw_context
*brw
,
2503 struct intel_mipmap_tree
*mt
, uint32_t level
,
2504 uint32_t start_layer
, uint32_t num_layers
,
2505 enum isl_aux_usage aux_usage
)
2507 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2509 switch (mt
->aux_usage
) {
2510 case ISL_AUX_USAGE_NONE
:
2514 case ISL_AUX_USAGE_MCS
:
2515 assert(mt
->aux_buf
);
2516 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2517 intel_miptree_finish_mcs_write(brw
, mt
, start_layer
+ a
,
2522 case ISL_AUX_USAGE_CCS_D
:
2523 case ISL_AUX_USAGE_CCS_E
:
2527 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2528 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2533 case ISL_AUX_USAGE_HIZ
:
2534 if (!intel_miptree_level_has_hiz(mt
, level
))
2537 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2538 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2544 unreachable("Invavlid aux usage");
2549 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2550 uint32_t level
, uint32_t layer
)
2552 intel_miptree_check_level_layer(mt
, level
, layer
);
2554 if (_mesa_is_format_color_format(mt
->format
)) {
2555 assert(mt
->aux_buf
!= NULL
);
2556 assert(mt
->surf
.samples
== 1 ||
2557 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2558 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2559 unreachable("Cannot get aux state for stencil");
2561 assert(intel_miptree_level_has_hiz(mt
, level
));
2564 return mt
->aux_state
[level
][layer
];
2568 intel_miptree_set_aux_state(struct brw_context
*brw
,
2569 struct intel_mipmap_tree
*mt
, uint32_t level
,
2570 uint32_t start_layer
, uint32_t num_layers
,
2571 enum isl_aux_state aux_state
)
2573 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2575 if (_mesa_is_format_color_format(mt
->format
)) {
2576 assert(mt
->aux_buf
!= NULL
);
2577 assert(mt
->surf
.samples
== 1 ||
2578 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2579 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2580 unreachable("Cannot get aux state for stencil");
2582 assert(intel_miptree_level_has_hiz(mt
, level
));
2585 for (unsigned a
= 0; a
< num_layers
; a
++) {
2586 if (mt
->aux_state
[level
][start_layer
+ a
] != aux_state
) {
2587 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2588 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2593 /* On Gen9 color buffers may be compressed by the hardware (lossless
2594 * compression). There are, however, format restrictions and care needs to be
2595 * taken that the sampler engine is capable for re-interpreting a buffer with
2596 * format different the buffer was originally written with.
2598 * For example, SRGB formats are not compressible and the sampler engine isn't
2599 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2600 * color buffer needs to be resolved so that the sampling surface can be
2601 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2605 can_texture_with_ccs(struct brw_context
*brw
,
2606 struct intel_mipmap_tree
*mt
,
2607 enum isl_format view_format
)
2609 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2612 if (!format_ccs_e_compat_with_miptree(&brw
->screen
->devinfo
,
2614 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2615 isl_format_get_layout(view_format
)->name
,
2616 _mesa_get_format_name(mt
->format
));
2624 intel_miptree_texture_aux_usage(struct brw_context
*brw
,
2625 struct intel_mipmap_tree
*mt
,
2626 enum isl_format view_format
)
2628 switch (mt
->aux_usage
) {
2629 case ISL_AUX_USAGE_HIZ
:
2630 if (intel_miptree_sample_with_hiz(brw
, mt
))
2631 return ISL_AUX_USAGE_HIZ
;
2634 case ISL_AUX_USAGE_MCS
:
2635 return ISL_AUX_USAGE_MCS
;
2637 case ISL_AUX_USAGE_CCS_D
:
2638 case ISL_AUX_USAGE_CCS_E
:
2640 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2641 return ISL_AUX_USAGE_NONE
;
2644 /* If we don't have any unresolved color, report an aux usage of
2645 * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
2646 * aux surface and we can save some bandwidth.
2648 if (!intel_miptree_has_color_unresolved(mt
, 0, INTEL_REMAINING_LEVELS
,
2649 0, INTEL_REMAINING_LAYERS
))
2650 return ISL_AUX_USAGE_NONE
;
2652 if (can_texture_with_ccs(brw
, mt
, view_format
))
2653 return ISL_AUX_USAGE_CCS_E
;
2660 return ISL_AUX_USAGE_NONE
;
2664 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
2666 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
2667 * values so sRGB curve application was a no-op for all fast-clearable
2670 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
2671 * values, the hardware interprets the floats, not as what would be
2672 * returned from the sampler (or written by the shader), but as being
2673 * between format conversion and sRGB curve application. This means that
2674 * we can switch between sRGB and UNORM without having to whack the clear
2677 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
2681 intel_miptree_prepare_texture(struct brw_context
*brw
,
2682 struct intel_mipmap_tree
*mt
,
2683 enum isl_format view_format
,
2684 uint32_t start_level
, uint32_t num_levels
,
2685 uint32_t start_layer
, uint32_t num_layers
)
2687 enum isl_aux_usage aux_usage
=
2688 intel_miptree_texture_aux_usage(brw
, mt
, view_format
);
2689 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2691 /* Clear color is specified as ints or floats and the conversion is done by
2692 * the sampler. If we have a texture view, we would have to perform the
2693 * clear color conversion manually. Just disable clear color.
2695 if (!isl_formats_are_fast_clear_compatible(mt
->surf
.format
, view_format
))
2696 clear_supported
= false;
2698 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2699 start_layer
, num_layers
,
2700 aux_usage
, clear_supported
);
2704 intel_miptree_prepare_image(struct brw_context
*brw
,
2705 struct intel_mipmap_tree
*mt
)
2707 /* The data port doesn't understand any compression */
2708 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2709 0, INTEL_REMAINING_LAYERS
,
2710 ISL_AUX_USAGE_NONE
, false);
2714 intel_miptree_render_aux_usage(struct brw_context
*brw
,
2715 struct intel_mipmap_tree
*mt
,
2716 enum isl_format render_format
,
2718 bool draw_aux_disabled
)
2720 struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2722 if (draw_aux_disabled
)
2723 return ISL_AUX_USAGE_NONE
;
2725 switch (mt
->aux_usage
) {
2726 case ISL_AUX_USAGE_MCS
:
2727 assert(mt
->aux_buf
);
2728 return ISL_AUX_USAGE_MCS
;
2730 case ISL_AUX_USAGE_CCS_D
:
2731 case ISL_AUX_USAGE_CCS_E
:
2733 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2734 return ISL_AUX_USAGE_NONE
;
2737 /* gen9 hardware technically supports non-0/1 clear colors with sRGB
2738 * formats. However, there are issues with blending where it doesn't
2739 * properly apply the sRGB curve to the clear color when blending.
2741 if (devinfo
->gen
== 9 && blend_enabled
&&
2742 isl_format_is_srgb(render_format
) &&
2743 !isl_color_value_is_zero_one(mt
->fast_clear_color
, render_format
))
2744 return ISL_AUX_USAGE_NONE
;
2746 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
&&
2747 format_ccs_e_compat_with_miptree(&brw
->screen
->devinfo
,
2749 return ISL_AUX_USAGE_CCS_E
;
2751 /* Otherwise, we have to fall back to CCS_D */
2752 return ISL_AUX_USAGE_CCS_D
;
2755 return ISL_AUX_USAGE_NONE
;
2760 intel_miptree_prepare_render(struct brw_context
*brw
,
2761 struct intel_mipmap_tree
*mt
, uint32_t level
,
2762 uint32_t start_layer
, uint32_t layer_count
,
2763 enum isl_aux_usage aux_usage
)
2765 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2766 aux_usage
, aux_usage
!= ISL_AUX_USAGE_NONE
);
2770 intel_miptree_finish_render(struct brw_context
*brw
,
2771 struct intel_mipmap_tree
*mt
, uint32_t level
,
2772 uint32_t start_layer
, uint32_t layer_count
,
2773 enum isl_aux_usage aux_usage
)
2775 assert(_mesa_is_format_color_format(mt
->format
));
2777 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2782 intel_miptree_prepare_depth(struct brw_context
*brw
,
2783 struct intel_mipmap_tree
*mt
, uint32_t level
,
2784 uint32_t start_layer
, uint32_t layer_count
)
2786 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2787 mt
->aux_usage
, mt
->aux_buf
!= NULL
);
2791 intel_miptree_finish_depth(struct brw_context
*brw
,
2792 struct intel_mipmap_tree
*mt
, uint32_t level
,
2793 uint32_t start_layer
, uint32_t layer_count
,
2796 if (depth_written
) {
2797 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2798 mt
->aux_buf
!= NULL
);
2803 intel_miptree_prepare_external(struct brw_context
*brw
,
2804 struct intel_mipmap_tree
*mt
)
2806 enum isl_aux_usage aux_usage
= ISL_AUX_USAGE_NONE
;
2807 bool supports_fast_clear
= false;
2809 const struct isl_drm_modifier_info
*mod_info
=
2810 isl_drm_modifier_get_info(mt
->drm_modifier
);
2812 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
2813 /* CCS_E is the only supported aux for external images and it's only
2814 * supported on very simple images.
2816 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
2817 assert(_mesa_is_format_color_format(mt
->format
));
2818 assert(mt
->first_level
== 0 && mt
->last_level
== 0);
2819 assert(mt
->surf
.logical_level0_px
.depth
== 1);
2820 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
2821 assert(mt
->surf
.samples
== 1);
2822 assert(mt
->aux_buf
!= NULL
);
2824 aux_usage
= mod_info
->aux_usage
;
2825 supports_fast_clear
= mod_info
->supports_clear_color
;
2828 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2829 0, INTEL_REMAINING_LAYERS
,
2830 aux_usage
, supports_fast_clear
);
2834 intel_miptree_finish_external(struct brw_context
*brw
,
2835 struct intel_mipmap_tree
*mt
)
2840 /* We don't know the actual aux state of the aux surface. The previous
2841 * owner could have given it to us in a number of different states.
2842 * Because we don't know the aux state, we reset the aux state to the
2843 * least common denominator of possible valid states.
2845 enum isl_aux_state default_aux_state
=
2846 isl_drm_modifier_get_default_aux_state(mt
->drm_modifier
);
2847 assert(mt
->last_level
== mt
->first_level
);
2848 intel_miptree_set_aux_state(brw
, mt
, 0, 0, INTEL_REMAINING_LAYERS
,
2853 * Make it possible to share the BO backing the given miptree with another
2854 * process or another miptree.
2856 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2857 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2858 * ensure that no MCS buffer gets allocated in the future.
2860 * HiZ is similarly unsafe with shared buffers.
2863 intel_miptree_make_shareable(struct brw_context
*brw
,
2864 struct intel_mipmap_tree
*mt
)
2866 /* MCS buffers are also used for multisample buffers, but we can't resolve
2867 * away a multisample MCS buffer because it's an integral part of how the
2868 * pixel data is stored. Fortunately this code path should never be
2869 * reached for multisample buffers.
2871 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2872 mt
->surf
.samples
== 1);
2874 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2875 0, INTEL_REMAINING_LAYERS
,
2876 ISL_AUX_USAGE_NONE
, false);
2879 intel_miptree_aux_buffer_free(mt
->aux_buf
);
2882 /* Make future calls of intel_miptree_level_has_hiz() return false. */
2883 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2884 mt
->level
[l
].has_hiz
= false;
2887 free(mt
->aux_state
);
2888 mt
->aux_state
= NULL
;
2889 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
2892 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2893 mt
->supports_fast_clear
= false;
2898 * \brief Get pointer offset into stencil buffer.
2900 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2901 * must decode the tile's layout in software.
2904 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2906 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2908 * Even though the returned offset is always positive, the return type is
2910 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2911 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2914 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2916 uint32_t tile_size
= 4096;
2917 uint32_t tile_width
= 64;
2918 uint32_t tile_height
= 64;
2919 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2921 uint32_t tile_x
= x
/ tile_width
;
2922 uint32_t tile_y
= y
/ tile_height
;
2924 /* The byte's address relative to the tile's base addres. */
2925 uint32_t byte_x
= x
% tile_width
;
2926 uint32_t byte_y
= y
% tile_height
;
2928 uintptr_t u
= tile_y
* row_size
2929 + tile_x
* tile_size
2930 + 512 * (byte_x
/ 8)
2932 + 32 * ((byte_y
/ 4) % 2)
2933 + 16 * ((byte_x
/ 4) % 2)
2934 + 8 * ((byte_y
/ 2) % 2)
2935 + 4 * ((byte_x
/ 2) % 2)
2940 /* adjust for bit6 swizzling */
2941 if (((byte_x
/ 8) % 2) == 1) {
2942 if (((byte_y
/ 8) % 2) == 0) {
2954 intel_miptree_updownsample(struct brw_context
*brw
,
2955 struct intel_mipmap_tree
*src
,
2956 struct intel_mipmap_tree
*dst
)
2958 unsigned src_w
= src
->surf
.logical_level0_px
.width
;
2959 unsigned src_h
= src
->surf
.logical_level0_px
.height
;
2960 unsigned dst_w
= dst
->surf
.logical_level0_px
.width
;
2961 unsigned dst_h
= dst
->surf
.logical_level0_px
.height
;
2963 brw_blorp_blit_miptrees(brw
,
2964 src
, 0 /* level */, 0 /* layer */,
2965 src
->format
, SWIZZLE_XYZW
,
2966 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2969 GL_NEAREST
, false, false /*mirror x, y*/,
2972 if (src
->stencil_mt
) {
2973 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2974 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2975 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2976 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2978 brw_blorp_blit_miptrees(brw
,
2979 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2980 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2981 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2982 dst
->stencil_mt
->format
,
2985 GL_NEAREST
, false, false /*mirror x, y*/,
2986 false, false /* decode/encode srgb */);
2991 intel_update_r8stencil(struct brw_context
*brw
,
2992 struct intel_mipmap_tree
*mt
)
2994 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
2996 assert(devinfo
->gen
>= 7);
2997 struct intel_mipmap_tree
*src
=
2998 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2999 if (!src
|| devinfo
->gen
>= 8 || !src
->r8stencil_needs_update
)
3002 assert(src
->surf
.size
> 0);
3004 if (!mt
->r8stencil_mt
) {
3005 assert(devinfo
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
3006 mt
->r8stencil_mt
= make_surface(
3009 MESA_FORMAT_R_UINT8
,
3010 src
->first_level
, src
->last_level
,
3011 src
->surf
.logical_level0_px
.width
,
3012 src
->surf
.logical_level0_px
.height
,
3013 src
->surf
.dim
== ISL_SURF_DIM_3D
?
3014 src
->surf
.logical_level0_px
.depth
:
3015 src
->surf
.logical_level0_px
.array_len
,
3018 ISL_SURF_USAGE_TEXTURE_BIT
,
3019 BO_ALLOC_BUSY
, 0, NULL
);
3020 assert(mt
->r8stencil_mt
);
3023 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
3025 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
3026 const unsigned depth
= src
->surf
.dim
== ISL_SURF_DIM_3D
?
3027 minify(src
->surf
.phys_level0_sa
.depth
, level
) :
3028 src
->surf
.phys_level0_sa
.array_len
;
3030 for (unsigned layer
= 0; layer
< depth
; layer
++) {
3031 brw_blorp_copy_miptrees(brw
,
3035 minify(src
->surf
.logical_level0_px
.width
,
3037 minify(src
->surf
.logical_level0_px
.height
,
3042 brw_cache_flush_for_read(brw
, dst
->bo
);
3043 src
->r8stencil_needs_update
= false;
3047 intel_miptree_map_raw(struct brw_context
*brw
,
3048 struct intel_mipmap_tree
*mt
,
3051 struct brw_bo
*bo
= mt
->bo
;
3053 if (brw_batch_references(&brw
->batch
, bo
))
3054 intel_batchbuffer_flush(brw
);
3056 return brw_bo_map(brw
, bo
, mode
);
3060 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
3062 brw_bo_unmap(mt
->bo
);
3066 intel_miptree_map_gtt(struct brw_context
*brw
,
3067 struct intel_mipmap_tree
*mt
,
3068 struct intel_miptree_map
*map
,
3069 unsigned int level
, unsigned int slice
)
3071 unsigned int bw
, bh
;
3073 unsigned int image_x
, image_y
;
3074 intptr_t x
= map
->x
;
3075 intptr_t y
= map
->y
;
3077 /* For compressed formats, the stride is the number of bytes per
3078 * row of blocks. intel_miptree_get_image_offset() already does
3081 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3082 assert(y
% bh
== 0);
3083 assert(x
% bw
== 0);
3087 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3094 /* Note that in the case of cube maps, the caller must have passed the
3095 * slice number referencing the face.
3097 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3101 map
->stride
= mt
->surf
.row_pitch
;
3102 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
3105 DBG("%s: %d,%d %dx%d from mt %p (%s) "
3106 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
3107 map
->x
, map
->y
, map
->w
, map
->h
,
3108 mt
, _mesa_get_format_name(mt
->format
),
3109 x
, y
, map
->ptr
, map
->stride
);
3113 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
3115 intel_miptree_unmap_raw(mt
);
3119 intel_miptree_map_blit(struct brw_context
*brw
,
3120 struct intel_mipmap_tree
*mt
,
3121 struct intel_miptree_map
*map
,
3122 unsigned int level
, unsigned int slice
)
3124 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
3125 /* first_level */ 0,
3129 MIPTREE_CREATE_LINEAR
);
3131 if (!map
->linear_mt
) {
3132 fprintf(stderr
, "Failed to allocate blit temporary\n");
3135 map
->stride
= map
->linear_mt
->surf
.row_pitch
;
3137 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3138 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3139 * invalidate is set, since we'll be writing the whole rectangle from our
3140 * temporary buffer back out.
3142 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3143 if (!intel_miptree_copy(brw
,
3144 mt
, level
, slice
, map
->x
, map
->y
,
3145 map
->linear_mt
, 0, 0, 0, 0,
3147 fprintf(stderr
, "Failed to blit\n");
3152 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3154 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3155 map
->x
, map
->y
, map
->w
, map
->h
,
3156 mt
, _mesa_get_format_name(mt
->format
),
3157 level
, slice
, map
->ptr
, map
->stride
);
3162 intel_miptree_release(&map
->linear_mt
);
3168 intel_miptree_unmap_blit(struct brw_context
*brw
,
3169 struct intel_mipmap_tree
*mt
,
3170 struct intel_miptree_map
*map
,
3174 struct gl_context
*ctx
= &brw
->ctx
;
3176 intel_miptree_unmap_raw(map
->linear_mt
);
3178 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3179 bool ok
= intel_miptree_copy(brw
,
3180 map
->linear_mt
, 0, 0, 0, 0,
3181 mt
, level
, slice
, map
->x
, map
->y
,
3183 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3186 intel_miptree_release(&map
->linear_mt
);
3190 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3192 #if defined(USE_SSE41)
3194 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3195 struct intel_mipmap_tree
*mt
,
3196 struct intel_miptree_map
*map
,
3197 unsigned int level
, unsigned int slice
)
3199 assert(map
->mode
& GL_MAP_READ_BIT
);
3200 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3202 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3203 map
->x
, map
->y
, map
->w
, map
->h
,
3204 mt
, _mesa_get_format_name(mt
->format
),
3205 level
, slice
, map
->ptr
, map
->stride
);
3207 /* Map the original image */
3210 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3214 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3220 src
+= image_y
* mt
->surf
.row_pitch
;
3221 src
+= image_x
* mt
->cpp
;
3223 /* Due to the pixel offsets for the particular image being mapped, our
3224 * src pointer may not be 16-byte aligned. However, if the pitch is
3225 * divisible by 16, then the amount by which it's misaligned will remain
3226 * consistent from row to row.
3228 assert((mt
->surf
.row_pitch
% 16) == 0);
3229 const int misalignment
= ((uintptr_t) src
) & 15;
3231 /* Create an untiled temporary buffer for the mapping. */
3232 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3234 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3236 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3237 /* Offset the destination so it has the same misalignment as src. */
3238 map
->ptr
= map
->buffer
+ misalignment
;
3240 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3242 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3243 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3244 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch
;
3246 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3249 intel_miptree_unmap_raw(mt
);
3253 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3254 struct intel_mipmap_tree
*mt
,
3255 struct intel_miptree_map
*map
,
3259 _mesa_align_free(map
->buffer
);
3266 intel_miptree_map_s8(struct brw_context
*brw
,
3267 struct intel_mipmap_tree
*mt
,
3268 struct intel_miptree_map
*map
,
3269 unsigned int level
, unsigned int slice
)
3271 map
->stride
= map
->w
;
3272 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3276 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3277 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3278 * invalidate is set, since we'll be writing the whole rectangle from our
3279 * temporary buffer back out.
3281 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3282 uint8_t *untiled_s8_map
= map
->ptr
;
3283 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3284 unsigned int image_x
, image_y
;
3286 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3288 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3289 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3290 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3291 x
+ image_x
+ map
->x
,
3292 y
+ image_y
+ map
->y
,
3293 brw
->has_swizzling
);
3294 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3298 intel_miptree_unmap_raw(mt
);
3300 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3301 map
->x
, map
->y
, map
->w
, map
->h
,
3302 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3304 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3305 map
->x
, map
->y
, map
->w
, map
->h
,
3306 mt
, map
->ptr
, map
->stride
);
3311 intel_miptree_unmap_s8(struct brw_context
*brw
,
3312 struct intel_mipmap_tree
*mt
,
3313 struct intel_miptree_map
*map
,
3317 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3318 unsigned int image_x
, image_y
;
3319 uint8_t *untiled_s8_map
= map
->ptr
;
3320 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3322 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3324 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3325 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3326 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3327 image_x
+ x
+ map
->x
,
3328 image_y
+ y
+ map
->y
,
3329 brw
->has_swizzling
);
3330 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3334 intel_miptree_unmap_raw(mt
);
3341 intel_miptree_map_etc(struct brw_context
*brw
,
3342 struct intel_mipmap_tree
*mt
,
3343 struct intel_miptree_map
*map
,
3347 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3348 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3349 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3352 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3353 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3355 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3356 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3357 map
->w
, map
->h
, 1));
3358 map
->ptr
= map
->buffer
;
3362 intel_miptree_unmap_etc(struct brw_context
*brw
,
3363 struct intel_mipmap_tree
*mt
,
3364 struct intel_miptree_map
*map
,
3370 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3375 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3376 + image_y
* mt
->surf
.row_pitch
3377 + image_x
* mt
->cpp
;
3379 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3380 _mesa_etc1_unpack_rgba8888(dst
, mt
->surf
.row_pitch
,
3381 map
->ptr
, map
->stride
,
3384 _mesa_unpack_etc2_format(dst
, mt
->surf
.row_pitch
,
3385 map
->ptr
, map
->stride
,
3386 map
->w
, map
->h
, mt
->etc_format
);
3388 intel_miptree_unmap_raw(mt
);
3393 * Mapping function for packed depth/stencil miptrees backed by real separate
3394 * miptrees for depth and stencil.
3396 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3397 * separate from the depth buffer. Yet at the GL API level, we have to expose
3398 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3399 * be able to map that memory for texture storage and glReadPixels-type
3400 * operations. We give Mesa core that access by mallocing a temporary and
3401 * copying the data between the actual backing store and the temporary.
3404 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3405 struct intel_mipmap_tree
*mt
,
3406 struct intel_miptree_map
*map
,
3407 unsigned int level
, unsigned int slice
)
3409 struct intel_mipmap_tree
*z_mt
= mt
;
3410 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3411 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3412 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3414 map
->stride
= map
->w
* packed_bpp
;
3415 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3419 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3420 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3421 * invalidate is set, since we'll be writing the whole rectangle from our
3422 * temporary buffer back out.
3424 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3425 uint32_t *packed_map
= map
->ptr
;
3426 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3427 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3428 unsigned int s_image_x
, s_image_y
;
3429 unsigned int z_image_x
, z_image_y
;
3431 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3432 &s_image_x
, &s_image_y
);
3433 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3434 &z_image_x
, &z_image_y
);
3436 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3437 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3438 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3439 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3442 brw
->has_swizzling
);
3443 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3444 (z_mt
->surf
.row_pitch
/ 4) +
3445 (map_x
+ z_image_x
));
3446 uint8_t s
= s_map
[s_offset
];
3447 uint32_t z
= z_map
[z_offset
];
3449 if (map_z32f_x24s8
) {
3450 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3451 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3453 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3458 intel_miptree_unmap_raw(s_mt
);
3459 intel_miptree_unmap_raw(z_mt
);
3461 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3463 map
->x
, map
->y
, map
->w
, map
->h
,
3464 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3465 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3466 map
->ptr
, map
->stride
);
3468 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3469 map
->x
, map
->y
, map
->w
, map
->h
,
3470 mt
, map
->ptr
, map
->stride
);
3475 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3476 struct intel_mipmap_tree
*mt
,
3477 struct intel_miptree_map
*map
,
3481 struct intel_mipmap_tree
*z_mt
= mt
;
3482 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3483 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3485 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3486 uint32_t *packed_map
= map
->ptr
;
3487 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3488 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3489 unsigned int s_image_x
, s_image_y
;
3490 unsigned int z_image_x
, z_image_y
;
3492 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3493 &s_image_x
, &s_image_y
);
3494 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3495 &z_image_x
, &z_image_y
);
3497 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3498 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3499 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3500 x
+ s_image_x
+ map
->x
,
3501 y
+ s_image_y
+ map
->y
,
3502 brw
->has_swizzling
);
3503 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3504 (z_mt
->surf
.row_pitch
/ 4) +
3505 (x
+ z_image_x
+ map
->x
));
3507 if (map_z32f_x24s8
) {
3508 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3509 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3511 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3512 s_map
[s_offset
] = packed
>> 24;
3513 z_map
[z_offset
] = packed
;
3518 intel_miptree_unmap_raw(s_mt
);
3519 intel_miptree_unmap_raw(z_mt
);
3521 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3523 map
->x
, map
->y
, map
->w
, map
->h
,
3524 z_mt
, _mesa_get_format_name(z_mt
->format
),
3525 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3526 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3527 map
->ptr
, map
->stride
);
3534 * Create and attach a map to the miptree at (level, slice). Return the
3537 static struct intel_miptree_map
*
3538 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3547 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3552 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3553 mt
->level
[level
].slice
[slice
].map
= map
;
3565 * Release the map at (level, slice).
3568 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3572 struct intel_miptree_map
**map
;
3574 map
= &mt
->level
[level
].slice
[slice
].map
;
3580 can_blit_slice(struct intel_mipmap_tree
*mt
,
3581 unsigned int level
, unsigned int slice
)
3583 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3584 if (mt
->surf
.row_pitch
>= 32768)
3591 use_intel_mipree_map_blit(struct brw_context
*brw
,
3592 struct intel_mipmap_tree
*mt
,
3597 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
3599 if (devinfo
->has_llc
&&
3600 /* It's probably not worth swapping to the blit ring because of
3601 * all the overhead involved.
3603 !(mode
& GL_MAP_WRITE_BIT
) &&
3605 (mt
->surf
.tiling
== ISL_TILING_X
||
3606 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3607 (devinfo
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3608 /* Fast copy blit on skl+ supports all tiling formats. */
3609 devinfo
->gen
>= 9) &&
3610 can_blit_slice(mt
, level
, slice
))
3613 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3614 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3615 assert(can_blit_slice(mt
, level
, slice
));
3623 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3624 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3625 * arithmetic overflow.
3627 * If you call this function and use \a out_stride, then you're doing pointer
3628 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3629 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3630 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3631 * which usually have type uint32_t or GLuint.
3634 intel_miptree_map(struct brw_context
*brw
,
3635 struct intel_mipmap_tree
*mt
,
3644 ptrdiff_t *out_stride
)
3646 struct intel_miptree_map
*map
;
3648 assert(mt
->surf
.samples
== 1);
3650 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3657 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3658 map
->mode
& GL_MAP_WRITE_BIT
);
3660 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3661 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3662 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3663 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3664 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3665 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3666 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3667 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3668 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3669 #if defined(USE_SSE41)
3670 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3671 !mt
->compressed
&& cpu_has_sse4_1
&&
3672 (mt
->surf
.row_pitch
% 16 == 0)) {
3673 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3676 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3679 *out_ptr
= map
->ptr
;
3680 *out_stride
= map
->stride
;
3682 if (map
->ptr
== NULL
)
3683 intel_miptree_release_map(mt
, level
, slice
);
3687 intel_miptree_unmap(struct brw_context
*brw
,
3688 struct intel_mipmap_tree
*mt
,
3692 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3694 assert(mt
->surf
.samples
== 1);
3699 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3700 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3702 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3703 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3704 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3705 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3706 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3707 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3708 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3709 } else if (map
->linear_mt
) {
3710 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3711 #if defined(USE_SSE41)
3712 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3713 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3716 intel_miptree_unmap_gtt(mt
);
3719 intel_miptree_release_map(mt
, level
, slice
);
3723 get_isl_surf_dim(GLenum target
)
3727 case GL_TEXTURE_1D_ARRAY
:
3728 return ISL_SURF_DIM_1D
;
3731 case GL_TEXTURE_2D_ARRAY
:
3732 case GL_TEXTURE_RECTANGLE
:
3733 case GL_TEXTURE_CUBE_MAP
:
3734 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3735 case GL_TEXTURE_2D_MULTISAMPLE
:
3736 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3737 case GL_TEXTURE_EXTERNAL_OES
:
3738 return ISL_SURF_DIM_2D
;
3741 return ISL_SURF_DIM_3D
;
3744 unreachable("Invalid texture target");
3748 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3749 enum isl_tiling tiling
, GLenum target
)
3753 case GL_TEXTURE_1D_ARRAY
:
3754 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3755 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3758 case GL_TEXTURE_2D_ARRAY
:
3759 case GL_TEXTURE_RECTANGLE
:
3760 case GL_TEXTURE_2D_MULTISAMPLE
:
3761 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3762 case GL_TEXTURE_EXTERNAL_OES
:
3763 return ISL_DIM_LAYOUT_GEN4_2D
;
3765 case GL_TEXTURE_CUBE_MAP
:
3766 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3767 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3768 ISL_DIM_LAYOUT_GEN4_2D
);
3771 return (devinfo
->gen
>= 9 ?
3772 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3775 unreachable("Invalid texture target");
3779 intel_miptree_set_clear_color(struct brw_context
*brw
,
3780 struct intel_mipmap_tree
*mt
,
3781 const union gl_color_union
*color
)
3783 const union isl_color_value clear_color
=
3784 brw_meta_convert_fast_clear_color(brw
, mt
, color
);
3786 if (memcmp(&mt
->fast_clear_color
, &clear_color
, sizeof(clear_color
)) != 0) {
3787 mt
->fast_clear_color
= clear_color
;
3788 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
3795 intel_miptree_set_depth_clear_value(struct brw_context
*brw
,
3796 struct intel_mipmap_tree
*mt
,
3799 if (mt
->fast_clear_color
.f32
[0] != clear_value
) {
3800 mt
->fast_clear_color
.f32
[0] = clear_value
;
3801 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;