2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_mipmap_tree.h"
31 #include "intel_resolve_map.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
);
54 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
57 intel_miptree_alloc_mcs(struct brw_context
*brw
,
58 struct intel_mipmap_tree
*mt
,
62 * Determine which MSAA layout should be used by the MSAA surface being
63 * created, based on the chip generation and the surface type.
65 static enum intel_msaa_layout
66 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
67 bool disable_aux_buffers
)
69 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
71 return INTEL_MSAA_LAYOUT_IMS
;
73 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
74 switch (_mesa_get_format_base_format(format
)) {
75 case GL_DEPTH_COMPONENT
:
76 case GL_STENCIL_INDEX
:
77 case GL_DEPTH_STENCIL
:
78 return INTEL_MSAA_LAYOUT_IMS
;
80 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
82 * This field must be set to 0 for all SINT MSRTs when all RT channels
85 * In practice this means that we have to disable MCS for all signed
86 * integer MSAA buffers. The alternative, to disable MCS only when one
87 * of the render target channels is disabled, is impractical because it
88 * would require converting between CMS and UMS MSAA layouts on the fly,
91 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
92 return INTEL_MSAA_LAYOUT_UMS
;
93 } else if (disable_aux_buffers
) {
94 /* We can't use the CMS layout because it uses an aux buffer, the MCS
95 * buffer. So fallback to UMS, which is identical to CMS without the
97 return INTEL_MSAA_LAYOUT_UMS
;
99 return INTEL_MSAA_LAYOUT_CMS
;
105 intel_tiling_supports_non_msrt_mcs(const struct brw_context
*brw
,
108 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
109 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
111 * - Support is limited to tiled render targets.
113 * Gen9 changes the restriction to Y-tile only.
116 return tiling
== I915_TILING_Y
;
117 else if (brw
->gen
>= 7)
118 return tiling
!= I915_TILING_NONE
;
124 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
125 * can be used. This doesn't (and should not) inspect any of the properties of
128 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
129 * beneath the "Fast Color Clear" bullet (p326):
131 * - Support is for non-mip-mapped and non-array surface types only.
133 * And then later, on p327:
135 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
138 * From the Skylake documentation, it is made clear that X-tiling is no longer
141 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
145 intel_miptree_supports_non_msrt_fast_clear(struct brw_context
*brw
,
146 const struct intel_mipmap_tree
*mt
)
148 /* MCS support does not exist prior to Gen7 */
152 if (mt
->disable_aux_buffers
)
155 /* This function applies only to non-multisampled render targets. */
156 if (mt
->num_samples
> 1)
159 /* MCS is only supported for color buffers */
160 switch (_mesa_get_format_base_format(mt
->format
)) {
161 case GL_DEPTH_COMPONENT
:
162 case GL_DEPTH_STENCIL
:
163 case GL_STENCIL_INDEX
:
167 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
170 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
171 const bool arrayed
= mt
->physical_depth0
!= 1;
174 /* Multisample surfaces with the CMS layout are not layered surfaces,
175 * yet still have physical_depth0 > 1. Assert that we don't
176 * accidentally reject a multisampled surface here. We should have
177 * rejected it earlier by explicitly checking the sample count.
179 assert(mt
->num_samples
<= 1);
182 /* Handle the hardware restrictions...
184 * All GENs have the following restriction: "MCS buffer for non-MSRT is
185 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
187 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
188 * Non-MultiSampler Render Target Restrictions) Support is for
189 * non-mip-mapped and non-array surface types only.
191 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
192 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
193 * surfaces are supported with MCS buffer layout with these alignments in
194 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
196 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
197 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
198 * surfaces are supported with MCS buffer layout with these alignments in
199 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
201 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
204 /* There's no point in using an MCS buffer if the surface isn't in a
207 if (!brw
->format_supported_as_render_target
[mt
->format
])
211 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
212 const uint32_t brw_format
= brw_format_for_mesa_format(linear_format
);
213 return isl_format_supports_lossless_compression(&brw
->screen
->devinfo
,
219 /* On Gen9 support for color buffer compression was extended to single
220 * sampled surfaces. This is a helper considering both auxiliary buffer
221 * type and number of samples telling if the given miptree represents
222 * the new single sampled case - also called lossless compression.
225 intel_miptree_is_lossless_compressed(const struct brw_context
*brw
,
226 const struct intel_mipmap_tree
*mt
)
228 /* Only available from Gen9 onwards. */
232 /* Compression always requires auxiliary buffer. */
236 /* Single sample compression is represented re-using msaa compression
237 * layout type: "Compressed Multisampled Surfaces".
239 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
)
242 /* And finally distinguish between msaa and single sample case. */
243 return mt
->num_samples
<= 1;
247 intel_miptree_supports_lossless_compressed(struct brw_context
*brw
,
248 const struct intel_mipmap_tree
*mt
)
250 /* For now compression is only enabled for integer formats even though
251 * there exist supported floating point formats also. This is a heuristic
252 * decision based on current public benchmarks. In none of the cases these
253 * formats provided any improvement but a few cases were seen to regress.
254 * Hence these are left to to be enabled in the future when they are known
257 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
260 /* Fast clear mechanism and lossless compression go hand in hand. */
261 if (!intel_miptree_supports_non_msrt_fast_clear(brw
, mt
))
264 /* Fast clear can be also used to clear srgb surfaces by using equivalent
265 * linear format. This trick, however, can't be extended to be used with
266 * lossless compression and therefore a check is needed to see if the format
269 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
273 * Determine depth format corresponding to a depth+stencil format,
274 * for separate stencil.
277 intel_depth_format_for_depthstencil_format(mesa_format format
) {
279 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
280 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
281 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
282 return MESA_FORMAT_Z_FLOAT32
;
290 * @param for_bo Indicates that the caller is
291 * intel_miptree_create_for_bo(). If true, then do not create
294 static struct intel_mipmap_tree
*
295 intel_miptree_create_layout(struct brw_context
*brw
,
304 uint32_t layout_flags
)
306 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
310 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
311 _mesa_enum_to_string(target
),
312 _mesa_get_format_name(format
),
313 first_level
, last_level
, depth0
, mt
);
315 if (target
== GL_TEXTURE_1D_ARRAY
)
316 assert(height0
== 1);
320 mt
->first_level
= first_level
;
321 mt
->last_level
= last_level
;
322 mt
->logical_width0
= width0
;
323 mt
->logical_height0
= height0
;
324 mt
->logical_depth0
= depth0
;
325 mt
->disable_aux_buffers
= (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) != 0;
327 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
328 exec_list_make_empty(&mt
->hiz_map
);
329 exec_list_make_empty(&mt
->color_resolve_map
);
330 mt
->cpp
= _mesa_get_format_bytes(format
);
331 mt
->num_samples
= num_samples
;
332 mt
->compressed
= _mesa_is_format_compressed(format
);
333 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
336 int depth_multiply
= 1;
337 if (num_samples
> 1) {
338 /* Adjust width/height/depth for MSAA */
339 mt
->msaa_layout
= compute_msaa_layout(brw
, format
,
340 mt
->disable_aux_buffers
);
341 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
342 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
343 * "If the surface is multisampled and it is a depth or stencil
344 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
345 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
348 * +----------------------------------------------------------------+
349 * | Num Multisamples | W_l = | H_l = |
350 * +----------------------------------------------------------------+
351 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
352 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
353 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
354 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
355 * +----------------------------------------------------------------+
358 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
359 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
360 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
362 * Another more complicated explanation for these adjustments comes
363 * from the Sandybridge PRM, volume 4, part 1, page 31:
365 * "Any of the other messages (sample*, LOD, load4) used with a
366 * (4x) multisampled surface will in-effect sample a surface with
367 * double the height and width as that indicated in the surface
368 * state. Each pixel position on the original-sized surface is
369 * replaced with a 2x2 of samples with the following arrangement:
374 * Thus, when sampling from a multisampled texture, it behaves as
375 * though the layout in memory for (x,y,sample) is:
377 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
378 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
380 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
381 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
383 * However, the actual layout of multisampled data in memory is:
385 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
386 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
388 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
389 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
391 * This pattern repeats for each 2x2 pixel block.
393 * As a result, when calculating the size of our 4-sample buffer for
394 * an odd width or height, we have to align before scaling up because
395 * sample 3 is in that bottom right 2x2 block.
397 switch (num_samples
) {
399 assert(brw
->gen
>= 8);
400 width0
= ALIGN(width0
, 2) * 2;
401 height0
= ALIGN(height0
, 2);
404 width0
= ALIGN(width0
, 2) * 2;
405 height0
= ALIGN(height0
, 2) * 2;
408 width0
= ALIGN(width0
, 2) * 4;
409 height0
= ALIGN(height0
, 2) * 2;
412 width0
= ALIGN(width0
, 2) * 4;
413 height0
= ALIGN(height0
, 2) * 4;
416 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
419 unreachable("not reached");
422 /* Non-interleaved */
423 depth_multiply
= num_samples
;
424 depth0
*= depth_multiply
;
428 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
429 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
430 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
431 * used on Gen8 to make it pick a qpitch value which doesn't include space
432 * for the mipmaps. On Gen9 this is not necessary because it will
433 * automatically pick a packed qpitch value whenever mt->first_level ==
435 * TODO: can we use it elsewhere?
436 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
439 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
441 switch (mt
->msaa_layout
) {
442 case INTEL_MSAA_LAYOUT_NONE
:
443 case INTEL_MSAA_LAYOUT_IMS
:
444 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
446 case INTEL_MSAA_LAYOUT_UMS
:
447 case INTEL_MSAA_LAYOUT_CMS
:
448 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
453 if (target
== GL_TEXTURE_CUBE_MAP
)
454 assert(depth0
== 6 * depth_multiply
);
456 mt
->physical_width0
= width0
;
457 mt
->physical_height0
= height0
;
458 mt
->physical_depth0
= depth0
;
460 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
461 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
462 (brw
->must_use_separate_stencil
||
463 (brw
->has_separate_stencil
&&
464 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
465 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
467 stencil_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
|
468 MIPTREE_LAYOUT_TILING_ANY
;
471 mt
->stencil_mt
= intel_miptree_create(brw
,
482 if (!mt
->stencil_mt
) {
483 intel_miptree_release(&mt
);
486 mt
->stencil_mt
->r8stencil_needs_update
= true;
488 /* Fix up the Z miptree format for how we're splitting out separate
489 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
491 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
494 if (format
== mt
->format
) {
495 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
496 _mesa_get_format_name(mt
->format
));
500 if (layout_flags
& MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
)
501 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
504 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
505 * multisampled or have an AUX buffer attached to it.
507 * GEN | MSRT | AUX_CCS_* or AUX_MCS
508 * -------------------------------------------
509 * 9 | HALIGN_16 | HALIGN_16
510 * 8 | HALIGN_ANY | HALIGN_16
514 if (intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
515 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
516 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
517 } else if (brw
->gen
>= 9 && num_samples
> 1) {
518 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
520 const UNUSED
bool is_lossless_compressed_aux
=
521 brw
->gen
>= 9 && num_samples
== 1 &&
522 mt
->format
== MESA_FORMAT_R_UINT32
;
524 /* For now, nothing else has this requirement */
525 assert(is_lossless_compressed_aux
||
526 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
529 brw_miptree_layout(brw
, mt
, layout_flags
);
531 if (mt
->disable_aux_buffers
)
532 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
539 * Choose an appropriate uncompressed format for a requested
540 * compressed format, if unsupported.
543 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
545 /* No need to lower ETC formats on these platforms,
546 * they are supported natively.
548 if (brw
->gen
>= 8 || brw
->is_baytrail
)
552 case MESA_FORMAT_ETC1_RGB8
:
553 return MESA_FORMAT_R8G8B8X8_UNORM
;
554 case MESA_FORMAT_ETC2_RGB8
:
555 return MESA_FORMAT_R8G8B8X8_UNORM
;
556 case MESA_FORMAT_ETC2_SRGB8
:
557 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
558 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
559 return MESA_FORMAT_B8G8R8A8_SRGB
;
560 case MESA_FORMAT_ETC2_RGBA8_EAC
:
561 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
562 return MESA_FORMAT_R8G8B8A8_UNORM
;
563 case MESA_FORMAT_ETC2_R11_EAC
:
564 return MESA_FORMAT_R_UNORM16
;
565 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
566 return MESA_FORMAT_R_SNORM16
;
567 case MESA_FORMAT_ETC2_RG11_EAC
:
568 return MESA_FORMAT_R16G16_UNORM
;
569 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
570 return MESA_FORMAT_R16G16_SNORM
;
572 /* Non ETC1 / ETC2 format */
577 /* This function computes Yf/Ys tiled bo size, alignment and pitch. */
579 intel_get_yf_ys_bo_size(struct intel_mipmap_tree
*mt
, unsigned *alignment
,
580 unsigned long *pitch
)
582 uint32_t tile_width
, tile_height
;
583 unsigned long stride
, size
, aligned_y
;
585 assert(mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
);
586 intel_get_tile_dims(mt
->tiling
, mt
->tr_mode
, mt
->cpp
,
587 &tile_width
, &tile_height
);
589 aligned_y
= ALIGN(mt
->total_height
, tile_height
);
590 stride
= mt
->total_width
* mt
->cpp
;
591 stride
= ALIGN(stride
, tile_width
);
592 size
= stride
* aligned_y
;
594 if (mt
->tr_mode
== INTEL_MIPTREE_TRMODE_YF
) {
595 assert(size
% 4096 == 0);
598 assert(size
% (64 * 1024) == 0);
599 *alignment
= 64 * 1024;
605 static struct intel_mipmap_tree
*
606 miptree_create(struct brw_context
*brw
,
615 uint32_t layout_flags
)
617 struct intel_mipmap_tree
*mt
;
618 mesa_format tex_format
= format
;
619 mesa_format etc_format
= MESA_FORMAT_NONE
;
620 uint32_t alloc_flags
= 0;
622 format
= intel_lower_compressed_format(brw
, format
);
624 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
626 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
627 mt
= intel_miptree_create_layout(brw
, target
, format
,
628 first_level
, last_level
, width0
,
629 height0
, depth0
, num_samples
,
632 * pitch == 0 || height == 0 indicates the null texture
634 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
635 intel_miptree_release(&mt
);
639 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
))
640 mt
->tiling
= I915_TILING_Y
;
642 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
643 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
646 mt
->etc_format
= etc_format
;
648 if (mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) {
649 unsigned alignment
= 0;
651 size
= intel_get_yf_ys_bo_size(mt
, &alignment
, &pitch
);
653 mt
->bo
= drm_intel_bo_alloc_for_render(brw
->bufmgr
, "miptree",
656 if (format
== MESA_FORMAT_S_UINT8
) {
657 /* Align to size of W tile, 64x64. */
658 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
659 ALIGN(mt
->total_width
, 64),
660 ALIGN(mt
->total_height
, 64),
661 mt
->cpp
, &mt
->tiling
, &pitch
,
664 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
665 mt
->total_width
, mt
->total_height
,
666 mt
->cpp
, &mt
->tiling
, &pitch
,
676 struct intel_mipmap_tree
*
677 intel_miptree_create(struct brw_context
*brw
,
686 uint32_t layout_flags
)
688 struct intel_mipmap_tree
*mt
= miptree_create(
690 first_level
, last_level
,
691 width0
, height0
, depth0
, num_samples
,
694 /* If the BO is too large to fit in the aperture, we need to use the
695 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
696 * handle Y-tiling, so we need to fall back to X.
698 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
699 mt
->tiling
== I915_TILING_Y
) {
700 unsigned long pitch
= mt
->pitch
;
701 const uint32_t alloc_flags
=
702 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
703 BO_ALLOC_FOR_RENDER
: 0;
704 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
705 mt
->total_width
, mt
->total_height
);
707 mt
->tiling
= I915_TILING_X
;
708 drm_intel_bo_unreference(mt
->bo
);
709 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
710 mt
->total_width
, mt
->total_height
, mt
->cpp
,
711 &mt
->tiling
, &pitch
, alloc_flags
);
718 intel_miptree_release(&mt
);
723 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
724 assert(mt
->num_samples
> 1);
725 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
726 intel_miptree_release(&mt
);
731 /* If this miptree is capable of supporting fast color clears, set
732 * fast_clear_state appropriately to ensure that fast clears will occur.
733 * Allocation of the MCS miptree will be deferred until the first fast
734 * clear actually occurs or when compressed single sampled buffer is
735 * written by the GPU for the first time.
737 if (intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) &&
738 intel_miptree_supports_non_msrt_fast_clear(brw
, mt
)) {
740 assert(brw
->gen
< 8 || mt
->halign
== 16 || num_samples
<= 1);
742 /* On Gen9+ clients are not currently capable of consuming compressed
743 * single-sampled buffers. Disabling compression allows us to skip
746 const bool lossless_compression_disabled
= INTEL_DEBUG
& DEBUG_NO_RBC
;
747 const bool is_lossless_compressed
=
748 unlikely(!lossless_compression_disabled
) &&
749 brw
->gen
>= 9 && !mt
->is_scanout
&&
750 intel_miptree_supports_lossless_compressed(brw
, mt
);
752 if (is_lossless_compressed
) {
753 intel_miptree_alloc_non_msrt_mcs(brw
, mt
, is_lossless_compressed
);
760 struct intel_mipmap_tree
*
761 intel_miptree_create_for_bo(struct brw_context
*brw
,
769 uint32_t layout_flags
)
771 struct intel_mipmap_tree
*mt
;
772 uint32_t tiling
, swizzle
;
775 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
777 /* Nothing will be able to use this miptree with the BO if the offset isn't
780 if (tiling
!= I915_TILING_NONE
)
781 assert(offset
% 4096 == 0);
783 /* miptrees can't handle negative pitch. If you need flipping of images,
784 * that's outside of the scope of the mt.
788 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
790 /* The BO already has a tiling format and we shouldn't confuse the lower
791 * layers by making it try to find a tiling format again.
793 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
794 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
796 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
797 mt
= intel_miptree_create_layout(brw
, target
, format
,
799 width
, height
, depth
, 0,
804 drm_intel_bo_reference(bo
);
814 * For a singlesample renderbuffer, this simply wraps the given BO with a
817 * For a multisample renderbuffer, this wraps the window system's
818 * (singlesample) BO with a singlesample miptree attached to the
819 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
820 * that will contain the actual rendering (which is lazily resolved to
821 * irb->singlesample_mt).
824 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
825 struct intel_renderbuffer
*irb
,
827 uint32_t width
, uint32_t height
,
830 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
831 struct intel_mipmap_tree
*multisample_mt
= NULL
;
832 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
833 mesa_format format
= rb
->Format
;
834 int num_samples
= rb
->NumSamples
;
836 /* Only the front and back buffers, which are color buffers, are allocated
837 * through the image loader.
839 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
840 _mesa_get_format_base_format(format
) == GL_RGBA
);
842 singlesample_mt
= intel_miptree_create_for_bo(intel
,
850 MIPTREE_LAYOUT_FOR_SCANOUT
);
851 if (!singlesample_mt
)
854 /* If this miptree is capable of supporting fast color clears, set
855 * mcs_state appropriately to ensure that fast clears will occur.
856 * Allocation of the MCS miptree will be deferred until the first fast
857 * clear actually occurs.
859 if (intel_tiling_supports_non_msrt_mcs(intel
, singlesample_mt
->tiling
) &&
860 intel_miptree_supports_non_msrt_fast_clear(intel
, singlesample_mt
)) {
861 singlesample_mt
->no_ccs
= false;
864 if (num_samples
== 0) {
865 intel_miptree_release(&irb
->mt
);
866 irb
->mt
= singlesample_mt
;
868 assert(!irb
->singlesample_mt
);
870 intel_miptree_release(&irb
->singlesample_mt
);
871 irb
->singlesample_mt
= singlesample_mt
;
874 irb
->mt
->logical_width0
!= width
||
875 irb
->mt
->logical_height0
!= height
) {
876 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
884 irb
->need_downsample
= false;
885 intel_miptree_release(&irb
->mt
);
886 irb
->mt
= multisample_mt
;
892 intel_miptree_release(&irb
->singlesample_mt
);
893 intel_miptree_release(&irb
->mt
);
897 struct intel_mipmap_tree
*
898 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
902 uint32_t num_samples
)
904 struct intel_mipmap_tree
*mt
;
907 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
908 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
909 MIPTREE_LAYOUT_TILING_ANY
|
910 MIPTREE_LAYOUT_FOR_SCANOUT
;
912 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
913 width
, height
, depth
, num_samples
,
918 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
919 ok
= intel_miptree_alloc_hiz(brw
, mt
);
927 intel_miptree_release(&mt
);
932 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
933 struct intel_mipmap_tree
*src
)
938 intel_miptree_release(dst
);
942 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
950 intel_miptree_release(struct intel_mipmap_tree
**mt
)
955 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
956 if (--(*mt
)->refcount
<= 0) {
959 DBG("%s deleting %p\n", __func__
, *mt
);
961 drm_intel_bo_unreference((*mt
)->bo
);
962 intel_miptree_release(&(*mt
)->stencil_mt
);
963 intel_miptree_release(&(*mt
)->r8stencil_mt
);
964 if ((*mt
)->hiz_buf
) {
965 if ((*mt
)->hiz_buf
->mt
)
966 intel_miptree_release(&(*mt
)->hiz_buf
->mt
);
968 drm_intel_bo_unreference((*mt
)->hiz_buf
->aux_base
.bo
);
969 free((*mt
)->hiz_buf
);
971 if ((*mt
)->mcs_buf
) {
972 drm_intel_bo_unreference((*mt
)->mcs_buf
->bo
);
973 free((*mt
)->mcs_buf
);
975 intel_resolve_map_clear(&(*mt
)->hiz_map
);
976 intel_resolve_map_clear(&(*mt
)->color_resolve_map
);
978 intel_miptree_release(&(*mt
)->plane
[0]);
979 intel_miptree_release(&(*mt
)->plane
[1]);
981 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
982 free((*mt
)->level
[i
].slice
);
992 intel_get_image_dims(struct gl_texture_image
*image
,
993 int *width
, int *height
, int *depth
)
995 switch (image
->TexObject
->Target
) {
996 case GL_TEXTURE_1D_ARRAY
:
997 /* For a 1D Array texture the OpenGL API will treat the image height as
998 * the number of array slices. For Intel hardware, we treat the 1D array
999 * as a 2D Array with a height of 1. So, here we want to swap image
1002 assert(image
->Depth
== 1);
1003 *width
= image
->Width
;
1005 *depth
= image
->Height
;
1007 case GL_TEXTURE_CUBE_MAP
:
1008 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1009 * though we really have 6 slices.
1011 assert(image
->Depth
== 1);
1012 *width
= image
->Width
;
1013 *height
= image
->Height
;
1017 *width
= image
->Width
;
1018 *height
= image
->Height
;
1019 *depth
= image
->Depth
;
1025 * Can the image be pulled into a unified mipmap tree? This mirrors
1026 * the completeness test in a lot of ways.
1028 * Not sure whether I want to pass gl_texture_image here.
1031 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1032 struct gl_texture_image
*image
)
1034 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1035 GLuint level
= intelImage
->base
.Base
.Level
;
1036 int width
, height
, depth
;
1038 /* glTexImage* choose the texture object based on the target passed in, and
1039 * objects can't change targets over their lifetimes, so this should be
1042 assert(image
->TexObject
->Target
== mt
->target
);
1044 mesa_format mt_format
= mt
->format
;
1045 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1046 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1047 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1048 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1049 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1050 mt_format
= mt
->etc_format
;
1052 if (image
->TexFormat
!= mt_format
)
1055 intel_get_image_dims(image
, &width
, &height
, &depth
);
1057 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1060 int level_depth
= mt
->level
[level
].depth
;
1061 if (mt
->num_samples
> 1) {
1062 switch (mt
->msaa_layout
) {
1063 case INTEL_MSAA_LAYOUT_NONE
:
1064 case INTEL_MSAA_LAYOUT_IMS
:
1066 case INTEL_MSAA_LAYOUT_UMS
:
1067 case INTEL_MSAA_LAYOUT_CMS
:
1068 level_depth
/= mt
->num_samples
;
1073 /* Test image dimensions against the base level image adjusted for
1074 * minification. This will also catch images not present in the
1075 * tree, changed targets, etc.
1077 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1078 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1079 depth
!= level_depth
) {
1083 if (image
->NumSamples
!= mt
->num_samples
)
1091 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1093 GLuint x
, GLuint y
, GLuint d
)
1095 mt
->level
[level
].depth
= d
;
1096 mt
->level
[level
].level_x
= x
;
1097 mt
->level
[level
].level_y
= y
;
1099 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1102 assert(mt
->level
[level
].slice
== NULL
);
1104 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
1105 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1106 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1111 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1112 GLuint level
, GLuint img
,
1115 if (img
== 0 && level
== 0)
1116 assert(x
== 0 && y
== 0);
1118 assert(img
< mt
->level
[level
].depth
);
1120 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1121 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1123 DBG("%s level %d img %d pos %d,%d\n",
1124 __func__
, level
, img
,
1125 mt
->level
[level
].slice
[img
].x_offset
,
1126 mt
->level
[level
].slice
[img
].y_offset
);
1130 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1131 GLuint level
, GLuint slice
,
1132 GLuint
*x
, GLuint
*y
)
1134 assert(slice
< mt
->level
[level
].depth
);
1136 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1137 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1142 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1143 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1144 * and tile_h is set to 1.
1147 intel_get_tile_dims(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1148 uint32_t *tile_w
, uint32_t *tile_h
)
1150 if (tr_mode
== INTEL_MIPTREE_TRMODE_NONE
) {
1160 case I915_TILING_NONE
:
1165 unreachable("not reached");
1168 uint32_t aspect_ratio
= 1;
1169 assert(_mesa_is_pow_two(cpp
));
1184 unreachable("not reached");
1187 if (cpp
== 2 || cpp
== 8)
1190 if (tr_mode
== INTEL_MIPTREE_TRMODE_YS
)
1193 *tile_w
= *tile_h
* aspect_ratio
* cpp
;
1199 * This function computes masks that may be used to select the bits of the X
1200 * and Y coordinates that indicate the offset within a tile. If the BO is
1201 * untiled, the masks are set to 0.
1204 intel_get_tile_masks(uint32_t tiling
, uint32_t tr_mode
, uint32_t cpp
,
1205 uint32_t *mask_x
, uint32_t *mask_y
)
1207 uint32_t tile_w_bytes
, tile_h
;
1209 intel_get_tile_dims(tiling
, tr_mode
, cpp
, &tile_w_bytes
, &tile_h
);
1211 *mask_x
= tile_w_bytes
/ cpp
- 1;
1212 *mask_y
= tile_h
- 1;
1216 * Compute the offset (in bytes) from the start of the BO to the given x
1217 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1218 * multiples of the tile size.
1221 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1222 uint32_t x
, uint32_t y
)
1225 uint32_t pitch
= mt
->pitch
;
1226 uint32_t tiling
= mt
->tiling
;
1230 unreachable("not reached");
1231 case I915_TILING_NONE
:
1232 return y
* pitch
+ x
* cpp
;
1234 assert((x
% (512 / cpp
)) == 0);
1235 assert((y
% 8) == 0);
1236 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1238 assert((x
% (128 / cpp
)) == 0);
1239 assert((y
% 32) == 0);
1240 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1245 * Rendering with tiled buffers requires that the base address of the buffer
1246 * be aligned to a page boundary. For renderbuffers, and sometimes with
1247 * textures, we may want the surface to point at a texture image level that
1248 * isn't at a page boundary.
1250 * This function returns an appropriately-aligned base offset
1251 * according to the tiling restrictions, plus any required x/y offset
1255 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1256 GLuint level
, GLuint slice
,
1261 uint32_t mask_x
, mask_y
;
1263 intel_get_tile_masks(mt
->tiling
, mt
->tr_mode
, mt
->cpp
, &mask_x
, &mask_y
);
1264 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1266 *tile_x
= x
& mask_x
;
1267 *tile_y
= y
& mask_y
;
1269 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1273 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1274 struct intel_mipmap_tree
*dst_mt
,
1275 struct intel_mipmap_tree
*src_mt
,
1282 ptrdiff_t src_stride
, dst_stride
;
1283 int cpp
= dst_mt
->cpp
;
1285 intel_miptree_map(brw
, src_mt
,
1289 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1292 intel_miptree_map(brw
, dst_mt
,
1296 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1300 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1301 _mesa_get_format_name(src_mt
->format
),
1302 src_mt
, src
, src_stride
,
1303 _mesa_get_format_name(dst_mt
->format
),
1304 dst_mt
, dst
, dst_stride
,
1307 int row_size
= cpp
* width
;
1308 if (src_stride
== row_size
&&
1309 dst_stride
== row_size
) {
1310 memcpy(dst
, src
, row_size
* height
);
1312 for (int i
= 0; i
< height
; i
++) {
1313 memcpy(dst
, src
, row_size
);
1319 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1320 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1322 /* Don't forget to copy the stencil data over, too. We could have skipped
1323 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1324 * shuffling the two data sources in/out of temporary storage instead of
1325 * the direct mapping we get this way.
1327 if (dst_mt
->stencil_mt
) {
1328 assert(src_mt
->stencil_mt
);
1329 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1330 level
, slice
, width
, height
);
1335 intel_miptree_copy_slice(struct brw_context
*brw
,
1336 struct intel_mipmap_tree
*dst_mt
,
1337 struct intel_mipmap_tree
*src_mt
,
1343 mesa_format format
= src_mt
->format
;
1344 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1345 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1353 assert(depth
< src_mt
->level
[level
].depth
);
1354 assert(src_mt
->format
== dst_mt
->format
);
1356 if (dst_mt
->compressed
) {
1358 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1359 height
= ALIGN_NPOT(height
, j
) / j
;
1360 width
= ALIGN_NPOT(width
, i
) / i
;
1363 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1364 * below won't apply since we can't do the depth's Y tiling or the
1365 * stencil's W tiling in the blitter.
1367 if (src_mt
->stencil_mt
) {
1368 intel_miptree_copy_slice_sw(brw
,
1375 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1376 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1377 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1379 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1380 _mesa_get_format_name(src_mt
->format
),
1381 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1382 _mesa_get_format_name(dst_mt
->format
),
1383 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1386 if (!intel_miptree_blit(brw
,
1387 src_mt
, level
, slice
, 0, 0, false,
1388 dst_mt
, level
, slice
, 0, 0, false,
1389 width
, height
, GL_COPY
)) {
1390 perf_debug("miptree validate blit for %s failed\n",
1391 _mesa_get_format_name(format
));
1393 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1399 * Copies the image's current data to the given miptree, and associates that
1400 * miptree with the image.
1402 * If \c invalidate is true, then the actual image data does not need to be
1403 * copied, but the image still needs to be associated to the new miptree (this
1404 * is set to true if we're about to clear the image).
1407 intel_miptree_copy_teximage(struct brw_context
*brw
,
1408 struct intel_texture_image
*intelImage
,
1409 struct intel_mipmap_tree
*dst_mt
,
1412 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1413 struct intel_texture_object
*intel_obj
=
1414 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1415 int level
= intelImage
->base
.Base
.Level
;
1416 int face
= intelImage
->base
.Base
.Face
;
1419 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
)
1420 depth
= intelImage
->base
.Base
.Height
;
1422 depth
= intelImage
->base
.Base
.Depth
;
1425 for (int slice
= 0; slice
< depth
; slice
++) {
1426 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1430 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1431 intel_obj
->needs_validate
= true;
1435 intel_miptree_init_mcs(struct brw_context
*brw
,
1436 struct intel_mipmap_tree
*mt
,
1439 assert(mt
->mcs_buf
!= NULL
);
1441 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1443 * When MCS buffer is enabled and bound to MSRT, it is required that it
1444 * is cleared prior to any rendering.
1446 * Since we don't use the MCS buffer for any purpose other than rendering,
1447 * it makes sense to just clear it immediately upon allocation.
1449 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1451 const int ret
= brw_bo_map_gtt(brw
, mt
->mcs_buf
->bo
, "miptree");
1452 if (unlikely(ret
)) {
1453 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1454 drm_intel_bo_unreference(mt
->mcs_buf
->bo
);
1458 void *data
= mt
->mcs_buf
->bo
->virtual;
1459 memset(data
, init_value
, mt
->mcs_buf
->size
);
1460 drm_intel_bo_unmap(mt
->mcs_buf
->bo
);
1463 static struct intel_miptree_aux_buffer
*
1464 intel_mcs_miptree_buf_create(struct brw_context
*brw
,
1465 struct intel_mipmap_tree
*mt
,
1468 unsigned mcs_height
,
1469 uint32_t layout_flags
)
1471 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1472 struct intel_mipmap_tree
*temp_mt
;
1477 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1479 * "The MCS surface must be stored as Tile Y."
1481 layout_flags
|= MIPTREE_LAYOUT_TILING_Y
;
1482 temp_mt
= miptree_create(brw
,
1490 0 /* num_samples */,
1497 buf
->bo
= temp_mt
->bo
;
1498 buf
->offset
= temp_mt
->offset
;
1499 buf
->size
= temp_mt
->total_height
* temp_mt
->pitch
;
1500 buf
->pitch
= temp_mt
->pitch
;
1501 buf
->qpitch
= temp_mt
->qpitch
;
1503 /* Just hang on to the BO which backs the AUX buffer; the rest of the miptree
1504 * structure should go away. We use miptree create simply as a means to make
1505 * sure all the constraints for the buffer are satisfied.
1507 drm_intel_bo_reference(temp_mt
->bo
);
1508 intel_miptree_release(&temp_mt
);
1514 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1515 struct intel_mipmap_tree
*mt
,
1518 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1519 assert(mt
->mcs_buf
== NULL
);
1520 assert(!mt
->disable_aux_buffers
);
1522 /* Choose the correct format for the MCS buffer. All that really matters
1523 * is that we allocate the right buffer size, since we'll always be
1524 * accessing this miptree using MCS-specific hardware mechanisms, which
1525 * infer the correct format based on num_samples.
1528 switch (num_samples
) {
1531 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1534 format
= MESA_FORMAT_R_UNORM8
;
1537 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1538 * for each sample, plus 8 padding bits).
1540 format
= MESA_FORMAT_R_UINT32
;
1543 /* 64 bits/pixel are required for MCS data when using 16x MSAA (4 bits
1546 format
= MESA_FORMAT_RG_UINT32
;
1549 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1553 intel_mcs_miptree_buf_create(brw
, mt
,
1556 mt
->logical_height0
,
1557 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
);
1561 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1563 /* Multisampled miptrees are only supported for single level. */
1564 assert(mt
->first_level
== 0);
1565 intel_miptree_set_fast_clear_state(brw
, mt
, mt
->first_level
, 0,
1567 INTEL_FAST_CLEAR_STATE_CLEAR
);
1574 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1575 struct intel_mipmap_tree
*mt
,
1576 bool is_lossless_compressed
)
1578 assert(mt
->mcs_buf
== NULL
);
1579 assert(!mt
->disable_aux_buffers
);
1580 assert(!mt
->no_ccs
);
1582 struct isl_surf temp_main_surf
;
1583 struct isl_surf temp_ccs_surf
;
1585 /* Create first an ISL presentation for the main color surface and let ISL
1586 * calculate equivalent CCS surface against it.
1588 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1589 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_ccs_surf
))
1592 assert(temp_ccs_surf
.size
&&
1593 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1595 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1599 buf
->size
= temp_ccs_surf
.size
;
1600 buf
->pitch
= temp_ccs_surf
.row_pitch
;
1601 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(&temp_ccs_surf
);
1603 /* In case of compression mcs buffer needs to be initialised requiring the
1604 * buffer to be immediately mapped to cpu space for writing. Therefore do
1605 * not use the gpu access flag which can cause an unnecessary delay if the
1606 * backing pages happened to be just used by the GPU.
1608 const uint32_t alloc_flags
=
1609 is_lossless_compressed
? 0 : BO_ALLOC_FOR_RENDER
;
1610 uint32_t tiling
= I915_TILING_Y
;
1611 unsigned long pitch
;
1613 /* ISL has stricter set of alignment rules then the drm allocator.
1614 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1615 * trying to recalculate based on different format block sizes.
1617 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "ccs-miptree",
1618 buf
->pitch
, buf
->size
/ buf
->pitch
,
1619 1, &tiling
, &pitch
, alloc_flags
);
1621 assert(pitch
== buf
->pitch
);
1622 assert(tiling
== I915_TILING_Y
);
1630 /* From Gen9 onwards single-sampled (non-msrt) auxiliary buffers are
1631 * used for lossless compression which requires similar initialisation
1632 * as multi-sample compression.
1634 if (is_lossless_compressed
) {
1635 /* Hardware sets the auxiliary buffer to all zeroes when it does full
1636 * resolve. Initialize it accordingly in case the first renderer is
1637 * cpu (or other none compression aware party).
1639 * This is also explicitly stated in the spec (MCS Buffer for Render
1641 * "If Software wants to enable Color Compression without Fast clear,
1642 * Software needs to initialize MCS with zeros."
1644 intel_miptree_init_mcs(brw
, mt
, 0);
1645 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_CMS
;
1652 * Helper for intel_miptree_alloc_hiz() that sets
1653 * \c mt->level[level].has_hiz. Return true if and only if
1654 * \c has_hiz was set.
1657 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1658 struct intel_mipmap_tree
*mt
,
1661 assert(mt
->hiz_buf
);
1663 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1664 uint32_t width
= minify(mt
->physical_width0
, level
);
1665 uint32_t height
= minify(mt
->physical_height0
, level
);
1667 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1668 * and the height is 4 aligned. This allows our HiZ support
1669 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1670 * we can grow the width & height to allow the HiZ op to
1671 * force the proper size alignments.
1673 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1674 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1679 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1680 mt
->level
[level
].has_hiz
= true;
1686 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1687 * buffer dimensions and allocates a bo for the hiz buffer.
1689 static struct intel_miptree_hiz_buffer
*
1690 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1691 struct intel_mipmap_tree
*mt
)
1693 unsigned z_width
= mt
->logical_width0
;
1694 unsigned z_height
= mt
->logical_height0
;
1695 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1696 unsigned hz_width
, hz_height
;
1697 struct intel_miptree_hiz_buffer
*buf
= calloc(sizeof(*buf
), 1);
1702 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1703 * adjustments required for Z_Height and Z_Width based on multisampling.
1705 switch (mt
->num_samples
) {
1719 unreachable("unsupported sample count");
1722 const unsigned vertical_align
= 8; /* 'j' in the docs */
1723 const unsigned H0
= z_height
;
1724 const unsigned h0
= ALIGN(H0
, vertical_align
);
1725 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1726 const unsigned Z0
= z_depth
;
1728 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1729 hz_width
= ALIGN(z_width
, 16);
1731 if (mt
->target
== GL_TEXTURE_3D
) {
1735 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1736 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1737 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1738 hz_height
+= h_i
* Z_i
;
1739 H_i
= minify(H_i
, 1);
1740 Z_i
= minify(Z_i
, 1);
1743 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1745 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1747 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1748 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1749 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1752 unsigned long pitch
;
1753 uint32_t tiling
= I915_TILING_Y
;
1754 buf
->aux_base
.bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1755 hz_width
, hz_height
, 1,
1757 BO_ALLOC_FOR_RENDER
);
1758 if (!buf
->aux_base
.bo
) {
1761 } else if (tiling
!= I915_TILING_Y
) {
1762 drm_intel_bo_unreference(buf
->aux_base
.bo
);
1767 buf
->aux_base
.size
= hz_width
* hz_height
;
1768 buf
->aux_base
.pitch
= pitch
;
1775 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1776 * buffer dimensions and allocates a bo for the hiz buffer.
1778 static struct intel_miptree_hiz_buffer
*
1779 intel_gen8_hiz_buf_create(struct brw_context
*brw
,
1780 struct intel_mipmap_tree
*mt
)
1782 unsigned z_width
= mt
->logical_width0
;
1783 unsigned z_height
= mt
->logical_height0
;
1784 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1785 unsigned hz_width
, hz_height
;
1786 struct intel_miptree_hiz_buffer
*buf
= calloc(sizeof(*buf
), 1);
1791 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1792 * adjustments required for Z_Height and Z_Width based on multisampling.
1795 switch (mt
->num_samples
) {
1809 unreachable("unsupported sample count");
1813 const unsigned vertical_align
= 8; /* 'j' in the docs */
1814 const unsigned H0
= z_height
;
1815 const unsigned h0
= ALIGN(H0
, vertical_align
);
1816 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1817 const unsigned Z0
= z_depth
;
1819 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1820 hz_width
= ALIGN(z_width
, 16);
1824 unsigned sum_h_i
= 0;
1825 unsigned hz_height_3d_sum
= 0;
1826 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1827 unsigned i
= level
- mt
->first_level
;
1828 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1829 /* sum(i=2 to m; h_i) */
1833 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1834 hz_height_3d_sum
+= h_i
* Z_i
;
1835 H_i
= minify(H_i
, 1);
1836 Z_i
= minify(Z_i
, 1);
1838 /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
1839 buf
->aux_base
.qpitch
= h0
+ MAX2(h1
, sum_h_i
);
1841 if (mt
->target
== GL_TEXTURE_3D
) {
1842 /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1843 hz_height
= DIV_ROUND_UP(hz_height_3d_sum
, 2);
1845 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
1846 hz_height
= DIV_ROUND_UP(buf
->aux_base
.qpitch
, 2 * 8) * 8 * Z0
;
1849 unsigned long pitch
;
1850 uint32_t tiling
= I915_TILING_Y
;
1851 buf
->aux_base
.bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1852 hz_width
, hz_height
, 1,
1854 BO_ALLOC_FOR_RENDER
);
1855 if (!buf
->aux_base
.bo
) {
1858 } else if (tiling
!= I915_TILING_Y
) {
1859 drm_intel_bo_unreference(buf
->aux_base
.bo
);
1864 buf
->aux_base
.size
= hz_width
* hz_height
;
1865 buf
->aux_base
.pitch
= pitch
;
1871 static struct intel_miptree_hiz_buffer
*
1872 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
1873 struct intel_mipmap_tree
*mt
)
1875 struct intel_miptree_hiz_buffer
*buf
= calloc(sizeof(*buf
), 1);
1876 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1879 layout_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
;
1884 layout_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
1885 buf
->mt
= intel_miptree_create(brw
,
1891 mt
->logical_height0
,
1900 buf
->aux_base
.bo
= buf
->mt
->bo
;
1901 buf
->aux_base
.size
= buf
->mt
->total_height
* buf
->mt
->pitch
;
1902 buf
->aux_base
.pitch
= buf
->mt
->pitch
;
1903 buf
->aux_base
.qpitch
= buf
->mt
->qpitch
;
1909 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
1910 struct intel_mipmap_tree
*mt
)
1915 if (mt
->hiz_buf
!= NULL
)
1918 if (mt
->disable_aux_buffers
)
1921 switch (mt
->format
) {
1922 case MESA_FORMAT_Z_FLOAT32
:
1923 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
1924 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
1925 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
1926 case MESA_FORMAT_Z_UNORM16
:
1934 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1935 struct intel_mipmap_tree
*mt
)
1937 assert(mt
->hiz_buf
== NULL
);
1938 assert(!mt
->disable_aux_buffers
);
1940 if (brw
->gen
== 7) {
1941 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
1942 } else if (brw
->gen
>= 8) {
1943 mt
->hiz_buf
= intel_gen8_hiz_buf_create(brw
, mt
);
1945 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
1951 /* Mark that all slices need a HiZ resolve. */
1952 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1953 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
1956 for (unsigned layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1957 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
1958 exec_node_init(&m
->link
);
1961 m
->need
= BLORP_HIZ_OP_HIZ_RESOLVE
;
1963 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
1971 * Can the miptree sample using the hiz buffer?
1974 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1975 struct intel_mipmap_tree
*mt
)
1977 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
1978 * so keep things conservative for now and never enable it unless we're SKL+.
1988 /* It seems the hardware won't fallback to the depth buffer if some of the
1989 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1990 * of the texture to be HiZ enabled.
1992 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1993 if (!intel_miptree_level_has_hiz(mt
, level
))
1997 /* If compressed multisampling is enabled, then we use it for the auxiliary
2000 * From the BDW PRM (Volume 2d: Command Reference: Structures
2001 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
2003 * "If this field is set to AUX_HIZ, Number of Multisamples must be
2004 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
2006 * There is no such blurb for 1D textures, but there is sufficient evidence
2007 * that this is broken on SKL+.
2009 return (mt
->num_samples
<= 1 &&
2010 mt
->target
!= GL_TEXTURE_3D
&&
2011 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
2015 * Does the miptree slice have hiz enabled?
2018 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
2020 intel_miptree_check_level_layer(mt
, level
, 0);
2021 return mt
->level
[level
].has_hiz
;
2025 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
2029 if (!intel_miptree_level_has_hiz(mt
, level
))
2032 intel_resolve_map_set(&mt
->hiz_map
,
2033 level
, layer
, BLORP_HIZ_OP_HIZ_RESOLVE
);
2038 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
2042 if (!intel_miptree_level_has_hiz(mt
, level
))
2045 intel_resolve_map_set(&mt
->hiz_map
,
2046 level
, layer
, BLORP_HIZ_OP_DEPTH_RESOLVE
);
2050 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
2054 uint32_t end_layer
= mt
->level
[level
].depth
;
2056 for (layer
= 0; layer
< end_layer
; layer
++) {
2057 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
2062 intel_miptree_slice_resolve(struct brw_context
*brw
,
2063 struct intel_mipmap_tree
*mt
,
2066 enum blorp_hiz_op need
)
2068 intel_miptree_check_level_layer(mt
, level
, layer
);
2070 struct intel_resolve_map
*item
=
2071 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
2073 if (!item
|| item
->need
!= need
)
2076 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
2077 intel_resolve_map_remove(item
);
2082 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
2083 struct intel_mipmap_tree
*mt
,
2087 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
2088 BLORP_HIZ_OP_HIZ_RESOLVE
);
2092 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
2093 struct intel_mipmap_tree
*mt
,
2097 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
2098 BLORP_HIZ_OP_DEPTH_RESOLVE
);
2102 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
2103 struct intel_mipmap_tree
*mt
,
2104 enum blorp_hiz_op need
)
2106 bool did_resolve
= false;
2108 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
2109 if (map
->need
!= need
)
2112 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
2113 intel_resolve_map_remove(map
);
2121 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
2122 struct intel_mipmap_tree
*mt
)
2124 return intel_miptree_all_slices_resolve(brw
, mt
,
2125 BLORP_HIZ_OP_HIZ_RESOLVE
);
2129 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
2130 struct intel_mipmap_tree
*mt
)
2132 return intel_miptree_all_slices_resolve(brw
, mt
,
2133 BLORP_HIZ_OP_DEPTH_RESOLVE
);
2136 enum intel_fast_clear_state
2137 intel_miptree_get_fast_clear_state(const struct intel_mipmap_tree
*mt
,
2138 unsigned level
, unsigned layer
)
2140 intel_miptree_check_level_layer(mt
, level
, layer
);
2142 const struct intel_resolve_map
*item
=
2143 intel_resolve_map_const_get(&mt
->color_resolve_map
, level
, layer
);
2146 return INTEL_FAST_CLEAR_STATE_RESOLVED
;
2148 return item
->fast_clear_state
;
2152 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2153 const struct intel_mipmap_tree
*mt
,
2154 unsigned level
, unsigned layer
)
2156 if (mt
->no_ccs
|| !mt
->mcs_buf
)
2159 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2160 assert(brw
->gen
>= 8 ||
2161 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2163 /* Compression of arrayed msaa surfaces is supported. */
2164 if (mt
->num_samples
> 1)
2167 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2168 assert(brw
->gen
>= 8 || (layer
== 0 && mt
->logical_depth0
== 1));
2175 intel_miptree_set_fast_clear_state(const struct brw_context
*brw
,
2176 struct intel_mipmap_tree
*mt
,
2178 unsigned first_layer
,
2179 unsigned num_layers
,
2180 enum intel_fast_clear_state new_state
)
2182 /* Setting the state to resolved means removing the item from the list
2185 assert(new_state
!= INTEL_FAST_CLEAR_STATE_RESOLVED
);
2187 intel_miptree_check_color_resolve(brw
, mt
, level
, first_layer
);
2189 assert(first_layer
+ num_layers
<= mt
->physical_depth0
);
2191 for (unsigned i
= 0; i
< num_layers
; i
++)
2192 intel_resolve_map_set(&mt
->color_resolve_map
, level
,
2193 first_layer
+ i
, new_state
);
2197 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
2198 unsigned start_level
, unsigned num_levels
,
2199 unsigned start_layer
, unsigned num_layers
)
2201 return intel_resolve_map_find_any(&mt
->color_resolve_map
,
2202 start_level
, num_levels
,
2203 start_layer
, num_layers
) != NULL
;
2207 intel_miptree_used_for_rendering(const struct brw_context
*brw
,
2208 struct intel_mipmap_tree
*mt
, unsigned level
,
2209 unsigned start_layer
, unsigned num_layers
)
2211 const bool is_lossless_compressed
=
2212 intel_miptree_is_lossless_compressed(brw
, mt
);
2214 for (unsigned i
= 0; i
< num_layers
; ++i
) {
2215 const enum intel_fast_clear_state fast_clear_state
=
2216 intel_miptree_get_fast_clear_state(mt
, level
, start_layer
+ i
);
2218 /* If the buffer was previously in fast clear state, change it to
2219 * unresolved state, since it won't be guaranteed to be clear after
2222 if (is_lossless_compressed
||
2223 fast_clear_state
== INTEL_FAST_CLEAR_STATE_CLEAR
) {
2224 intel_miptree_set_fast_clear_state(
2225 brw
, mt
, level
, start_layer
+ i
, 1,
2226 INTEL_FAST_CLEAR_STATE_UNRESOLVED
);
2232 intel_miptree_needs_color_resolve(const struct brw_context
*brw
,
2233 const struct intel_mipmap_tree
*mt
,
2239 const bool is_lossless_compressed
=
2240 intel_miptree_is_lossless_compressed(brw
, mt
);
2242 /* From gen9 onwards there is new compression scheme for single sampled
2243 * surfaces called "lossless compressed". These don't need to be always
2246 if ((flags
& INTEL_MIPTREE_IGNORE_CCS_E
) && is_lossless_compressed
)
2249 /* Fast color clear resolves only make sense for non-MSAA buffers. */
2250 if (mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_NONE
&& !is_lossless_compressed
)
2257 intel_miptree_resolve_color(struct brw_context
*brw
,
2258 struct intel_mipmap_tree
*mt
, unsigned level
,
2259 unsigned start_layer
, unsigned num_layers
,
2262 intel_miptree_check_color_resolve(brw
, mt
, level
, start_layer
);
2264 if (!intel_miptree_needs_color_resolve(brw
, mt
, flags
))
2267 /* Arrayed fast clear is only supported for gen8+. */
2268 assert(brw
->gen
>= 8 || num_layers
== 1);
2270 bool resolved
= false;
2271 for (unsigned i
= 0; i
< num_layers
; ++i
) {
2272 intel_miptree_check_level_layer(mt
, level
, start_layer
+ i
);
2274 struct intel_resolve_map
*item
=
2275 intel_resolve_map_get(&mt
->color_resolve_map
, level
,
2279 assert(item
->fast_clear_state
!= INTEL_FAST_CLEAR_STATE_RESOLVED
);
2281 brw_blorp_resolve_color(brw
, mt
, level
, start_layer
);
2282 intel_resolve_map_remove(item
);
2291 intel_miptree_all_slices_resolve_color(struct brw_context
*brw
,
2292 struct intel_mipmap_tree
*mt
,
2295 if (!intel_miptree_needs_color_resolve(brw
, mt
, flags
))
2298 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
,
2299 &mt
->color_resolve_map
) {
2300 assert(map
->fast_clear_state
!= INTEL_FAST_CLEAR_STATE_RESOLVED
);
2302 brw_blorp_resolve_color(brw
, mt
, map
->level
, map
->layer
);
2303 intel_resolve_map_remove(map
);
2308 * Make it possible to share the BO backing the given miptree with another
2309 * process or another miptree.
2311 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2312 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2313 * ensure that no MCS buffer gets allocated in the future.
2316 intel_miptree_make_shareable(struct brw_context
*brw
,
2317 struct intel_mipmap_tree
*mt
)
2319 /* MCS buffers are also used for multisample buffers, but we can't resolve
2320 * away a multisample MCS buffer because it's an integral part of how the
2321 * pixel data is stored. Fortunately this code path should never be
2322 * reached for multisample buffers.
2324 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
|| mt
->num_samples
<= 1);
2327 intel_miptree_all_slices_resolve_color(brw
, mt
, 0);
2329 drm_intel_bo_unreference(mt
->mcs_buf
->bo
);
2334 mt
->disable_aux_buffers
= true;
2339 * \brief Get pointer offset into stencil buffer.
2341 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2342 * must decode the tile's layout in software.
2345 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2347 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2349 * Even though the returned offset is always positive, the return type is
2351 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2352 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2355 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2357 uint32_t tile_size
= 4096;
2358 uint32_t tile_width
= 64;
2359 uint32_t tile_height
= 64;
2360 uint32_t row_size
= 64 * stride
;
2362 uint32_t tile_x
= x
/ tile_width
;
2363 uint32_t tile_y
= y
/ tile_height
;
2365 /* The byte's address relative to the tile's base addres. */
2366 uint32_t byte_x
= x
% tile_width
;
2367 uint32_t byte_y
= y
% tile_height
;
2369 uintptr_t u
= tile_y
* row_size
2370 + tile_x
* tile_size
2371 + 512 * (byte_x
/ 8)
2373 + 32 * ((byte_y
/ 4) % 2)
2374 + 16 * ((byte_x
/ 4) % 2)
2375 + 8 * ((byte_y
/ 2) % 2)
2376 + 4 * ((byte_x
/ 2) % 2)
2381 /* adjust for bit6 swizzling */
2382 if (((byte_x
/ 8) % 2) == 1) {
2383 if (((byte_y
/ 8) % 2) == 0) {
2395 intel_miptree_updownsample(struct brw_context
*brw
,
2396 struct intel_mipmap_tree
*src
,
2397 struct intel_mipmap_tree
*dst
)
2399 brw_blorp_blit_miptrees(brw
,
2400 src
, 0 /* level */, 0 /* layer */,
2401 src
->format
, SWIZZLE_XYZW
,
2402 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2404 src
->logical_width0
, src
->logical_height0
,
2406 dst
->logical_width0
, dst
->logical_height0
,
2407 GL_NEAREST
, false, false /*mirror x, y*/,
2410 if (src
->stencil_mt
) {
2411 brw_blorp_blit_miptrees(brw
,
2412 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2413 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2414 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2415 dst
->stencil_mt
->format
,
2417 src
->logical_width0
, src
->logical_height0
,
2419 dst
->logical_width0
, dst
->logical_height0
,
2420 GL_NEAREST
, false, false /*mirror x, y*/,
2421 false, false /* decode/encode srgb */);
2426 intel_update_r8stencil(struct brw_context
*brw
,
2427 struct intel_mipmap_tree
*mt
)
2429 assert(brw
->gen
>= 7);
2430 struct intel_mipmap_tree
*src
=
2431 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2432 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
2435 if (!mt
->r8stencil_mt
) {
2436 const uint32_t r8stencil_flags
=
2437 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
| MIPTREE_LAYOUT_TILING_Y
|
2438 MIPTREE_LAYOUT_DISABLE_AUX
;
2439 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD */
2440 mt
->r8stencil_mt
= intel_miptree_create(brw
,
2442 MESA_FORMAT_R_UINT8
,
2445 src
->logical_width0
,
2446 src
->logical_height0
,
2447 src
->logical_depth0
,
2450 assert(mt
->r8stencil_mt
);
2453 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2455 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2456 const unsigned depth
= src
->level
[level
].depth
;
2457 const int layers_per_blit
=
2458 (dst
->msaa_layout
== INTEL_MSAA_LAYOUT_UMS
||
2459 dst
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) ?
2460 dst
->num_samples
: 1;
2462 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2463 brw_blorp_blit_miptrees(brw
,
2465 src
->format
, SWIZZLE_X
,
2466 dst
, level
, layers_per_blit
* layer
,
2467 MESA_FORMAT_R_UNORM8
,
2469 minify(src
->logical_width0
, level
),
2470 minify(src
->logical_height0
, level
),
2472 minify(dst
->logical_width0
, level
),
2473 minify(dst
->logical_height0
, level
),
2474 GL_NEAREST
, false, false /*mirror x, y*/,
2475 false, false /* decode/encode srgb */);
2479 brw_render_cache_set_check_flush(brw
, dst
->bo
);
2480 src
->r8stencil_needs_update
= false;
2484 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
2486 /* CPU accesses to color buffers don't understand fast color clears, so
2487 * resolve any pending fast color clears before we map.
2489 intel_miptree_all_slices_resolve_color(brw
, mt
, 0);
2491 drm_intel_bo
*bo
= mt
->bo
;
2493 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
2494 intel_batchbuffer_flush(brw
);
2496 if (mt
->tiling
!= I915_TILING_NONE
)
2497 brw_bo_map_gtt(brw
, bo
, "miptree");
2499 brw_bo_map(brw
, bo
, true, "miptree");
2505 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2507 drm_intel_bo_unmap(mt
->bo
);
2511 intel_miptree_map_gtt(struct brw_context
*brw
,
2512 struct intel_mipmap_tree
*mt
,
2513 struct intel_miptree_map
*map
,
2514 unsigned int level
, unsigned int slice
)
2516 unsigned int bw
, bh
;
2518 unsigned int image_x
, image_y
;
2519 intptr_t x
= map
->x
;
2520 intptr_t y
= map
->y
;
2522 /* For compressed formats, the stride is the number of bytes per
2523 * row of blocks. intel_miptree_get_image_offset() already does
2526 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2527 assert(y
% bh
== 0);
2528 assert(x
% bw
== 0);
2532 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
2537 /* Note that in the case of cube maps, the caller must have passed the
2538 * slice number referencing the face.
2540 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2544 map
->stride
= mt
->pitch
;
2545 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2548 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2549 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2550 map
->x
, map
->y
, map
->w
, map
->h
,
2551 mt
, _mesa_get_format_name(mt
->format
),
2552 x
, y
, map
->ptr
, map
->stride
);
2556 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2558 intel_miptree_unmap_raw(mt
);
2562 intel_miptree_map_blit(struct brw_context
*brw
,
2563 struct intel_mipmap_tree
*mt
,
2564 struct intel_miptree_map
*map
,
2565 unsigned int level
, unsigned int slice
)
2567 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2568 /* first_level */ 0,
2572 MIPTREE_LAYOUT_TILING_NONE
);
2574 if (!map
->linear_mt
) {
2575 fprintf(stderr
, "Failed to allocate blit temporary\n");
2578 map
->stride
= map
->linear_mt
->pitch
;
2580 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2581 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2582 * invalidate is set, since we'll be writing the whole rectangle from our
2583 * temporary buffer back out.
2585 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2586 if (!intel_miptree_blit(brw
,
2588 map
->x
, map
->y
, false,
2589 map
->linear_mt
, 0, 0,
2591 map
->w
, map
->h
, GL_COPY
)) {
2592 fprintf(stderr
, "Failed to blit\n");
2597 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
);
2599 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2600 map
->x
, map
->y
, map
->w
, map
->h
,
2601 mt
, _mesa_get_format_name(mt
->format
),
2602 level
, slice
, map
->ptr
, map
->stride
);
2607 intel_miptree_release(&map
->linear_mt
);
2613 intel_miptree_unmap_blit(struct brw_context
*brw
,
2614 struct intel_mipmap_tree
*mt
,
2615 struct intel_miptree_map
*map
,
2619 struct gl_context
*ctx
= &brw
->ctx
;
2621 intel_miptree_unmap_raw(map
->linear_mt
);
2623 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2624 bool ok
= intel_miptree_blit(brw
,
2625 map
->linear_mt
, 0, 0,
2628 map
->x
, map
->y
, false,
2629 map
->w
, map
->h
, GL_COPY
);
2630 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2633 intel_miptree_release(&map
->linear_mt
);
2637 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2639 #if defined(USE_SSE41)
2641 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2642 struct intel_mipmap_tree
*mt
,
2643 struct intel_miptree_map
*map
,
2644 unsigned int level
, unsigned int slice
)
2646 assert(map
->mode
& GL_MAP_READ_BIT
);
2647 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2649 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2650 map
->x
, map
->y
, map
->w
, map
->h
,
2651 mt
, _mesa_get_format_name(mt
->format
),
2652 level
, slice
, map
->ptr
, map
->stride
);
2654 /* Map the original image */
2657 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2661 void *src
= intel_miptree_map_raw(brw
, mt
);
2667 src
+= image_y
* mt
->pitch
;
2668 src
+= image_x
* mt
->cpp
;
2670 /* Due to the pixel offsets for the particular image being mapped, our
2671 * src pointer may not be 16-byte aligned. However, if the pitch is
2672 * divisible by 16, then the amount by which it's misaligned will remain
2673 * consistent from row to row.
2675 assert((mt
->pitch
% 16) == 0);
2676 const int misalignment
= ((uintptr_t) src
) & 15;
2678 /* Create an untiled temporary buffer for the mapping. */
2679 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
2681 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
2683 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
2684 /* Offset the destination so it has the same misalignment as src. */
2685 map
->ptr
= map
->buffer
+ misalignment
;
2687 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
2689 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2690 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
2691 void *src_ptr
= src
+ y
* mt
->pitch
;
2693 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
2696 intel_miptree_unmap_raw(mt
);
2700 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
2701 struct intel_mipmap_tree
*mt
,
2702 struct intel_miptree_map
*map
,
2706 _mesa_align_free(map
->buffer
);
2713 intel_miptree_map_s8(struct brw_context
*brw
,
2714 struct intel_mipmap_tree
*mt
,
2715 struct intel_miptree_map
*map
,
2716 unsigned int level
, unsigned int slice
)
2718 map
->stride
= map
->w
;
2719 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2723 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2724 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2725 * invalidate is set, since we'll be writing the whole rectangle from our
2726 * temporary buffer back out.
2728 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2729 uint8_t *untiled_s8_map
= map
->ptr
;
2730 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2731 unsigned int image_x
, image_y
;
2733 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2735 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2736 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2737 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2738 x
+ image_x
+ map
->x
,
2739 y
+ image_y
+ map
->y
,
2740 brw
->has_swizzling
);
2741 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
2745 intel_miptree_unmap_raw(mt
);
2747 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
2748 map
->x
, map
->y
, map
->w
, map
->h
,
2749 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
2751 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2752 map
->x
, map
->y
, map
->w
, map
->h
,
2753 mt
, map
->ptr
, map
->stride
);
2758 intel_miptree_unmap_s8(struct brw_context
*brw
,
2759 struct intel_mipmap_tree
*mt
,
2760 struct intel_miptree_map
*map
,
2764 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2765 unsigned int image_x
, image_y
;
2766 uint8_t *untiled_s8_map
= map
->ptr
;
2767 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2769 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2771 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2772 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2773 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2774 image_x
+ x
+ map
->x
,
2775 image_y
+ y
+ map
->y
,
2776 brw
->has_swizzling
);
2777 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
2781 intel_miptree_unmap_raw(mt
);
2788 intel_miptree_map_etc(struct brw_context
*brw
,
2789 struct intel_mipmap_tree
*mt
,
2790 struct intel_miptree_map
*map
,
2794 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
2795 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
2796 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2799 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2800 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2802 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2803 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2804 map
->w
, map
->h
, 1));
2805 map
->ptr
= map
->buffer
;
2809 intel_miptree_unmap_etc(struct brw_context
*brw
,
2810 struct intel_mipmap_tree
*mt
,
2811 struct intel_miptree_map
*map
,
2817 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2822 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2823 + image_y
* mt
->pitch
2824 + image_x
* mt
->cpp
;
2826 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2827 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2828 map
->ptr
, map
->stride
,
2831 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2832 map
->ptr
, map
->stride
,
2833 map
->w
, map
->h
, mt
->etc_format
);
2835 intel_miptree_unmap_raw(mt
);
2840 * Mapping function for packed depth/stencil miptrees backed by real separate
2841 * miptrees for depth and stencil.
2843 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2844 * separate from the depth buffer. Yet at the GL API level, we have to expose
2845 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2846 * be able to map that memory for texture storage and glReadPixels-type
2847 * operations. We give Mesa core that access by mallocing a temporary and
2848 * copying the data between the actual backing store and the temporary.
2851 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2852 struct intel_mipmap_tree
*mt
,
2853 struct intel_miptree_map
*map
,
2854 unsigned int level
, unsigned int slice
)
2856 struct intel_mipmap_tree
*z_mt
= mt
;
2857 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2858 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2859 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2861 map
->stride
= map
->w
* packed_bpp
;
2862 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2866 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2867 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2868 * invalidate is set, since we'll be writing the whole rectangle from our
2869 * temporary buffer back out.
2871 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2872 uint32_t *packed_map
= map
->ptr
;
2873 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2874 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2875 unsigned int s_image_x
, s_image_y
;
2876 unsigned int z_image_x
, z_image_y
;
2878 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2879 &s_image_x
, &s_image_y
);
2880 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2881 &z_image_x
, &z_image_y
);
2883 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2884 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2885 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2886 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2889 brw
->has_swizzling
);
2890 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2892 (map_x
+ z_image_x
));
2893 uint8_t s
= s_map
[s_offset
];
2894 uint32_t z
= z_map
[z_offset
];
2896 if (map_z32f_x24s8
) {
2897 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2898 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2900 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2905 intel_miptree_unmap_raw(s_mt
);
2906 intel_miptree_unmap_raw(z_mt
);
2908 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2910 map
->x
, map
->y
, map
->w
, map
->h
,
2911 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2912 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2913 map
->ptr
, map
->stride
);
2915 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2916 map
->x
, map
->y
, map
->w
, map
->h
,
2917 mt
, map
->ptr
, map
->stride
);
2922 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2923 struct intel_mipmap_tree
*mt
,
2924 struct intel_miptree_map
*map
,
2928 struct intel_mipmap_tree
*z_mt
= mt
;
2929 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2930 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2932 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2933 uint32_t *packed_map
= map
->ptr
;
2934 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2935 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2936 unsigned int s_image_x
, s_image_y
;
2937 unsigned int z_image_x
, z_image_y
;
2939 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2940 &s_image_x
, &s_image_y
);
2941 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2942 &z_image_x
, &z_image_y
);
2944 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2945 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2946 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2947 x
+ s_image_x
+ map
->x
,
2948 y
+ s_image_y
+ map
->y
,
2949 brw
->has_swizzling
);
2950 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2952 (x
+ z_image_x
+ map
->x
));
2954 if (map_z32f_x24s8
) {
2955 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2956 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2958 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2959 s_map
[s_offset
] = packed
>> 24;
2960 z_map
[z_offset
] = packed
;
2965 intel_miptree_unmap_raw(s_mt
);
2966 intel_miptree_unmap_raw(z_mt
);
2968 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2970 map
->x
, map
->y
, map
->w
, map
->h
,
2971 z_mt
, _mesa_get_format_name(z_mt
->format
),
2972 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2973 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2974 map
->ptr
, map
->stride
);
2981 * Create and attach a map to the miptree at (level, slice). Return the
2984 static struct intel_miptree_map
*
2985 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2994 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2999 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3000 mt
->level
[level
].slice
[slice
].map
= map
;
3012 * Release the map at (level, slice).
3015 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3019 struct intel_miptree_map
**map
;
3021 map
= &mt
->level
[level
].slice
[slice
].map
;
3027 can_blit_slice(struct intel_mipmap_tree
*mt
,
3028 unsigned int level
, unsigned int slice
)
3030 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3031 if (mt
->pitch
>= 32768)
3038 use_intel_mipree_map_blit(struct brw_context
*brw
,
3039 struct intel_mipmap_tree
*mt
,
3045 /* It's probably not worth swapping to the blit ring because of
3046 * all the overhead involved. But, we must use blitter for the
3047 * surfaces with INTEL_MIPTREE_TRMODE_{YF,YS}.
3049 (!(mode
& GL_MAP_WRITE_BIT
) ||
3050 mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) &&
3052 (mt
->tiling
== I915_TILING_X
||
3053 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3054 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
) ||
3055 /* Fast copy blit on skl+ supports all tiling formats. */
3057 can_blit_slice(mt
, level
, slice
))
3060 if (mt
->tiling
!= I915_TILING_NONE
&&
3061 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3062 assert(can_blit_slice(mt
, level
, slice
));
3070 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3071 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3072 * arithmetic overflow.
3074 * If you call this function and use \a out_stride, then you're doing pointer
3075 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3076 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3077 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3078 * which usually have type uint32_t or GLuint.
3081 intel_miptree_map(struct brw_context
*brw
,
3082 struct intel_mipmap_tree
*mt
,
3091 ptrdiff_t *out_stride
)
3093 struct intel_miptree_map
*map
;
3095 assert(mt
->num_samples
<= 1);
3097 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3104 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
3105 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3106 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
3109 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3110 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3111 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3112 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3113 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3114 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3115 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3116 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3117 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3118 #if defined(USE_SSE41)
3119 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3120 !mt
->compressed
&& cpu_has_sse4_1
&&
3121 (mt
->pitch
% 16 == 0)) {
3122 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3125 /* intel_miptree_map_gtt() doesn't support surfaces with Yf/Ys tiling. */
3126 assert(mt
->tr_mode
== INTEL_MIPTREE_TRMODE_NONE
);
3127 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3130 *out_ptr
= map
->ptr
;
3131 *out_stride
= map
->stride
;
3133 if (map
->ptr
== NULL
)
3134 intel_miptree_release_map(mt
, level
, slice
);
3138 intel_miptree_unmap(struct brw_context
*brw
,
3139 struct intel_mipmap_tree
*mt
,
3143 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3145 assert(mt
->num_samples
<= 1);
3150 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3151 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3153 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3154 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3155 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3156 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3157 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3158 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3159 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3160 } else if (map
->linear_mt
) {
3161 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3162 #if defined(USE_SSE41)
3163 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3164 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3167 intel_miptree_unmap_gtt(mt
);
3170 intel_miptree_release_map(mt
, level
, slice
);
3174 get_isl_surf_dim(GLenum target
)
3178 case GL_TEXTURE_1D_ARRAY
:
3179 return ISL_SURF_DIM_1D
;
3182 case GL_TEXTURE_2D_ARRAY
:
3183 case GL_TEXTURE_RECTANGLE
:
3184 case GL_TEXTURE_CUBE_MAP
:
3185 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3186 case GL_TEXTURE_2D_MULTISAMPLE
:
3187 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3188 case GL_TEXTURE_EXTERNAL_OES
:
3189 return ISL_SURF_DIM_2D
;
3192 return ISL_SURF_DIM_3D
;
3195 unreachable("Invalid texture target");
3199 get_isl_dim_layout(const struct gen_device_info
*devinfo
, uint32_t tiling
,
3204 case GL_TEXTURE_1D_ARRAY
:
3205 return (devinfo
->gen
>= 9 && tiling
== I915_TILING_NONE
?
3206 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3209 case GL_TEXTURE_2D_ARRAY
:
3210 case GL_TEXTURE_RECTANGLE
:
3211 case GL_TEXTURE_2D_MULTISAMPLE
:
3212 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3213 case GL_TEXTURE_EXTERNAL_OES
:
3214 return ISL_DIM_LAYOUT_GEN4_2D
;
3216 case GL_TEXTURE_CUBE_MAP
:
3217 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3218 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3219 ISL_DIM_LAYOUT_GEN4_2D
);
3222 return (devinfo
->gen
>= 9 ?
3223 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3226 unreachable("Invalid texture target");
3230 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree
*mt
)
3232 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3233 return ISL_TILING_W
;
3235 switch (mt
->tiling
) {
3236 case I915_TILING_NONE
:
3237 return ISL_TILING_LINEAR
;
3239 return ISL_TILING_X
;
3241 switch (mt
->tr_mode
) {
3242 case INTEL_MIPTREE_TRMODE_NONE
:
3243 return ISL_TILING_Y0
;
3244 case INTEL_MIPTREE_TRMODE_YF
:
3245 return ISL_TILING_Yf
;
3246 case INTEL_MIPTREE_TRMODE_YS
:
3247 return ISL_TILING_Ys
;
3249 unreachable("Invalid tiled resource mode");
3252 unreachable("Invalid tiling mode");
3258 intel_miptree_get_isl_surf(struct brw_context
*brw
,
3259 const struct intel_mipmap_tree
*mt
,
3260 struct isl_surf
*surf
)
3262 surf
->dim
= get_isl_surf_dim(mt
->target
);
3263 surf
->dim_layout
= get_isl_dim_layout(&brw
->screen
->devinfo
,
3264 mt
->tiling
, mt
->target
);
3266 if (mt
->num_samples
> 1) {
3267 switch (mt
->msaa_layout
) {
3268 case INTEL_MSAA_LAYOUT_IMS
:
3269 surf
->msaa_layout
= ISL_MSAA_LAYOUT_INTERLEAVED
;
3271 case INTEL_MSAA_LAYOUT_UMS
:
3272 case INTEL_MSAA_LAYOUT_CMS
:
3273 surf
->msaa_layout
= ISL_MSAA_LAYOUT_ARRAY
;
3276 unreachable("Invalid MSAA layout");
3279 surf
->msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
3282 surf
->tiling
= intel_miptree_get_isl_tiling(mt
);
3284 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3285 /* The ISL definition of row_pitch matches the surface state pitch field
3286 * a bit better than intel_mipmap_tree. In particular, ISL incorporates
3287 * the factor of 2 for W-tiling in row_pitch.
3289 surf
->row_pitch
= 2 * mt
->pitch
;
3291 surf
->row_pitch
= mt
->pitch
;
3294 surf
->format
= translate_tex_format(brw
, mt
->format
, false);
3296 if (brw
->gen
>= 9) {
3297 if (surf
->dim
== ISL_SURF_DIM_1D
&& surf
->tiling
== ISL_TILING_LINEAR
) {
3298 /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
3299 surf
->image_alignment_el
= isl_extent3d(64, 1, 1);
3301 /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
3302 * alignment in terms of surface elements like we want.
3304 surf
->image_alignment_el
= isl_extent3d(mt
->halign
, mt
->valign
, 1);
3307 /* On earlier gens it's stored in pixels. */
3309 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3310 surf
->image_alignment_el
=
3311 isl_extent3d(mt
->halign
/ bw
, mt
->valign
/ bh
, 1);
3314 surf
->logical_level0_px
.width
= mt
->logical_width0
;
3315 surf
->logical_level0_px
.height
= mt
->logical_height0
;
3316 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3317 surf
->logical_level0_px
.depth
= mt
->logical_depth0
;
3318 surf
->logical_level0_px
.array_len
= 1;
3320 surf
->logical_level0_px
.depth
= 1;
3321 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
;
3324 surf
->phys_level0_sa
.width
= mt
->physical_width0
;
3325 surf
->phys_level0_sa
.height
= mt
->physical_height0
;
3326 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3327 surf
->phys_level0_sa
.depth
= mt
->physical_depth0
;
3328 surf
->phys_level0_sa
.array_len
= 1;
3330 surf
->phys_level0_sa
.depth
= 1;
3331 surf
->phys_level0_sa
.array_len
= mt
->physical_depth0
;
3334 surf
->levels
= mt
->last_level
+ 1;
3335 surf
->samples
= MAX2(mt
->num_samples
, 1);
3337 surf
->size
= 0; /* TODO */
3338 surf
->alignment
= 0; /* TODO */
3340 switch (surf
->dim_layout
) {
3341 case ISL_DIM_LAYOUT_GEN4_2D
:
3342 case ISL_DIM_LAYOUT_GEN4_3D
:
3343 if (brw
->gen
>= 9) {
3344 surf
->array_pitch_el_rows
= mt
->qpitch
;
3347 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3348 assert(mt
->qpitch
% bh
== 0);
3349 surf
->array_pitch_el_rows
= mt
->qpitch
/ bh
;
3352 case ISL_DIM_LAYOUT_GEN9_1D
:
3353 surf
->array_pitch_el_rows
= 1;
3357 switch (mt
->array_layout
) {
3358 case ALL_LOD_IN_EACH_SLICE
:
3359 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_FULL
;
3361 case ALL_SLICES_AT_EACH_LOD
:
3362 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_COMPACT
;
3365 unreachable("Invalid array layout");
3368 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
3369 switch (base_format
) {
3370 case GL_DEPTH_COMPONENT
:
3371 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
3373 case GL_STENCIL_INDEX
:
3374 surf
->usage
= ISL_SURF_USAGE_STENCIL_BIT
;
3376 surf
->usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
3378 case GL_DEPTH_STENCIL
:
3379 /* In this case we only texture from the depth part */
3380 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
|
3381 ISL_SURF_USAGE_TEXTURE_BIT
;
3384 surf
->usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
3385 if (brw
->format_supported_as_render_target
[mt
->format
])
3386 surf
->usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
3390 if (_mesa_is_cube_map_texture(mt
->target
))
3391 surf
->usage
|= ISL_SURF_USAGE_CUBE_BIT
;
3394 /* WARNING: THE SURFACE CREATED BY THIS FUNCTION IS NOT COMPLETE AND CANNOT BE
3395 * USED FOR ANY REAL CALCULATIONS. THE ONLY VALID USE OF SUCH A SURFACE IS TO
3396 * PASS IT INTO isl_surf_fill_state.
3399 intel_miptree_get_aux_isl_surf(struct brw_context
*brw
,
3400 const struct intel_mipmap_tree
*mt
,
3401 struct isl_surf
*surf
,
3402 enum isl_aux_usage
*usage
)
3404 uint32_t aux_pitch
, aux_qpitch
;
3406 aux_pitch
= mt
->mcs_buf
->pitch
;
3407 aux_qpitch
= mt
->mcs_buf
->qpitch
;
3409 if (mt
->num_samples
> 1) {
3410 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
);
3411 *usage
= ISL_AUX_USAGE_MCS
;
3412 } else if (intel_miptree_is_lossless_compressed(brw
, mt
)) {
3413 assert(brw
->gen
>= 9);
3414 *usage
= ISL_AUX_USAGE_CCS_E
;
3415 } else if (!mt
->no_ccs
) {
3416 *usage
= ISL_AUX_USAGE_CCS_D
;
3418 unreachable("Invalid MCS miptree");
3420 } else if (mt
->hiz_buf
) {
3421 if (mt
->hiz_buf
->mt
) {
3422 aux_pitch
= mt
->hiz_buf
->mt
->pitch
;
3423 aux_qpitch
= mt
->hiz_buf
->mt
->qpitch
;
3425 aux_pitch
= mt
->hiz_buf
->aux_base
.pitch
;
3426 aux_qpitch
= mt
->hiz_buf
->aux_base
.qpitch
;
3429 *usage
= ISL_AUX_USAGE_HIZ
;
3431 *usage
= ISL_AUX_USAGE_NONE
;
3435 /* Start with a copy of the original surface. */
3436 intel_miptree_get_isl_surf(brw
, mt
, surf
);
3438 /* Figure out the format and tiling of the auxiliary surface */
3440 case ISL_AUX_USAGE_NONE
:
3441 unreachable("Invalid auxiliary usage");
3443 case ISL_AUX_USAGE_HIZ
:
3444 isl_surf_get_hiz_surf(&brw
->isl_dev
, surf
, surf
);
3447 case ISL_AUX_USAGE_MCS
:
3450 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
3451 * HALIGN 16 must be used."
3454 assert(mt
->halign
== 16);
3456 isl_surf_get_mcs_surf(&brw
->isl_dev
, surf
, surf
);
3459 case ISL_AUX_USAGE_CCS_D
:
3460 case ISL_AUX_USAGE_CCS_E
:
3462 * From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
3464 * "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
3466 * From the hardware spec for GEN9:
3468 * "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E,
3469 * HALIGN 16 must be used."
3471 assert(mt
->num_samples
<= 1);
3473 assert(mt
->halign
== 16);
3475 isl_surf_get_ccs_surf(&brw
->isl_dev
, surf
, surf
);
3479 /* We want the pitch of the actual aux buffer. */
3480 surf
->row_pitch
= aux_pitch
;
3482 /* Auxiliary surfaces in ISL have compressed formats and array_pitch_el_rows
3483 * is in elements. This doesn't match intel_mipmap_tree::qpitch which is
3484 * in elements of the primary color surface so we have to divide by the
3485 * compression block height.
3487 surf
->array_pitch_el_rows
=
3488 aux_qpitch
/ isl_format_get_layout(surf
->format
)->bh
;
3491 union isl_color_value
3492 intel_miptree_get_isl_clear_color(struct brw_context
*brw
,
3493 const struct intel_mipmap_tree
*mt
)
3495 union isl_color_value clear_color
;
3497 if (_mesa_get_format_base_format(mt
->format
) == GL_DEPTH_COMPONENT
) {
3498 clear_color
.i32
[0] = mt
->depth_clear_value
;
3499 clear_color
.i32
[1] = 0;
3500 clear_color
.i32
[2] = 0;
3501 clear_color
.i32
[3] = 0;
3502 } else if (brw
->gen
>= 9) {
3503 clear_color
.i32
[0] = mt
->gen9_fast_clear_color
.i
[0];
3504 clear_color
.i32
[1] = mt
->gen9_fast_clear_color
.i
[1];
3505 clear_color
.i32
[2] = mt
->gen9_fast_clear_color
.i
[2];
3506 clear_color
.i32
[3] = mt
->gen9_fast_clear_color
.i
[3];
3507 } else if (_mesa_is_format_integer(mt
->format
)) {
3508 clear_color
.i32
[0] = (mt
->fast_clear_color_value
& (1u << 31)) != 0;
3509 clear_color
.i32
[1] = (mt
->fast_clear_color_value
& (1u << 30)) != 0;
3510 clear_color
.i32
[2] = (mt
->fast_clear_color_value
& (1u << 29)) != 0;
3511 clear_color
.i32
[3] = (mt
->fast_clear_color_value
& (1u << 28)) != 0;
3513 clear_color
.f32
[0] = (mt
->fast_clear_color_value
& (1u << 31)) != 0;
3514 clear_color
.f32
[1] = (mt
->fast_clear_color_value
& (1u << 30)) != 0;
3515 clear_color
.f32
[2] = (mt
->fast_clear_color_value
& (1u << 29)) != 0;
3516 clear_color
.f32
[3] = (mt
->fast_clear_color_value
& (1u << 28)) != 0;