2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_image.h"
31 #include "intel_mipmap_tree.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
,
55 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
58 intel_miptree_alloc_aux(struct brw_context
*brw
,
59 struct intel_mipmap_tree
*mt
);
62 intel_miptree_supports_mcs(struct brw_context
*brw
,
63 const struct intel_mipmap_tree
*mt
)
65 /* MCS compression only applies to multisampled miptrees */
66 if (mt
->surf
.samples
<= 1)
69 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
73 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
74 switch (_mesa_get_format_base_format(mt
->format
)) {
75 case GL_DEPTH_COMPONENT
:
76 case GL_STENCIL_INDEX
:
77 case GL_DEPTH_STENCIL
:
80 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
82 * This field must be set to 0 for all SINT MSRTs when all RT channels
85 * In practice this means that we have to disable MCS for all signed
86 * integer MSAA buffers. The alternative, to disable MCS only when one
87 * of the render target channels is disabled, is impractical because it
88 * would require converting between CMS and UMS MSAA layouts on the fly,
91 if (brw
->gen
== 7 && _mesa_get_format_datatype(mt
->format
) == GL_INT
) {
100 intel_tiling_supports_ccs(const struct brw_context
*brw
,
101 enum isl_tiling tiling
)
103 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
104 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
106 * - Support is limited to tiled render targets.
108 * Gen9 changes the restriction to Y-tile only.
111 return tiling
== ISL_TILING_Y0
;
112 else if (brw
->gen
>= 7)
113 return tiling
!= ISL_TILING_LINEAR
;
119 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
120 * can be used. This doesn't (and should not) inspect any of the properties of
123 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
124 * beneath the "Fast Color Clear" bullet (p326):
126 * - Support is for non-mip-mapped and non-array surface types only.
128 * And then later, on p327:
130 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
133 * From the Skylake documentation, it is made clear that X-tiling is no longer
136 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
140 intel_miptree_supports_ccs(struct brw_context
*brw
,
141 const struct intel_mipmap_tree
*mt
)
143 /* MCS support does not exist prior to Gen7 */
147 /* This function applies only to non-multisampled render targets. */
148 if (mt
->surf
.samples
> 1)
151 /* MCS is only supported for color buffers */
152 switch (_mesa_get_format_base_format(mt
->format
)) {
153 case GL_DEPTH_COMPONENT
:
154 case GL_DEPTH_STENCIL
:
155 case GL_STENCIL_INDEX
:
159 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
162 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
163 const bool arrayed
= mt
->surf
.logical_level0_px
.array_len
> 1 ||
164 mt
->surf
.logical_level0_px
.depth
> 1;
167 /* Multisample surfaces with the CMS layout are not layered surfaces,
168 * yet still have physical_depth0 > 1. Assert that we don't
169 * accidentally reject a multisampled surface here. We should have
170 * rejected it earlier by explicitly checking the sample count.
172 assert(mt
->surf
.samples
== 1);
175 /* Handle the hardware restrictions...
177 * All GENs have the following restriction: "MCS buffer for non-MSRT is
178 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
180 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
181 * Non-MultiSampler Render Target Restrictions) Support is for
182 * non-mip-mapped and non-array surface types only.
184 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
185 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
186 * surfaces are supported with MCS buffer layout with these alignments in
187 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
189 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
190 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
191 * surfaces are supported with MCS buffer layout with these alignments in
192 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
194 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
197 /* There's no point in using an MCS buffer if the surface isn't in a
200 if (!brw
->mesa_format_supports_render
[mt
->format
])
207 intel_tiling_supports_hiz(const struct brw_context
*brw
,
208 enum isl_tiling tiling
)
213 return tiling
== ISL_TILING_Y0
;
217 intel_miptree_supports_hiz(const struct brw_context
*brw
,
218 const struct intel_mipmap_tree
*mt
)
223 switch (mt
->format
) {
224 case MESA_FORMAT_Z_FLOAT32
:
225 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
226 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
227 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
228 case MESA_FORMAT_Z_UNORM16
:
236 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
237 const struct intel_mipmap_tree
*mt
)
242 /* For now compression is only enabled for integer formats even though
243 * there exist supported floating point formats also. This is a heuristic
244 * decision based on current public benchmarks. In none of the cases these
245 * formats provided any improvement but a few cases were seen to regress.
246 * Hence these are left to to be enabled in the future when they are known
249 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
252 if (!intel_miptree_supports_ccs(brw
, mt
))
255 /* Many window system buffers are sRGB even if they are never rendered as
256 * sRGB. For those, we want CCS_E for when sRGBEncode is false. When the
257 * surface is used as sRGB, we fall back to CCS_D.
259 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
260 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
261 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
265 * Determine depth format corresponding to a depth+stencil format,
266 * for separate stencil.
269 intel_depth_format_for_depthstencil_format(mesa_format format
) {
271 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
272 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
273 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
274 return MESA_FORMAT_Z_FLOAT32
;
281 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
282 unsigned depth0
, struct intel_mipmap_level
*table
)
284 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
286 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
288 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
289 if (!table
[level
].slice
)
296 for (unsigned level
= first_level
; level
<= last_level
; level
++)
297 free(table
[level
].slice
);
303 needs_separate_stencil(const struct brw_context
*brw
,
304 struct intel_mipmap_tree
*mt
,
307 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
310 if (brw
->must_use_separate_stencil
)
313 return brw
->has_separate_stencil
&&
314 intel_miptree_supports_hiz(brw
, mt
);
318 * Choose the aux usage for this miptree. This function must be called fairly
319 * late in the miptree create process after we have a tiling.
322 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
323 struct intel_mipmap_tree
*mt
)
325 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
327 if (intel_miptree_supports_mcs(brw
, mt
)) {
328 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
329 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
330 } else if (intel_tiling_supports_ccs(brw
, mt
->surf
.tiling
) &&
331 intel_miptree_supports_ccs(brw
, mt
)) {
332 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
333 intel_miptree_supports_ccs_e(brw
, mt
)) {
334 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
336 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
338 } else if (intel_tiling_supports_hiz(brw
, mt
->surf
.tiling
) &&
339 intel_miptree_supports_hiz(brw
, mt
)) {
340 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
343 /* We can do fast-clear on all auxiliary surface types that are
344 * allocated through the normal texture creation paths.
346 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
347 mt
->supports_fast_clear
= true;
352 * Choose an appropriate uncompressed format for a requested
353 * compressed format, if unsupported.
356 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
358 /* No need to lower ETC formats on these platforms,
359 * they are supported natively.
361 if (brw
->gen
>= 8 || brw
->is_baytrail
)
365 case MESA_FORMAT_ETC1_RGB8
:
366 return MESA_FORMAT_R8G8B8X8_UNORM
;
367 case MESA_FORMAT_ETC2_RGB8
:
368 return MESA_FORMAT_R8G8B8X8_UNORM
;
369 case MESA_FORMAT_ETC2_SRGB8
:
370 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
371 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
372 return MESA_FORMAT_B8G8R8A8_SRGB
;
373 case MESA_FORMAT_ETC2_RGBA8_EAC
:
374 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
375 return MESA_FORMAT_R8G8B8A8_UNORM
;
376 case MESA_FORMAT_ETC2_R11_EAC
:
377 return MESA_FORMAT_R_UNORM16
;
378 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
379 return MESA_FORMAT_R_SNORM16
;
380 case MESA_FORMAT_ETC2_RG11_EAC
:
381 return MESA_FORMAT_R16G16_UNORM
;
382 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
383 return MESA_FORMAT_R16G16_SNORM
;
385 /* Non ETC1 / ETC2 format */
391 brw_get_num_logical_layers(const struct intel_mipmap_tree
*mt
, unsigned level
)
393 if (mt
->surf
.dim
== ISL_SURF_DIM_3D
)
394 return minify(mt
->surf
.logical_level0_px
.depth
, level
);
396 return mt
->surf
.logical_level0_px
.array_len
;
400 get_num_phys_layers(const struct isl_surf
*surf
, unsigned level
)
402 /* In case of physical dimensions one needs to consider also the layout.
403 * See isl_calc_phys_level0_extent_sa().
405 if (surf
->dim
!= ISL_SURF_DIM_3D
)
406 return surf
->phys_level0_sa
.array_len
;
408 if (surf
->dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
)
409 return minify(surf
->phys_level0_sa
.array_len
, level
);
411 return minify(surf
->phys_level0_sa
.depth
, level
);
414 /** \brief Assert that the level and layer are valid for the miptree. */
416 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
424 assert(level
>= mt
->first_level
);
425 assert(level
<= mt
->last_level
);
426 assert(layer
< get_num_phys_layers(&mt
->surf
, level
));
429 static enum isl_aux_state
**
430 create_aux_state_map(struct intel_mipmap_tree
*mt
,
431 enum isl_aux_state initial
)
433 const uint32_t levels
= mt
->last_level
+ 1;
435 uint32_t total_slices
= 0;
436 for (uint32_t level
= 0; level
< levels
; level
++)
437 total_slices
+= brw_get_num_logical_layers(mt
, level
);
439 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
441 /* We're going to allocate a single chunk of data for both the per-level
442 * reference array and the arrays of aux_state. This makes cleanup
443 * significantly easier.
445 const size_t total_size
= per_level_array_size
+
446 total_slices
* sizeof(enum isl_aux_state
);
447 void *data
= malloc(total_size
);
451 enum isl_aux_state
**per_level_arr
= data
;
452 enum isl_aux_state
*s
= data
+ per_level_array_size
;
453 for (uint32_t level
= 0; level
< levels
; level
++) {
454 per_level_arr
[level
] = s
;
455 const unsigned level_layers
= brw_get_num_logical_layers(mt
, level
);
456 for (uint32_t a
= 0; a
< level_layers
; a
++)
459 assert((void *)s
== data
+ total_size
);
461 return per_level_arr
;
465 free_aux_state_map(enum isl_aux_state
**state
)
471 need_to_retile_as_linear(struct brw_context
*brw
, unsigned row_pitch
,
472 enum isl_tiling tiling
, unsigned samples
)
477 if (tiling
== ISL_TILING_LINEAR
)
480 /* If the width is much smaller than a tile, don't bother tiling. */
484 if (ALIGN(row_pitch
, 512) >= 32768) {
485 perf_debug("row pitch %u too large to blit, falling back to untiled",
494 need_to_retile_as_x(const struct brw_context
*brw
, uint64_t size
,
495 enum isl_tiling tiling
)
497 /* If the BO is too large to fit in the aperture, we need to use the
498 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
499 * handle Y-tiling, so we need to fall back to X.
501 if (brw
->gen
< 6 && size
>= brw
->max_gtt_map_object_size
&&
502 tiling
== ISL_TILING_Y0
)
508 static struct intel_mipmap_tree
*
509 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
510 unsigned first_level
, unsigned last_level
,
511 unsigned width0
, unsigned height0
, unsigned depth0
,
512 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
513 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
514 unsigned row_pitch
, struct brw_bo
*bo
)
516 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
520 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
528 if (target
== GL_TEXTURE_CUBE_MAP
||
529 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
530 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
532 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
534 _mesa_enum_to_string(target
),
535 _mesa_get_format_name(format
),
536 num_samples
, width0
, height0
, depth0
,
537 first_level
, last_level
, mt
);
539 struct isl_surf_init_info init_info
= {
540 .dim
= get_isl_surf_dim(target
),
541 .format
= translate_tex_format(brw
, format
, false),
544 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
545 .levels
= last_level
- first_level
+ 1,
546 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
547 .samples
= num_samples
,
548 .row_pitch
= row_pitch
,
549 .usage
= isl_usage_flags
,
550 .tiling_flags
= tiling_flags
,
553 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
556 /* In case caller doesn't specifically request Y-tiling (needed
557 * unconditionally for depth), check for corner cases needing special
560 if (tiling_flags
& ~ISL_TILING_Y0_BIT
) {
561 if (need_to_retile_as_linear(brw
, mt
->surf
.row_pitch
,
562 mt
->surf
.tiling
, mt
->surf
.samples
)) {
563 init_info
.tiling_flags
= 1u << ISL_TILING_LINEAR
;
564 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
566 } else if (need_to_retile_as_x(brw
, mt
->surf
.size
, mt
->surf
.tiling
)) {
567 init_info
.tiling_flags
= 1u << ISL_TILING_X
;
568 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
573 /* In case of linear the buffer gets padded by fixed 64 bytes and therefore
574 * the size may not be multiple of row_pitch.
575 * See isl_apply_surface_padding().
577 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
)
578 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
581 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
583 isl_tiling_to_i915_tiling(
585 mt
->surf
.row_pitch
, alloc_flags
);
592 mt
->first_level
= first_level
;
593 mt
->last_level
= last_level
;
596 mt
->aux_state
= NULL
;
597 mt
->cpp
= isl_format_get_layout(mt
->surf
.format
)->bpb
/ 8;
598 mt
->compressed
= _mesa_is_format_compressed(format
);
603 intel_miptree_release(&mt
);
608 make_separate_stencil_surface(struct brw_context
*brw
,
609 struct intel_mipmap_tree
*mt
)
611 mt
->stencil_mt
= make_surface(brw
, mt
->target
, MESA_FORMAT_S_UINT8
,
612 0, mt
->surf
.levels
- 1,
613 mt
->surf
.logical_level0_px
.width
,
614 mt
->surf
.logical_level0_px
.height
,
615 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
616 mt
->surf
.logical_level0_px
.depth
:
617 mt
->surf
.logical_level0_px
.array_len
,
618 mt
->surf
.samples
, ISL_TILING_W_BIT
,
619 ISL_SURF_USAGE_STENCIL_BIT
|
620 ISL_SURF_USAGE_TEXTURE_BIT
,
621 BO_ALLOC_FOR_RENDER
, 0, NULL
);
626 mt
->stencil_mt
->r8stencil_needs_update
= true;
631 static struct intel_mipmap_tree
*
632 miptree_create(struct brw_context
*brw
,
641 uint32_t layout_flags
)
643 if (format
== MESA_FORMAT_S_UINT8
)
644 return make_surface(brw
, target
, format
, first_level
, last_level
,
645 width0
, height0
, depth0
, num_samples
,
647 ISL_SURF_USAGE_STENCIL_BIT
|
648 ISL_SURF_USAGE_TEXTURE_BIT
,
653 const GLenum base_format
= _mesa_get_format_base_format(format
);
654 if ((base_format
== GL_DEPTH_COMPONENT
||
655 base_format
== GL_DEPTH_STENCIL
) &&
656 !(layout_flags
& MIPTREE_LAYOUT_TILING_NONE
)) {
657 /* Fix up the Z miptree format for how we're splitting out separate
658 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
660 const mesa_format depth_only_format
=
661 intel_depth_format_for_depthstencil_format(format
);
662 struct intel_mipmap_tree
*mt
= make_surface(
663 brw
, target
, brw
->gen
>= 6 ? depth_only_format
: format
,
664 first_level
, last_level
,
665 width0
, height0
, depth0
, num_samples
, ISL_TILING_Y0_BIT
,
666 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
667 BO_ALLOC_FOR_RENDER
, 0, NULL
);
669 if (needs_separate_stencil(brw
, mt
, format
) &&
670 !make_separate_stencil_surface(brw
, mt
)) {
671 intel_miptree_release(&mt
);
675 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
676 intel_miptree_choose_aux_usage(brw
, mt
);
681 mesa_format tex_format
= format
;
682 mesa_format etc_format
= MESA_FORMAT_NONE
;
683 uint32_t alloc_flags
= 0;
685 format
= intel_lower_compressed_format(brw
, format
);
687 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
689 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
690 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
692 isl_tiling_flags_t tiling_flags
=
693 (layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) ?
694 ISL_TILING_LINEAR_BIT
: ISL_TILING_ANY_MASK
;
696 /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
698 tiling_flags
&= ~ISL_TILING_Y0_BIT
;
700 struct intel_mipmap_tree
*mt
= make_surface(
702 first_level
, last_level
,
703 width0
, height0
, depth0
,
704 num_samples
, tiling_flags
,
705 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
706 ISL_SURF_USAGE_TEXTURE_BIT
,
707 alloc_flags
, 0, NULL
);
711 mt
->etc_format
= etc_format
;
713 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
714 intel_miptree_choose_aux_usage(brw
, mt
);
719 struct intel_mipmap_tree
*
720 intel_miptree_create(struct brw_context
*brw
,
729 uint32_t layout_flags
)
731 assert(num_samples
> 0);
733 struct intel_mipmap_tree
*mt
= miptree_create(
735 first_level
, last_level
,
736 width0
, height0
, depth0
, num_samples
,
743 if (!intel_miptree_alloc_aux(brw
, mt
)) {
744 intel_miptree_release(&mt
);
751 struct intel_mipmap_tree
*
752 intel_miptree_create_for_bo(struct brw_context
*brw
,
760 uint32_t layout_flags
)
762 struct intel_mipmap_tree
*mt
;
763 uint32_t tiling
, swizzle
;
764 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
765 const GLenum base_format
= _mesa_get_format_base_format(format
);
767 if ((base_format
== GL_DEPTH_COMPONENT
||
768 base_format
== GL_DEPTH_STENCIL
)) {
769 const mesa_format depth_only_format
=
770 intel_depth_format_for_depthstencil_format(format
);
771 mt
= make_surface(brw
, target
,
772 brw
->gen
>= 6 ? depth_only_format
: format
,
773 0, 0, width
, height
, depth
, 1, ISL_TILING_Y0_BIT
,
774 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
775 BO_ALLOC_FOR_RENDER
, pitch
, bo
);
779 brw_bo_reference(bo
);
781 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
782 intel_miptree_choose_aux_usage(brw
, mt
);
785 } else if (format
== MESA_FORMAT_S_UINT8
) {
786 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
787 0, 0, width
, height
, depth
, 1,
789 ISL_SURF_USAGE_STENCIL_BIT
|
790 ISL_SURF_USAGE_TEXTURE_BIT
,
791 BO_ALLOC_FOR_RENDER
, pitch
, bo
);
795 assert(bo
->size
>= mt
->surf
.size
);
797 brw_bo_reference(bo
);
801 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
803 /* Nothing will be able to use this miptree with the BO if the offset isn't
806 if (tiling
!= I915_TILING_NONE
)
807 assert(offset
% 4096 == 0);
809 /* miptrees can't handle negative pitch. If you need flipping of images,
810 * that's outside of the scope of the mt.
814 /* The BO already has a tiling format and we shouldn't confuse the lower
815 * layers by making it try to find a tiling format again.
817 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
819 mt
= make_surface(brw
, target
, format
,
820 0, 0, width
, height
, depth
, 1,
821 1lu << isl_tiling_from_i915_tiling(tiling
),
822 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
823 ISL_SURF_USAGE_TEXTURE_BIT
,
828 brw_bo_reference(bo
);
832 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
)) {
833 intel_miptree_choose_aux_usage(brw
, mt
);
835 if (!intel_miptree_alloc_aux(brw
, mt
)) {
836 intel_miptree_release(&mt
);
844 static struct intel_mipmap_tree
*
845 miptree_create_for_planar_image(struct brw_context
*brw
,
846 __DRIimage
*image
, GLenum target
)
848 const struct intel_image_format
*f
= image
->planar_format
;
849 struct intel_mipmap_tree
*planar_mt
= NULL
;
851 for (int i
= 0; i
< f
->nplanes
; i
++) {
852 const int index
= f
->planes
[i
].buffer_index
;
853 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
854 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
855 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
856 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
858 /* Disable creation of the texture's aux buffers because the driver
859 * exposes no EGL API to manage them. That is, there is no API for
860 * resolving the aux buffer's content to the main buffer nor for
861 * invalidating the aux buffer's content.
863 struct intel_mipmap_tree
*mt
=
864 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
865 image
->offsets
[index
],
867 image
->strides
[index
],
868 MIPTREE_LAYOUT_DISABLE_AUX
);
877 planar_mt
->plane
[i
- 1] = mt
;
883 struct intel_mipmap_tree
*
884 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
885 __DRIimage
*image
, GLenum target
,
886 enum isl_colorspace colorspace
,
887 bool is_winsys_image
)
889 if (image
->planar_format
&& image
->planar_format
->nplanes
> 0) {
890 assert(colorspace
== ISL_COLORSPACE_NONE
||
891 colorspace
== ISL_COLORSPACE_YUV
);
892 return miptree_create_for_planar_image(brw
, image
, target
);
895 mesa_format format
= image
->format
;
896 switch (colorspace
) {
897 case ISL_COLORSPACE_NONE
:
898 /* Keep the image format unmodified */
901 case ISL_COLORSPACE_LINEAR
:
902 format
=_mesa_get_srgb_format_linear(format
);
905 case ISL_COLORSPACE_SRGB
:
906 format
=_mesa_get_linear_format_srgb(format
);
910 unreachable("Inalid colorspace for non-planar image");
913 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
914 /* The texture storage paths in core Mesa detect if the driver does not
915 * support the user-requested format, and then searches for a
916 * fallback format. The DRIimage code bypasses core Mesa, though. So we
917 * do the fallbacks here for important formats.
919 * We must support DRM_FOURCC_XBGR8888 textures because the Android
920 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
921 * the Chrome OS compositor consumes as dma_buf EGLImages.
923 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
926 if (!brw
->ctx
.TextureFormatSupported
[format
])
929 /* If this image comes in from a window system, we have different
930 * requirements than if it comes in via an EGL import operation. Window
931 * system images can use any form of auxiliary compression we wish because
932 * they get "flushed" before being handed off to the window system and we
933 * have the opportunity to do resolves. Window system buffers also may be
934 * used for scanout so we need to flag that appropriately.
936 const uint32_t mt_layout_flags
=
937 is_winsys_image
? 0 : MIPTREE_LAYOUT_DISABLE_AUX
;
939 /* Disable creation of the texture's aux buffers because the driver exposes
940 * no EGL API to manage them. That is, there is no API for resolving the aux
941 * buffer's content to the main buffer nor for invalidating the aux buffer's
944 struct intel_mipmap_tree
*mt
=
945 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
946 image
->offset
, image
->width
, image
->height
, 1,
947 image
->pitch
, mt_layout_flags
);
952 mt
->level
[0].level_x
= image
->tile_x
;
953 mt
->level
[0].level_y
= image
->tile_y
;
955 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
956 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
957 * trouble resolving back to destination image due to alignment issues.
959 if (!brw
->has_surface_tile_offset
) {
960 uint32_t draw_x
, draw_y
;
961 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
963 if (draw_x
!= 0 || draw_y
!= 0) {
964 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
965 intel_miptree_release(&mt
);
970 /* If this is a window-system image, then we can no longer assume it's
971 * cache-coherent because it may suddenly get scanned out which destroys
975 image
->bo
->cache_coherent
= false;
981 * For a singlesample renderbuffer, this simply wraps the given BO with a
984 * For a multisample renderbuffer, this wraps the window system's
985 * (singlesample) BO with a singlesample miptree attached to the
986 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
987 * that will contain the actual rendering (which is lazily resolved to
988 * irb->singlesample_mt).
991 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
992 struct intel_renderbuffer
*irb
,
993 struct intel_mipmap_tree
*singlesample_mt
,
994 uint32_t width
, uint32_t height
,
997 struct intel_mipmap_tree
*multisample_mt
= NULL
;
998 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
999 mesa_format format
= rb
->Format
;
1000 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1002 /* Only the front and back buffers, which are color buffers, are allocated
1003 * through the image loader.
1005 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1006 _mesa_get_format_base_format(format
) == GL_RGBA
);
1008 assert(singlesample_mt
);
1010 if (num_samples
== 1) {
1011 intel_miptree_release(&irb
->mt
);
1012 irb
->mt
= singlesample_mt
;
1014 assert(!irb
->singlesample_mt
);
1016 intel_miptree_release(&irb
->singlesample_mt
);
1017 irb
->singlesample_mt
= singlesample_mt
;
1020 irb
->mt
->surf
.logical_level0_px
.width
!= width
||
1021 irb
->mt
->surf
.logical_level0_px
.height
!= height
) {
1022 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1027 if (!multisample_mt
)
1030 irb
->need_downsample
= false;
1031 intel_miptree_release(&irb
->mt
);
1032 irb
->mt
= multisample_mt
;
1038 intel_miptree_release(&irb
->mt
);
1042 struct intel_mipmap_tree
*
1043 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1047 uint32_t num_samples
)
1049 struct intel_mipmap_tree
*mt
;
1051 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1052 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1054 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1055 width
, height
, depth
, num_samples
,
1063 intel_miptree_release(&mt
);
1068 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1069 struct intel_mipmap_tree
*src
)
1074 intel_miptree_release(dst
);
1078 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1085 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1087 if (aux_buf
== NULL
)
1090 brw_bo_unreference(aux_buf
->bo
);
1096 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1101 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1102 if (--(*mt
)->refcount
<= 0) {
1105 DBG("%s deleting %p\n", __func__
, *mt
);
1107 brw_bo_unreference((*mt
)->bo
);
1108 intel_miptree_release(&(*mt
)->stencil_mt
);
1109 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1110 intel_miptree_aux_buffer_free((*mt
)->hiz_buf
);
1111 intel_miptree_aux_buffer_free((*mt
)->mcs_buf
);
1112 free_aux_state_map((*mt
)->aux_state
);
1114 intel_miptree_release(&(*mt
)->plane
[0]);
1115 intel_miptree_release(&(*mt
)->plane
[1]);
1117 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1118 free((*mt
)->level
[i
].slice
);
1128 intel_get_image_dims(struct gl_texture_image
*image
,
1129 int *width
, int *height
, int *depth
)
1131 switch (image
->TexObject
->Target
) {
1132 case GL_TEXTURE_1D_ARRAY
:
1133 /* For a 1D Array texture the OpenGL API will treat the image height as
1134 * the number of array slices. For Intel hardware, we treat the 1D array
1135 * as a 2D Array with a height of 1. So, here we want to swap image
1138 assert(image
->Depth
== 1);
1139 *width
= image
->Width
;
1141 *depth
= image
->Height
;
1143 case GL_TEXTURE_CUBE_MAP
:
1144 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1145 * though we really have 6 slices.
1147 assert(image
->Depth
== 1);
1148 *width
= image
->Width
;
1149 *height
= image
->Height
;
1153 *width
= image
->Width
;
1154 *height
= image
->Height
;
1155 *depth
= image
->Depth
;
1161 * Can the image be pulled into a unified mipmap tree? This mirrors
1162 * the completeness test in a lot of ways.
1164 * Not sure whether I want to pass gl_texture_image here.
1167 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1168 struct gl_texture_image
*image
)
1170 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1171 GLuint level
= intelImage
->base
.Base
.Level
;
1172 int width
, height
, depth
;
1174 /* glTexImage* choose the texture object based on the target passed in, and
1175 * objects can't change targets over their lifetimes, so this should be
1178 assert(image
->TexObject
->Target
== mt
->target
);
1180 mesa_format mt_format
= mt
->format
;
1181 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1182 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1183 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1184 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1185 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1186 mt_format
= mt
->etc_format
;
1188 if (image
->TexFormat
!= mt_format
)
1191 intel_get_image_dims(image
, &width
, &height
, &depth
);
1193 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1196 if (level
>= mt
->surf
.levels
)
1199 const unsigned level_depth
=
1200 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1201 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1202 mt
->surf
.logical_level0_px
.array_len
;
1204 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1205 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1206 depth
== level_depth
&&
1207 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1211 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1212 GLuint level
, GLuint slice
,
1213 GLuint
*x
, GLuint
*y
)
1215 if (level
== 0 && slice
== 0) {
1216 *x
= mt
->level
[0].level_x
;
1217 *y
= mt
->level
[0].level_y
;
1221 uint32_t x_offset_sa
, y_offset_sa
;
1223 /* Miptree itself can have an offset only if it represents a single
1224 * slice in an imported buffer object.
1225 * See intel_miptree_create_for_dri_image().
1227 assert(mt
->level
[0].level_x
== 0);
1228 assert(mt
->level
[0].level_y
== 0);
1230 /* Given level is relative to level zero while the miptree may be
1231 * represent just a subset of all levels starting from 'first_level'.
1233 assert(level
>= mt
->first_level
);
1234 level
-= mt
->first_level
;
1236 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1237 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1238 isl_surf_get_image_offset_el(&mt
->surf
, level
, slice
, z
,
1239 &x_offset_sa
, &y_offset_sa
);
1247 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1248 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1249 * and tile_h is set to 1.
1252 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1253 uint32_t *tile_w
, uint32_t *tile_h
)
1264 case ISL_TILING_LINEAR
:
1269 unreachable("not reached");
1275 * This function computes masks that may be used to select the bits of the X
1276 * and Y coordinates that indicate the offset within a tile. If the BO is
1277 * untiled, the masks are set to 0.
1280 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1281 uint32_t *mask_x
, uint32_t *mask_y
)
1283 uint32_t tile_w_bytes
, tile_h
;
1285 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1287 *mask_x
= tile_w_bytes
/ cpp
- 1;
1288 *mask_y
= tile_h
- 1;
1292 * Compute the offset (in bytes) from the start of the BO to the given x
1293 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1294 * multiples of the tile size.
1297 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1298 uint32_t x
, uint32_t y
)
1301 uint32_t pitch
= mt
->surf
.row_pitch
;
1303 switch (mt
->surf
.tiling
) {
1305 unreachable("not reached");
1306 case ISL_TILING_LINEAR
:
1307 return y
* pitch
+ x
* cpp
;
1309 assert((x
% (512 / cpp
)) == 0);
1310 assert((y
% 8) == 0);
1311 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1313 assert((x
% (128 / cpp
)) == 0);
1314 assert((y
% 32) == 0);
1315 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1320 * Rendering with tiled buffers requires that the base address of the buffer
1321 * be aligned to a page boundary. For renderbuffers, and sometimes with
1322 * textures, we may want the surface to point at a texture image level that
1323 * isn't at a page boundary.
1325 * This function returns an appropriately-aligned base offset
1326 * according to the tiling restrictions, plus any required x/y offset
1330 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1331 GLuint level
, GLuint slice
,
1336 uint32_t mask_x
, mask_y
;
1338 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1339 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1341 *tile_x
= x
& mask_x
;
1342 *tile_y
= y
& mask_y
;
1344 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1348 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1349 struct intel_mipmap_tree
*src_mt
,
1350 unsigned src_level
, unsigned src_layer
,
1351 struct intel_mipmap_tree
*dst_mt
,
1352 unsigned dst_level
, unsigned dst_layer
,
1353 unsigned width
, unsigned height
)
1356 ptrdiff_t src_stride
, dst_stride
;
1357 const unsigned cpp
= (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8);
1359 intel_miptree_map(brw
, src_mt
,
1360 src_level
, src_layer
,
1363 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1366 intel_miptree_map(brw
, dst_mt
,
1367 dst_level
, dst_layer
,
1370 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1374 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1375 _mesa_get_format_name(src_mt
->format
),
1376 src_mt
, src
, src_stride
,
1377 _mesa_get_format_name(dst_mt
->format
),
1378 dst_mt
, dst
, dst_stride
,
1381 int row_size
= cpp
* width
;
1382 if (src_stride
== row_size
&&
1383 dst_stride
== row_size
) {
1384 memcpy(dst
, src
, row_size
* height
);
1386 for (int i
= 0; i
< height
; i
++) {
1387 memcpy(dst
, src
, row_size
);
1393 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1394 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1396 /* Don't forget to copy the stencil data over, too. We could have skipped
1397 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1398 * shuffling the two data sources in/out of temporary storage instead of
1399 * the direct mapping we get this way.
1401 if (dst_mt
->stencil_mt
) {
1402 assert(src_mt
->stencil_mt
);
1403 intel_miptree_copy_slice_sw(brw
,
1404 src_mt
->stencil_mt
, src_level
, src_layer
,
1405 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1411 intel_miptree_copy_slice(struct brw_context
*brw
,
1412 struct intel_mipmap_tree
*src_mt
,
1413 unsigned src_level
, unsigned src_layer
,
1414 struct intel_mipmap_tree
*dst_mt
,
1415 unsigned dst_level
, unsigned dst_layer
)
1418 mesa_format format
= src_mt
->format
;
1419 unsigned width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1420 src_level
- src_mt
->first_level
);
1421 unsigned height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1422 src_level
- src_mt
->first_level
);
1424 assert(src_layer
< get_num_phys_layers(&src_mt
->surf
,
1425 src_level
- src_mt
->first_level
));
1427 assert(src_mt
->format
== dst_mt
->format
);
1429 if (dst_mt
->compressed
) {
1431 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1432 height
= ALIGN_NPOT(height
, j
) / j
;
1433 width
= ALIGN_NPOT(width
, i
) / i
;
1436 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1437 * below won't apply since we can't do the depth's Y tiling or the
1438 * stencil's W tiling in the blitter.
1440 if (src_mt
->stencil_mt
) {
1441 intel_miptree_copy_slice_sw(brw
,
1442 src_mt
, src_level
, src_layer
,
1443 dst_mt
, dst_level
, dst_layer
,
1448 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1449 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1451 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1454 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1455 _mesa_get_format_name(src_mt
->format
),
1456 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch
,
1457 _mesa_get_format_name(dst_mt
->format
),
1458 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch
,
1461 if (!intel_miptree_blit(brw
,
1462 src_mt
, src_level
, src_layer
, 0, 0, false,
1463 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1464 width
, height
, GL_COPY
)) {
1465 perf_debug("miptree validate blit for %s failed\n",
1466 _mesa_get_format_name(format
));
1468 intel_miptree_copy_slice_sw(brw
,
1469 src_mt
, src_level
, src_layer
,
1470 dst_mt
, dst_level
, dst_layer
,
1476 * Copies the image's current data to the given miptree, and associates that
1477 * miptree with the image.
1479 * If \c invalidate is true, then the actual image data does not need to be
1480 * copied, but the image still needs to be associated to the new miptree (this
1481 * is set to true if we're about to clear the image).
1484 intel_miptree_copy_teximage(struct brw_context
*brw
,
1485 struct intel_texture_image
*intelImage
,
1486 struct intel_mipmap_tree
*dst_mt
,
1489 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1490 struct intel_texture_object
*intel_obj
=
1491 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1492 int level
= intelImage
->base
.Base
.Level
;
1493 const unsigned face
= intelImage
->base
.Base
.Face
;
1494 unsigned start_layer
, end_layer
;
1496 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1498 assert(intelImage
->base
.Base
.Height
);
1500 end_layer
= intelImage
->base
.Base
.Height
- 1;
1501 } else if (face
> 0) {
1505 assert(intelImage
->base
.Base
.Depth
);
1507 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1511 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1512 intel_miptree_copy_slice(brw
,
1518 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1519 intel_obj
->needs_validate
= true;
1523 intel_miptree_init_mcs(struct brw_context
*brw
,
1524 struct intel_mipmap_tree
*mt
,
1527 assert(mt
->mcs_buf
!= NULL
);
1529 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1531 * When MCS buffer is enabled and bound to MSRT, it is required that it
1532 * is cleared prior to any rendering.
1534 * Since we don't use the MCS buffer for any purpose other than rendering,
1535 * it makes sense to just clear it immediately upon allocation.
1537 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1539 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1540 if (unlikely(map
== NULL
)) {
1541 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1542 brw_bo_unreference(mt
->mcs_buf
->bo
);
1547 memset(data
, init_value
, mt
->mcs_buf
->size
);
1548 brw_bo_unmap(mt
->mcs_buf
->bo
);
1551 static struct intel_miptree_aux_buffer
*
1552 intel_alloc_aux_buffer(struct brw_context
*brw
,
1554 const struct isl_surf
*aux_surf
,
1555 uint32_t alloc_flags
,
1556 struct intel_mipmap_tree
*mt
)
1558 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1562 buf
->size
= aux_surf
->size
;
1563 buf
->pitch
= aux_surf
->row_pitch
;
1564 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1566 /* ISL has stricter set of alignment rules then the drm allocator.
1567 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1568 * trying to recalculate based on different format block sizes.
1570 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1571 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1577 buf
->surf
= *aux_surf
;
1583 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1584 struct intel_mipmap_tree
*mt
,
1587 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1588 assert(mt
->mcs_buf
== NULL
);
1589 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1591 /* Multisampled miptrees are only supported for single level. */
1592 assert(mt
->first_level
== 0);
1593 enum isl_aux_state
**aux_state
=
1594 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1598 struct isl_surf temp_mcs_surf
;
1600 MAYBE_UNUSED
bool ok
=
1601 isl_surf_get_mcs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_mcs_surf
);
1604 /* Buffer needs to be initialised requiring the buffer to be immediately
1605 * mapped to cpu space for writing. Therefore do not use the gpu access
1606 * flag which can cause an unnecessary delay if the backing pages happened
1607 * to be just used by the GPU.
1609 const uint32_t alloc_flags
= 0;
1610 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1611 &temp_mcs_surf
, alloc_flags
, mt
);
1617 mt
->aux_state
= aux_state
;
1619 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1625 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1626 struct intel_mipmap_tree
*mt
)
1628 assert(mt
->mcs_buf
== NULL
);
1629 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1630 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1632 struct isl_surf temp_ccs_surf
;
1634 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
, 0))
1637 assert(temp_ccs_surf
.size
&&
1638 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1640 enum isl_aux_state
**aux_state
=
1641 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1645 /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
1646 * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
1648 * "If Software wants to enable Color Compression without Fast clear,
1649 * Software needs to initialize MCS with zeros."
1651 * A CCS value of 0 indicates that the corresponding block is in the
1652 * pass-through state which is what we want.
1654 * For CCS_D, on the other hand, we don't care as we're about to perform a
1655 * fast-clear operation. In that case, being hot in caches more useful.
1657 const uint32_t alloc_flags
= mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
?
1658 BO_ALLOC_ZEROED
: BO_ALLOC_FOR_RENDER
;
1659 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
1660 &temp_ccs_surf
, alloc_flags
, mt
);
1666 mt
->aux_state
= aux_state
;
1672 * Helper for intel_miptree_alloc_hiz() that sets
1673 * \c mt->level[level].has_hiz. Return true if and only if
1674 * \c has_hiz was set.
1677 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1678 struct intel_mipmap_tree
*mt
,
1681 assert(mt
->hiz_buf
);
1682 assert(mt
->surf
.size
> 0);
1684 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1685 uint32_t width
= minify(mt
->surf
.phys_level0_sa
.width
, level
);
1686 uint32_t height
= minify(mt
->surf
.phys_level0_sa
.height
, level
);
1688 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1689 * and the height is 4 aligned. This allows our HiZ support
1690 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1691 * we can grow the width & height to allow the HiZ op to
1692 * force the proper size alignments.
1694 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1695 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1700 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1701 mt
->level
[level
].has_hiz
= true;
1706 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1707 struct intel_mipmap_tree
*mt
)
1709 assert(mt
->hiz_buf
== NULL
);
1710 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
1712 enum isl_aux_state
**aux_state
=
1713 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1717 struct isl_surf temp_hiz_surf
;
1719 MAYBE_UNUSED
bool ok
=
1720 isl_surf_get_hiz_surf(&brw
->isl_dev
, &mt
->surf
, &temp_hiz_surf
);
1723 const uint32_t alloc_flags
= BO_ALLOC_FOR_RENDER
;
1724 mt
->hiz_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
1725 &temp_hiz_surf
, alloc_flags
, mt
);
1732 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1733 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1735 mt
->aux_state
= aux_state
;
1742 * Allocate the initial aux surface for a miptree based on mt->aux_usage
1744 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
1745 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
1746 * compress clear color so we wait until an actual fast-clear to allocate it.
1749 intel_miptree_alloc_aux(struct brw_context
*brw
,
1750 struct intel_mipmap_tree
*mt
)
1752 switch (mt
->aux_usage
) {
1753 case ISL_AUX_USAGE_NONE
:
1756 case ISL_AUX_USAGE_HIZ
:
1757 assert(!_mesa_is_format_color_format(mt
->format
));
1758 if (!intel_miptree_alloc_hiz(brw
, mt
))
1762 case ISL_AUX_USAGE_MCS
:
1763 assert(_mesa_is_format_color_format(mt
->format
));
1764 assert(mt
->surf
.samples
> 1);
1765 if (!intel_miptree_alloc_mcs(brw
, mt
, mt
->surf
.samples
))
1769 case ISL_AUX_USAGE_CCS_D
:
1770 /* Since CCS_D can only compress clear color so we wait until an actual
1771 * fast-clear to allocate it.
1775 case ISL_AUX_USAGE_CCS_E
:
1776 assert(_mesa_is_format_color_format(mt
->format
));
1777 assert(mt
->surf
.samples
== 1);
1778 if (!intel_miptree_alloc_ccs(brw
, mt
))
1783 unreachable("Invalid aux usage");
1788 * Can the miptree sample using the hiz buffer?
1791 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1792 struct intel_mipmap_tree
*mt
)
1794 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
1795 * so keep things conservative for now and never enable it unless we're SKL+.
1805 /* It seems the hardware won't fallback to the depth buffer if some of the
1806 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1807 * of the texture to be HiZ enabled.
1809 for (unsigned level
= 0; level
< mt
->surf
.levels
; ++level
) {
1810 if (!intel_miptree_level_has_hiz(mt
, level
))
1814 /* If compressed multisampling is enabled, then we use it for the auxiliary
1817 * From the BDW PRM (Volume 2d: Command Reference: Structures
1818 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1820 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1821 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1823 * There is no such blurb for 1D textures, but there is sufficient evidence
1824 * that this is broken on SKL+.
1826 return (mt
->surf
.samples
== 1 &&
1827 mt
->target
!= GL_TEXTURE_3D
&&
1828 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1832 * Does the miptree slice have hiz enabled?
1835 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
1837 intel_miptree_check_level_layer(mt
, level
, 0);
1838 return mt
->level
[level
].has_hiz
;
1841 static inline uint32_t
1842 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
1843 uint32_t start_level
, uint32_t num_levels
)
1845 assert(start_level
>= mt
->first_level
);
1846 assert(start_level
<= mt
->last_level
);
1848 if (num_levels
== INTEL_REMAINING_LAYERS
)
1849 num_levels
= mt
->last_level
- start_level
+ 1;
1850 /* Check for overflow */
1851 assert(start_level
+ num_levels
>= start_level
);
1852 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
1857 static inline uint32_t
1858 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
1859 uint32_t start_layer
, uint32_t num_layers
)
1861 assert(level
<= mt
->last_level
);
1863 const uint32_t total_num_layers
= brw_get_num_logical_layers(mt
, level
);
1864 assert(start_layer
< total_num_layers
);
1865 if (num_layers
== INTEL_REMAINING_LAYERS
)
1866 num_layers
= total_num_layers
- start_layer
;
1867 /* Check for overflow */
1868 assert(start_layer
+ num_layers
>= start_layer
);
1869 assert(start_layer
+ num_layers
<= total_num_layers
);
1875 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
1876 unsigned start_level
, unsigned num_levels
,
1877 unsigned start_layer
, unsigned num_layers
)
1879 assert(_mesa_is_format_color_format(mt
->format
));
1884 /* Clamp the level range to fit the miptree */
1885 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
1887 for (uint32_t l
= 0; l
< num_levels
; l
++) {
1888 const uint32_t level
= start_level
+ l
;
1889 const uint32_t level_layers
=
1890 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
1891 for (unsigned a
= 0; a
< level_layers
; a
++) {
1892 enum isl_aux_state aux_state
=
1893 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
1894 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
1895 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
1904 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
1905 const struct intel_mipmap_tree
*mt
,
1906 unsigned level
, unsigned layer
)
1912 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
1913 assert(brw
->gen
>= 8 ||
1914 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
1916 /* Compression of arrayed msaa surfaces is supported. */
1917 if (mt
->surf
.samples
> 1)
1920 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
1921 assert(brw
->gen
>= 8 ||
1923 mt
->surf
.logical_level0_px
.depth
== 1 &&
1924 mt
->surf
.logical_level0_px
.array_len
== 1));
1930 static enum blorp_fast_clear_op
1931 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
1932 enum isl_aux_usage aux_usage
,
1933 bool fast_clear_supported
)
1935 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
1937 const bool ccs_supported
= aux_usage
== ISL_AUX_USAGE_CCS_D
;
1939 assert(ccs_supported
== fast_clear_supported
);
1941 switch (aux_state
) {
1942 case ISL_AUX_STATE_CLEAR
:
1943 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1945 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
1947 return BLORP_FAST_CLEAR_OP_NONE
;
1949 case ISL_AUX_STATE_PASS_THROUGH
:
1950 return BLORP_FAST_CLEAR_OP_NONE
;
1952 case ISL_AUX_STATE_RESOLVED
:
1953 case ISL_AUX_STATE_AUX_INVALID
:
1954 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1955 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1959 unreachable("Invalid aux state for CCS_D");
1962 static enum blorp_fast_clear_op
1963 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
1964 enum isl_aux_usage aux_usage
,
1965 bool fast_clear_supported
)
1967 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
1968 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
1969 aux_usage
== ISL_AUX_USAGE_CCS_D
||
1970 aux_usage
== ISL_AUX_USAGE_CCS_E
);
1972 if (aux_usage
== ISL_AUX_USAGE_CCS_D
)
1973 assert(fast_clear_supported
);
1975 switch (aux_state
) {
1976 case ISL_AUX_STATE_CLEAR
:
1977 case ISL_AUX_STATE_PARTIAL_CLEAR
:
1978 if (fast_clear_supported
)
1979 return BLORP_FAST_CLEAR_OP_NONE
;
1980 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
1981 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
1983 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
1985 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
1986 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1987 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
1988 else if (!fast_clear_supported
)
1989 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
1991 return BLORP_FAST_CLEAR_OP_NONE
;
1993 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
1994 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1995 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
1997 return BLORP_FAST_CLEAR_OP_NONE
;
1999 case ISL_AUX_STATE_PASS_THROUGH
:
2000 return BLORP_FAST_CLEAR_OP_NONE
;
2002 case ISL_AUX_STATE_RESOLVED
:
2003 case ISL_AUX_STATE_AUX_INVALID
:
2007 unreachable("Invalid aux state for CCS_E");
2011 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2012 struct intel_mipmap_tree
*mt
,
2013 uint32_t level
, uint32_t layer
,
2014 enum isl_aux_usage aux_usage
,
2015 bool fast_clear_supported
)
2017 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2019 enum blorp_fast_clear_op resolve_op
;
2020 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2021 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
2022 fast_clear_supported
);
2024 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2025 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
2026 fast_clear_supported
);
2029 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2030 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2031 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2033 switch (resolve_op
) {
2034 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2035 /* The CCS full resolve operation destroys the CCS and sets it to the
2036 * pass-through state. (You can also think of this as being both a
2037 * resolve and an ambiguate in one operation.)
2039 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2040 ISL_AUX_STATE_PASS_THROUGH
);
2043 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2044 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2045 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2049 unreachable("Invalid resolve op");
2055 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2056 struct intel_mipmap_tree
*mt
,
2057 uint32_t level
, uint32_t layer
,
2058 enum isl_aux_usage aux_usage
)
2060 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2061 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2062 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2064 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2066 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2067 switch (aux_state
) {
2068 case ISL_AUX_STATE_CLEAR
:
2069 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2070 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
2071 aux_usage
== ISL_AUX_USAGE_CCS_D
);
2073 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2074 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2075 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2076 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
2077 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2078 ISL_AUX_STATE_PARTIAL_CLEAR
);
2082 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2083 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2084 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
2085 break; /* Nothing to do */
2087 case ISL_AUX_STATE_PASS_THROUGH
:
2088 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2089 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2090 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2096 case ISL_AUX_STATE_RESOLVED
:
2097 case ISL_AUX_STATE_AUX_INVALID
:
2098 unreachable("Invalid aux state for CCS_E");
2101 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2102 /* CCS_D is a bit simpler */
2103 switch (aux_state
) {
2104 case ISL_AUX_STATE_CLEAR
:
2105 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2106 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2107 ISL_AUX_STATE_PARTIAL_CLEAR
);
2110 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2111 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2112 break; /* Nothing to do */
2114 case ISL_AUX_STATE_PASS_THROUGH
:
2118 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2119 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2120 case ISL_AUX_STATE_RESOLVED
:
2121 case ISL_AUX_STATE_AUX_INVALID
:
2122 unreachable("Invalid aux state for CCS_D");
2128 intel_miptree_prepare_mcs_access(struct brw_context
*brw
,
2129 struct intel_mipmap_tree
*mt
,
2131 enum isl_aux_usage aux_usage
,
2132 bool fast_clear_supported
)
2134 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2136 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2137 case ISL_AUX_STATE_CLEAR
:
2138 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2139 if (!fast_clear_supported
) {
2140 brw_blorp_mcs_partial_resolve(brw
, mt
, layer
, 1);
2141 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2142 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2146 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2147 break; /* Nothing to do */
2149 case ISL_AUX_STATE_RESOLVED
:
2150 case ISL_AUX_STATE_PASS_THROUGH
:
2151 case ISL_AUX_STATE_AUX_INVALID
:
2152 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2153 unreachable("Invalid aux state for MCS");
2158 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2159 struct intel_mipmap_tree
*mt
,
2161 enum isl_aux_usage aux_usage
)
2163 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2165 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2166 case ISL_AUX_STATE_CLEAR
:
2167 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2168 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2171 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2172 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2173 break; /* Nothing to do */
2175 case ISL_AUX_STATE_RESOLVED
:
2176 case ISL_AUX_STATE_PASS_THROUGH
:
2177 case ISL_AUX_STATE_AUX_INVALID
:
2178 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2179 unreachable("Invalid aux state for MCS");
2184 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2185 struct intel_mipmap_tree
*mt
,
2186 uint32_t level
, uint32_t layer
,
2187 enum isl_aux_usage aux_usage
,
2188 bool fast_clear_supported
)
2190 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2192 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2193 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2194 case ISL_AUX_STATE_CLEAR
:
2195 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2196 if (aux_usage
!= ISL_AUX_USAGE_HIZ
|| !fast_clear_supported
)
2197 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2200 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2201 if (aux_usage
!= ISL_AUX_USAGE_HIZ
)
2202 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2205 case ISL_AUX_STATE_PASS_THROUGH
:
2206 case ISL_AUX_STATE_RESOLVED
:
2209 case ISL_AUX_STATE_AUX_INVALID
:
2210 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
2211 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2214 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2215 unreachable("Invalid HiZ state");
2218 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2219 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2222 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2223 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2224 ISL_AUX_STATE_RESOLVED
);
2227 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2228 /* The HiZ resolve operation is actually an ambiguate */
2229 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2230 ISL_AUX_STATE_PASS_THROUGH
);
2234 unreachable("Invalid HiZ op");
2240 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2241 struct intel_mipmap_tree
*mt
,
2242 uint32_t level
, uint32_t layer
,
2243 enum isl_aux_usage aux_usage
)
2245 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2247 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2248 case ISL_AUX_STATE_CLEAR
:
2249 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2250 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2251 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2254 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2255 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2256 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2257 break; /* Nothing to do */
2259 case ISL_AUX_STATE_RESOLVED
:
2260 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2261 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2262 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2264 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2265 ISL_AUX_STATE_AUX_INVALID
);
2269 case ISL_AUX_STATE_PASS_THROUGH
:
2270 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2271 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2272 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2276 case ISL_AUX_STATE_AUX_INVALID
:
2277 assert(aux_usage
!= ISL_AUX_USAGE_HIZ
);
2280 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2281 unreachable("Invalid HiZ state");
2286 intel_miptree_prepare_access(struct brw_context
*brw
,
2287 struct intel_mipmap_tree
*mt
,
2288 uint32_t start_level
, uint32_t num_levels
,
2289 uint32_t start_layer
, uint32_t num_layers
,
2290 enum isl_aux_usage aux_usage
,
2291 bool fast_clear_supported
)
2293 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2295 switch (mt
->aux_usage
) {
2296 case ISL_AUX_USAGE_NONE
:
2300 case ISL_AUX_USAGE_MCS
:
2301 assert(mt
->mcs_buf
);
2302 assert(start_level
== 0 && num_levels
== 1);
2303 const uint32_t level_layers
=
2304 miptree_layer_range_length(mt
, 0, start_layer
, num_layers
);
2305 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2306 intel_miptree_prepare_mcs_access(brw
, mt
, start_layer
+ a
,
2307 aux_usage
, fast_clear_supported
);
2311 case ISL_AUX_USAGE_CCS_D
:
2312 case ISL_AUX_USAGE_CCS_E
:
2316 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2317 const uint32_t level
= start_level
+ l
;
2318 const uint32_t level_layers
=
2319 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2320 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2321 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2323 aux_usage
, fast_clear_supported
);
2328 case ISL_AUX_USAGE_HIZ
:
2329 assert(mt
->hiz_buf
);
2330 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2331 const uint32_t level
= start_level
+ l
;
2332 if (!intel_miptree_level_has_hiz(mt
, level
))
2335 const uint32_t level_layers
=
2336 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2337 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2338 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2339 aux_usage
, fast_clear_supported
);
2345 unreachable("Invalid aux usage");
2350 intel_miptree_finish_write(struct brw_context
*brw
,
2351 struct intel_mipmap_tree
*mt
, uint32_t level
,
2352 uint32_t start_layer
, uint32_t num_layers
,
2353 enum isl_aux_usage aux_usage
)
2355 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2357 switch (mt
->aux_usage
) {
2358 case ISL_AUX_USAGE_NONE
:
2362 case ISL_AUX_USAGE_MCS
:
2363 assert(mt
->mcs_buf
);
2364 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2365 intel_miptree_finish_mcs_write(brw
, mt
, start_layer
+ a
,
2370 case ISL_AUX_USAGE_CCS_D
:
2371 case ISL_AUX_USAGE_CCS_E
:
2375 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2376 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2381 case ISL_AUX_USAGE_HIZ
:
2382 if (!intel_miptree_level_has_hiz(mt
, level
))
2385 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2386 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2392 unreachable("Invavlid aux usage");
2397 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2398 uint32_t level
, uint32_t layer
)
2400 intel_miptree_check_level_layer(mt
, level
, layer
);
2402 if (_mesa_is_format_color_format(mt
->format
)) {
2403 assert(mt
->mcs_buf
!= NULL
);
2404 assert(mt
->surf
.samples
== 1 ||
2405 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2406 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2407 unreachable("Cannot get aux state for stencil");
2409 assert(intel_miptree_level_has_hiz(mt
, level
));
2412 return mt
->aux_state
[level
][layer
];
2416 intel_miptree_set_aux_state(struct brw_context
*brw
,
2417 struct intel_mipmap_tree
*mt
, uint32_t level
,
2418 uint32_t start_layer
, uint32_t num_layers
,
2419 enum isl_aux_state aux_state
)
2421 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2423 if (_mesa_is_format_color_format(mt
->format
)) {
2424 assert(mt
->mcs_buf
!= NULL
);
2425 assert(mt
->surf
.samples
== 1 ||
2426 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2427 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2428 unreachable("Cannot get aux state for stencil");
2430 assert(intel_miptree_level_has_hiz(mt
, level
));
2433 for (unsigned a
= 0; a
< num_layers
; a
++)
2434 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2437 /* On Gen9 color buffers may be compressed by the hardware (lossless
2438 * compression). There are, however, format restrictions and care needs to be
2439 * taken that the sampler engine is capable for re-interpreting a buffer with
2440 * format different the buffer was originally written with.
2442 * For example, SRGB formats are not compressible and the sampler engine isn't
2443 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2444 * color buffer needs to be resolved so that the sampling surface can be
2445 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2449 can_texture_with_ccs(struct brw_context
*brw
,
2450 struct intel_mipmap_tree
*mt
,
2451 enum isl_format view_format
)
2453 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2456 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2457 mt
->surf
.format
, view_format
)) {
2458 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2459 isl_format_get_layout(view_format
)->name
,
2460 _mesa_get_format_name(mt
->format
));
2468 intel_miptree_texture_aux_usage(struct brw_context
*brw
,
2469 struct intel_mipmap_tree
*mt
,
2470 enum isl_format view_format
)
2472 switch (mt
->aux_usage
) {
2473 case ISL_AUX_USAGE_HIZ
:
2474 if (intel_miptree_sample_with_hiz(brw
, mt
))
2475 return ISL_AUX_USAGE_HIZ
;
2478 case ISL_AUX_USAGE_MCS
:
2479 return ISL_AUX_USAGE_MCS
;
2481 case ISL_AUX_USAGE_CCS_D
:
2482 case ISL_AUX_USAGE_CCS_E
:
2483 if (mt
->mcs_buf
&& can_texture_with_ccs(brw
, mt
, view_format
))
2484 return ISL_AUX_USAGE_CCS_E
;
2491 return ISL_AUX_USAGE_NONE
;
2495 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
2497 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
2498 * values so sRGB curve application was a no-op for all fast-clearable
2501 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
2502 * values, the hardware interprets the floats, not as what would be
2503 * returned from the sampler (or written by the shader), but as being
2504 * between format conversion and sRGB curve application. This means that
2505 * we can switch between sRGB and UNORM without having to whack the clear
2508 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
2512 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2513 struct intel_mipmap_tree
*mt
,
2514 enum isl_format view_format
,
2515 uint32_t start_level
, uint32_t num_levels
,
2516 uint32_t start_layer
, uint32_t num_layers
,
2517 bool *aux_supported_out
)
2519 enum isl_aux_usage aux_usage
=
2520 intel_miptree_texture_aux_usage(brw
, mt
, view_format
);
2521 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2523 /* Clear color is specified as ints or floats and the conversion is done by
2524 * the sampler. If we have a texture view, we would have to perform the
2525 * clear color conversion manually. Just disable clear color.
2527 if (!isl_formats_are_fast_clear_compatible(mt
->surf
.format
, view_format
))
2528 clear_supported
= false;
2530 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2531 start_layer
, num_layers
,
2532 aux_usage
, clear_supported
);
2533 if (aux_supported_out
)
2534 *aux_supported_out
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2538 intel_miptree_prepare_texture(struct brw_context
*brw
,
2539 struct intel_mipmap_tree
*mt
,
2540 enum isl_format view_format
,
2541 bool *aux_supported_out
)
2543 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2544 0, INTEL_REMAINING_LEVELS
,
2545 0, INTEL_REMAINING_LAYERS
,
2550 intel_miptree_prepare_image(struct brw_context
*brw
,
2551 struct intel_mipmap_tree
*mt
)
2553 /* The data port doesn't understand any compression */
2554 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2555 0, INTEL_REMAINING_LAYERS
,
2556 ISL_AUX_USAGE_NONE
, false);
2560 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2561 struct intel_mipmap_tree
*mt
, uint32_t level
,
2562 uint32_t start_layer
, uint32_t num_layers
)
2564 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->surf
.format
, level
, 1,
2565 start_layer
, num_layers
, NULL
);
2569 intel_miptree_render_aux_usage(struct brw_context
*brw
,
2570 struct intel_mipmap_tree
*mt
,
2571 bool srgb_enabled
, bool blend_enabled
)
2573 switch (mt
->aux_usage
) {
2574 case ISL_AUX_USAGE_MCS
:
2575 assert(mt
->mcs_buf
);
2576 return ISL_AUX_USAGE_MCS
;
2578 case ISL_AUX_USAGE_CCS_D
:
2579 return mt
->mcs_buf
? ISL_AUX_USAGE_CCS_D
: ISL_AUX_USAGE_NONE
;
2581 case ISL_AUX_USAGE_CCS_E
: {
2582 mesa_format mesa_format
=
2583 srgb_enabled
? mt
->format
:_mesa_get_srgb_format_linear(mt
->format
);
2584 enum isl_format isl_format
= brw_isl_format_for_mesa_format(mesa_format
);
2586 /* If the format supports CCS_E, then we can just use it */
2587 if (isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
))
2588 return ISL_AUX_USAGE_CCS_E
;
2590 /* Otherwise, we have to fall back to CCS_D */
2592 /* gen9 hardware technically supports non-0/1 clear colors with sRGB
2593 * formats. However, there are issues with blending where it doesn't
2594 * properly apply the sRGB curve to the clear color when blending.
2596 if (blend_enabled
&& isl_format_is_srgb(isl_format
) &&
2597 !isl_color_value_is_zero_one(mt
->fast_clear_color
, isl_format
))
2598 return ISL_AUX_USAGE_NONE
;
2600 return ISL_AUX_USAGE_CCS_D
;
2604 return ISL_AUX_USAGE_NONE
;
2609 intel_miptree_prepare_render(struct brw_context
*brw
,
2610 struct intel_mipmap_tree
*mt
, uint32_t level
,
2611 uint32_t start_layer
, uint32_t layer_count
,
2612 bool srgb_enabled
, bool blend_enabled
)
2614 enum isl_aux_usage aux_usage
=
2615 intel_miptree_render_aux_usage(brw
, mt
, srgb_enabled
, blend_enabled
);
2616 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2617 aux_usage
, aux_usage
!= ISL_AUX_USAGE_NONE
);
2621 intel_miptree_finish_render(struct brw_context
*brw
,
2622 struct intel_mipmap_tree
*mt
, uint32_t level
,
2623 uint32_t start_layer
, uint32_t layer_count
,
2624 bool srgb_enabled
, bool blend_enabled
)
2626 assert(_mesa_is_format_color_format(mt
->format
));
2628 enum isl_aux_usage aux_usage
=
2629 intel_miptree_render_aux_usage(brw
, mt
, srgb_enabled
, blend_enabled
);
2630 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2635 intel_miptree_prepare_depth(struct brw_context
*brw
,
2636 struct intel_mipmap_tree
*mt
, uint32_t level
,
2637 uint32_t start_layer
, uint32_t layer_count
)
2639 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2640 mt
->aux_usage
, mt
->hiz_buf
!= NULL
);
2644 intel_miptree_finish_depth(struct brw_context
*brw
,
2645 struct intel_mipmap_tree
*mt
, uint32_t level
,
2646 uint32_t start_layer
, uint32_t layer_count
,
2649 if (depth_written
) {
2650 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2651 mt
->hiz_buf
!= NULL
);
2656 * Make it possible to share the BO backing the given miptree with another
2657 * process or another miptree.
2659 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2660 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2661 * ensure that no MCS buffer gets allocated in the future.
2663 * HiZ is similarly unsafe with shared buffers.
2666 intel_miptree_make_shareable(struct brw_context
*brw
,
2667 struct intel_mipmap_tree
*mt
)
2669 /* MCS buffers are also used for multisample buffers, but we can't resolve
2670 * away a multisample MCS buffer because it's an integral part of how the
2671 * pixel data is stored. Fortunately this code path should never be
2672 * reached for multisample buffers.
2674 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2675 mt
->surf
.samples
== 1);
2677 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2678 0, INTEL_REMAINING_LAYERS
,
2679 ISL_AUX_USAGE_NONE
, false);
2682 brw_bo_unreference(mt
->mcs_buf
->bo
);
2686 /* Any pending MCS/CCS operations are no longer needed. Trying to
2687 * execute any will likely crash due to the missing aux buffer. So let's
2688 * delete all pending ops.
2690 free(mt
->aux_state
);
2691 mt
->aux_state
= NULL
;
2695 intel_miptree_aux_buffer_free(mt
->hiz_buf
);
2698 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2699 mt
->level
[l
].has_hiz
= false;
2702 /* Any pending HiZ operations are no longer needed. Trying to execute
2703 * any will likely crash due to the missing aux buffer. So let's delete
2706 free(mt
->aux_state
);
2707 mt
->aux_state
= NULL
;
2710 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2715 * \brief Get pointer offset into stencil buffer.
2717 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2718 * must decode the tile's layout in software.
2721 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2723 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2725 * Even though the returned offset is always positive, the return type is
2727 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2728 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2731 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2733 uint32_t tile_size
= 4096;
2734 uint32_t tile_width
= 64;
2735 uint32_t tile_height
= 64;
2736 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2738 uint32_t tile_x
= x
/ tile_width
;
2739 uint32_t tile_y
= y
/ tile_height
;
2741 /* The byte's address relative to the tile's base addres. */
2742 uint32_t byte_x
= x
% tile_width
;
2743 uint32_t byte_y
= y
% tile_height
;
2745 uintptr_t u
= tile_y
* row_size
2746 + tile_x
* tile_size
2747 + 512 * (byte_x
/ 8)
2749 + 32 * ((byte_y
/ 4) % 2)
2750 + 16 * ((byte_x
/ 4) % 2)
2751 + 8 * ((byte_y
/ 2) % 2)
2752 + 4 * ((byte_x
/ 2) % 2)
2757 /* adjust for bit6 swizzling */
2758 if (((byte_x
/ 8) % 2) == 1) {
2759 if (((byte_y
/ 8) % 2) == 0) {
2771 intel_miptree_updownsample(struct brw_context
*brw
,
2772 struct intel_mipmap_tree
*src
,
2773 struct intel_mipmap_tree
*dst
)
2775 unsigned src_w
= src
->surf
.logical_level0_px
.width
;
2776 unsigned src_h
= src
->surf
.logical_level0_px
.height
;
2777 unsigned dst_w
= dst
->surf
.logical_level0_px
.width
;
2778 unsigned dst_h
= dst
->surf
.logical_level0_px
.height
;
2780 brw_blorp_blit_miptrees(brw
,
2781 src
, 0 /* level */, 0 /* layer */,
2782 src
->format
, SWIZZLE_XYZW
,
2783 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2786 GL_NEAREST
, false, false /*mirror x, y*/,
2789 if (src
->stencil_mt
) {
2790 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2791 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2792 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2793 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2795 brw_blorp_blit_miptrees(brw
,
2796 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2797 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2798 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2799 dst
->stencil_mt
->format
,
2802 GL_NEAREST
, false, false /*mirror x, y*/,
2803 false, false /* decode/encode srgb */);
2808 intel_update_r8stencil(struct brw_context
*brw
,
2809 struct intel_mipmap_tree
*mt
)
2811 assert(brw
->gen
>= 7);
2812 struct intel_mipmap_tree
*src
=
2813 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2814 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
2817 assert(src
->surf
.size
> 0);
2819 if (!mt
->r8stencil_mt
) {
2820 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2821 mt
->r8stencil_mt
= make_surface(
2824 MESA_FORMAT_R_UINT8
,
2825 src
->first_level
, src
->last_level
,
2826 src
->surf
.logical_level0_px
.width
,
2827 src
->surf
.logical_level0_px
.height
,
2828 src
->surf
.dim
== ISL_SURF_DIM_3D
?
2829 src
->surf
.logical_level0_px
.depth
:
2830 src
->surf
.logical_level0_px
.array_len
,
2833 ISL_SURF_USAGE_TEXTURE_BIT
,
2834 BO_ALLOC_FOR_RENDER
, 0, NULL
);
2835 assert(mt
->r8stencil_mt
);
2838 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2840 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2841 const unsigned depth
= src
->surf
.dim
== ISL_SURF_DIM_3D
?
2842 minify(src
->surf
.phys_level0_sa
.depth
, level
) :
2843 src
->surf
.phys_level0_sa
.array_len
;
2845 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2846 brw_blorp_copy_miptrees(brw
,
2850 minify(src
->surf
.logical_level0_px
.width
,
2852 minify(src
->surf
.logical_level0_px
.height
,
2857 brw_render_cache_set_check_flush(brw
, dst
->bo
);
2858 src
->r8stencil_needs_update
= false;
2862 intel_miptree_map_raw(struct brw_context
*brw
,
2863 struct intel_mipmap_tree
*mt
,
2866 struct brw_bo
*bo
= mt
->bo
;
2868 if (brw_batch_references(&brw
->batch
, bo
))
2869 intel_batchbuffer_flush(brw
);
2871 return brw_bo_map(brw
, bo
, mode
);
2875 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2877 brw_bo_unmap(mt
->bo
);
2881 intel_miptree_map_gtt(struct brw_context
*brw
,
2882 struct intel_mipmap_tree
*mt
,
2883 struct intel_miptree_map
*map
,
2884 unsigned int level
, unsigned int slice
)
2886 unsigned int bw
, bh
;
2888 unsigned int image_x
, image_y
;
2889 intptr_t x
= map
->x
;
2890 intptr_t y
= map
->y
;
2892 /* For compressed formats, the stride is the number of bytes per
2893 * row of blocks. intel_miptree_get_image_offset() already does
2896 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2897 assert(y
% bh
== 0);
2898 assert(x
% bw
== 0);
2902 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
2909 /* Note that in the case of cube maps, the caller must have passed the
2910 * slice number referencing the face.
2912 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2916 map
->stride
= mt
->surf
.row_pitch
;
2917 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2920 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2921 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2922 map
->x
, map
->y
, map
->w
, map
->h
,
2923 mt
, _mesa_get_format_name(mt
->format
),
2924 x
, y
, map
->ptr
, map
->stride
);
2928 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
2930 intel_miptree_unmap_raw(mt
);
2934 intel_miptree_map_blit(struct brw_context
*brw
,
2935 struct intel_mipmap_tree
*mt
,
2936 struct intel_miptree_map
*map
,
2937 unsigned int level
, unsigned int slice
)
2939 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2940 /* first_level */ 0,
2944 MIPTREE_LAYOUT_TILING_NONE
);
2946 if (!map
->linear_mt
) {
2947 fprintf(stderr
, "Failed to allocate blit temporary\n");
2950 map
->stride
= map
->linear_mt
->surf
.row_pitch
;
2952 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2953 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2954 * invalidate is set, since we'll be writing the whole rectangle from our
2955 * temporary buffer back out.
2957 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2958 if (!intel_miptree_copy(brw
,
2959 mt
, level
, slice
, map
->x
, map
->y
,
2960 map
->linear_mt
, 0, 0, 0, 0,
2962 fprintf(stderr
, "Failed to blit\n");
2967 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
2969 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2970 map
->x
, map
->y
, map
->w
, map
->h
,
2971 mt
, _mesa_get_format_name(mt
->format
),
2972 level
, slice
, map
->ptr
, map
->stride
);
2977 intel_miptree_release(&map
->linear_mt
);
2983 intel_miptree_unmap_blit(struct brw_context
*brw
,
2984 struct intel_mipmap_tree
*mt
,
2985 struct intel_miptree_map
*map
,
2989 struct gl_context
*ctx
= &brw
->ctx
;
2991 intel_miptree_unmap_raw(map
->linear_mt
);
2993 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2994 bool ok
= intel_miptree_copy(brw
,
2995 map
->linear_mt
, 0, 0, 0, 0,
2996 mt
, level
, slice
, map
->x
, map
->y
,
2998 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3001 intel_miptree_release(&map
->linear_mt
);
3005 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3007 #if defined(USE_SSE41)
3009 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3010 struct intel_mipmap_tree
*mt
,
3011 struct intel_miptree_map
*map
,
3012 unsigned int level
, unsigned int slice
)
3014 assert(map
->mode
& GL_MAP_READ_BIT
);
3015 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3017 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3018 map
->x
, map
->y
, map
->w
, map
->h
,
3019 mt
, _mesa_get_format_name(mt
->format
),
3020 level
, slice
, map
->ptr
, map
->stride
);
3022 /* Map the original image */
3025 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3029 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3035 src
+= image_y
* mt
->surf
.row_pitch
;
3036 src
+= image_x
* mt
->cpp
;
3038 /* Due to the pixel offsets for the particular image being mapped, our
3039 * src pointer may not be 16-byte aligned. However, if the pitch is
3040 * divisible by 16, then the amount by which it's misaligned will remain
3041 * consistent from row to row.
3043 assert((mt
->surf
.row_pitch
% 16) == 0);
3044 const int misalignment
= ((uintptr_t) src
) & 15;
3046 /* Create an untiled temporary buffer for the mapping. */
3047 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3049 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3051 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3052 /* Offset the destination so it has the same misalignment as src. */
3053 map
->ptr
= map
->buffer
+ misalignment
;
3055 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3057 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3058 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3059 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch
;
3061 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3064 intel_miptree_unmap_raw(mt
);
3068 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3069 struct intel_mipmap_tree
*mt
,
3070 struct intel_miptree_map
*map
,
3074 _mesa_align_free(map
->buffer
);
3081 intel_miptree_map_s8(struct brw_context
*brw
,
3082 struct intel_mipmap_tree
*mt
,
3083 struct intel_miptree_map
*map
,
3084 unsigned int level
, unsigned int slice
)
3086 map
->stride
= map
->w
;
3087 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3091 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3092 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3093 * invalidate is set, since we'll be writing the whole rectangle from our
3094 * temporary buffer back out.
3096 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3097 uint8_t *untiled_s8_map
= map
->ptr
;
3098 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3099 unsigned int image_x
, image_y
;
3101 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3103 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3104 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3105 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3106 x
+ image_x
+ map
->x
,
3107 y
+ image_y
+ map
->y
,
3108 brw
->has_swizzling
);
3109 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3113 intel_miptree_unmap_raw(mt
);
3115 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3116 map
->x
, map
->y
, map
->w
, map
->h
,
3117 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3119 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3120 map
->x
, map
->y
, map
->w
, map
->h
,
3121 mt
, map
->ptr
, map
->stride
);
3126 intel_miptree_unmap_s8(struct brw_context
*brw
,
3127 struct intel_mipmap_tree
*mt
,
3128 struct intel_miptree_map
*map
,
3132 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3133 unsigned int image_x
, image_y
;
3134 uint8_t *untiled_s8_map
= map
->ptr
;
3135 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3137 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3139 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3140 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3141 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3142 image_x
+ x
+ map
->x
,
3143 image_y
+ y
+ map
->y
,
3144 brw
->has_swizzling
);
3145 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3149 intel_miptree_unmap_raw(mt
);
3156 intel_miptree_map_etc(struct brw_context
*brw
,
3157 struct intel_mipmap_tree
*mt
,
3158 struct intel_miptree_map
*map
,
3162 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3163 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3164 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3167 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3168 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3170 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3171 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3172 map
->w
, map
->h
, 1));
3173 map
->ptr
= map
->buffer
;
3177 intel_miptree_unmap_etc(struct brw_context
*brw
,
3178 struct intel_mipmap_tree
*mt
,
3179 struct intel_miptree_map
*map
,
3185 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3190 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3191 + image_y
* mt
->surf
.row_pitch
3192 + image_x
* mt
->cpp
;
3194 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3195 _mesa_etc1_unpack_rgba8888(dst
, mt
->surf
.row_pitch
,
3196 map
->ptr
, map
->stride
,
3199 _mesa_unpack_etc2_format(dst
, mt
->surf
.row_pitch
,
3200 map
->ptr
, map
->stride
,
3201 map
->w
, map
->h
, mt
->etc_format
);
3203 intel_miptree_unmap_raw(mt
);
3208 * Mapping function for packed depth/stencil miptrees backed by real separate
3209 * miptrees for depth and stencil.
3211 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3212 * separate from the depth buffer. Yet at the GL API level, we have to expose
3213 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3214 * be able to map that memory for texture storage and glReadPixels-type
3215 * operations. We give Mesa core that access by mallocing a temporary and
3216 * copying the data between the actual backing store and the temporary.
3219 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3220 struct intel_mipmap_tree
*mt
,
3221 struct intel_miptree_map
*map
,
3222 unsigned int level
, unsigned int slice
)
3224 struct intel_mipmap_tree
*z_mt
= mt
;
3225 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3226 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3227 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3229 map
->stride
= map
->w
* packed_bpp
;
3230 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3234 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3235 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3236 * invalidate is set, since we'll be writing the whole rectangle from our
3237 * temporary buffer back out.
3239 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3240 uint32_t *packed_map
= map
->ptr
;
3241 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3242 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3243 unsigned int s_image_x
, s_image_y
;
3244 unsigned int z_image_x
, z_image_y
;
3246 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3247 &s_image_x
, &s_image_y
);
3248 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3249 &z_image_x
, &z_image_y
);
3251 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3252 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3253 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3254 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3257 brw
->has_swizzling
);
3258 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3259 (z_mt
->surf
.row_pitch
/ 4) +
3260 (map_x
+ z_image_x
));
3261 uint8_t s
= s_map
[s_offset
];
3262 uint32_t z
= z_map
[z_offset
];
3264 if (map_z32f_x24s8
) {
3265 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3266 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3268 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3273 intel_miptree_unmap_raw(s_mt
);
3274 intel_miptree_unmap_raw(z_mt
);
3276 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3278 map
->x
, map
->y
, map
->w
, map
->h
,
3279 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3280 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3281 map
->ptr
, map
->stride
);
3283 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3284 map
->x
, map
->y
, map
->w
, map
->h
,
3285 mt
, map
->ptr
, map
->stride
);
3290 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3291 struct intel_mipmap_tree
*mt
,
3292 struct intel_miptree_map
*map
,
3296 struct intel_mipmap_tree
*z_mt
= mt
;
3297 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3298 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3300 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3301 uint32_t *packed_map
= map
->ptr
;
3302 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3303 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3304 unsigned int s_image_x
, s_image_y
;
3305 unsigned int z_image_x
, z_image_y
;
3307 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3308 &s_image_x
, &s_image_y
);
3309 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3310 &z_image_x
, &z_image_y
);
3312 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3313 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3314 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3315 x
+ s_image_x
+ map
->x
,
3316 y
+ s_image_y
+ map
->y
,
3317 brw
->has_swizzling
);
3318 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3319 (z_mt
->surf
.row_pitch
/ 4) +
3320 (x
+ z_image_x
+ map
->x
));
3322 if (map_z32f_x24s8
) {
3323 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3324 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3326 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3327 s_map
[s_offset
] = packed
>> 24;
3328 z_map
[z_offset
] = packed
;
3333 intel_miptree_unmap_raw(s_mt
);
3334 intel_miptree_unmap_raw(z_mt
);
3336 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3338 map
->x
, map
->y
, map
->w
, map
->h
,
3339 z_mt
, _mesa_get_format_name(z_mt
->format
),
3340 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3341 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3342 map
->ptr
, map
->stride
);
3349 * Create and attach a map to the miptree at (level, slice). Return the
3352 static struct intel_miptree_map
*
3353 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3362 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3367 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3368 mt
->level
[level
].slice
[slice
].map
= map
;
3380 * Release the map at (level, slice).
3383 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3387 struct intel_miptree_map
**map
;
3389 map
= &mt
->level
[level
].slice
[slice
].map
;
3395 can_blit_slice(struct intel_mipmap_tree
*mt
,
3396 unsigned int level
, unsigned int slice
)
3398 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3399 if (mt
->surf
.row_pitch
>= 32768)
3406 use_intel_mipree_map_blit(struct brw_context
*brw
,
3407 struct intel_mipmap_tree
*mt
,
3413 /* It's probably not worth swapping to the blit ring because of
3414 * all the overhead involved.
3416 !(mode
& GL_MAP_WRITE_BIT
) &&
3418 (mt
->surf
.tiling
== ISL_TILING_X
||
3419 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3420 (brw
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3421 /* Fast copy blit on skl+ supports all tiling formats. */
3423 can_blit_slice(mt
, level
, slice
))
3426 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3427 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3428 assert(can_blit_slice(mt
, level
, slice
));
3436 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3437 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3438 * arithmetic overflow.
3440 * If you call this function and use \a out_stride, then you're doing pointer
3441 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3442 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3443 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3444 * which usually have type uint32_t or GLuint.
3447 intel_miptree_map(struct brw_context
*brw
,
3448 struct intel_mipmap_tree
*mt
,
3457 ptrdiff_t *out_stride
)
3459 struct intel_miptree_map
*map
;
3461 assert(mt
->surf
.samples
== 1);
3463 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3470 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3471 map
->mode
& GL_MAP_WRITE_BIT
);
3473 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3474 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3475 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3476 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3477 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3478 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3479 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3480 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3481 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3482 #if defined(USE_SSE41)
3483 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3484 !mt
->compressed
&& cpu_has_sse4_1
&&
3485 (mt
->surf
.row_pitch
% 16 == 0)) {
3486 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3489 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3492 *out_ptr
= map
->ptr
;
3493 *out_stride
= map
->stride
;
3495 if (map
->ptr
== NULL
)
3496 intel_miptree_release_map(mt
, level
, slice
);
3500 intel_miptree_unmap(struct brw_context
*brw
,
3501 struct intel_mipmap_tree
*mt
,
3505 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3507 assert(mt
->surf
.samples
== 1);
3512 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3513 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3515 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3516 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3517 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3518 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3519 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3520 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3521 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3522 } else if (map
->linear_mt
) {
3523 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3524 #if defined(USE_SSE41)
3525 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3526 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3529 intel_miptree_unmap_gtt(mt
);
3532 intel_miptree_release_map(mt
, level
, slice
);
3536 get_isl_surf_dim(GLenum target
)
3540 case GL_TEXTURE_1D_ARRAY
:
3541 return ISL_SURF_DIM_1D
;
3544 case GL_TEXTURE_2D_ARRAY
:
3545 case GL_TEXTURE_RECTANGLE
:
3546 case GL_TEXTURE_CUBE_MAP
:
3547 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3548 case GL_TEXTURE_2D_MULTISAMPLE
:
3549 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3550 case GL_TEXTURE_EXTERNAL_OES
:
3551 return ISL_SURF_DIM_2D
;
3554 return ISL_SURF_DIM_3D
;
3557 unreachable("Invalid texture target");
3561 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3562 enum isl_tiling tiling
, GLenum target
)
3566 case GL_TEXTURE_1D_ARRAY
:
3567 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3568 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3571 case GL_TEXTURE_2D_ARRAY
:
3572 case GL_TEXTURE_RECTANGLE
:
3573 case GL_TEXTURE_2D_MULTISAMPLE
:
3574 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3575 case GL_TEXTURE_EXTERNAL_OES
:
3576 return ISL_DIM_LAYOUT_GEN4_2D
;
3578 case GL_TEXTURE_CUBE_MAP
:
3579 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3580 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3581 ISL_DIM_LAYOUT_GEN4_2D
);
3584 return (devinfo
->gen
>= 9 ?
3585 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3588 unreachable("Invalid texture target");
3592 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3593 const struct intel_mipmap_tree
*mt
)
3596 return ISL_AUX_USAGE_HIZ
;
3599 return ISL_AUX_USAGE_NONE
;
3601 return mt
->aux_usage
;