2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
28 #include <drm_fourcc.h>
30 #include "intel_batchbuffer.h"
31 #include "intel_image.h"
32 #include "intel_mipmap_tree.h"
33 #include "intel_tex.h"
34 #include "intel_blit.h"
35 #include "intel_fbo.h"
37 #include "brw_blorp.h"
38 #include "brw_context.h"
39 #include "brw_state.h"
41 #include "main/enums.h"
42 #include "main/fbobject.h"
43 #include "main/formats.h"
44 #include "main/glformats.h"
45 #include "main/texcompress_etc.h"
46 #include "main/teximage.h"
47 #include "main/streaming-load-memcpy.h"
48 #include "x86/common_x86_asm.h"
50 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
52 static void *intel_miptree_map_raw(struct brw_context
*brw
,
53 struct intel_mipmap_tree
*mt
,
56 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
59 intel_miptree_alloc_aux(struct brw_context
*brw
,
60 struct intel_mipmap_tree
*mt
);
63 intel_miptree_supports_mcs(struct brw_context
*brw
,
64 const struct intel_mipmap_tree
*mt
)
66 /* MCS compression only applies to multisampled miptrees */
67 if (mt
->surf
.samples
<= 1)
70 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
74 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
75 switch (_mesa_get_format_base_format(mt
->format
)) {
76 case GL_DEPTH_COMPONENT
:
77 case GL_STENCIL_INDEX
:
78 case GL_DEPTH_STENCIL
:
81 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
83 * This field must be set to 0 for all SINT MSRTs when all RT channels
86 * In practice this means that we have to disable MCS for all signed
87 * integer MSAA buffers. The alternative, to disable MCS only when one
88 * of the render target channels is disabled, is impractical because it
89 * would require converting between CMS and UMS MSAA layouts on the fly,
92 if (brw
->gen
== 7 && _mesa_get_format_datatype(mt
->format
) == GL_INT
) {
101 intel_tiling_supports_ccs(const struct brw_context
*brw
,
102 enum isl_tiling tiling
)
104 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
105 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
107 * - Support is limited to tiled render targets.
109 * Gen9 changes the restriction to Y-tile only.
112 return tiling
== ISL_TILING_Y0
;
113 else if (brw
->gen
>= 7)
114 return tiling
!= ISL_TILING_LINEAR
;
120 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
121 * can be used. This doesn't (and should not) inspect any of the properties of
124 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
125 * beneath the "Fast Color Clear" bullet (p326):
127 * - Support is for non-mip-mapped and non-array surface types only.
129 * And then later, on p327:
131 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
134 * From the Skylake documentation, it is made clear that X-tiling is no longer
137 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
141 intel_miptree_supports_ccs(struct brw_context
*brw
,
142 const struct intel_mipmap_tree
*mt
)
144 /* MCS support does not exist prior to Gen7 */
148 /* This function applies only to non-multisampled render targets. */
149 if (mt
->surf
.samples
> 1)
152 /* MCS is only supported for color buffers */
153 switch (_mesa_get_format_base_format(mt
->format
)) {
154 case GL_DEPTH_COMPONENT
:
155 case GL_DEPTH_STENCIL
:
156 case GL_STENCIL_INDEX
:
160 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
163 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
164 const bool arrayed
= mt
->surf
.logical_level0_px
.array_len
> 1 ||
165 mt
->surf
.logical_level0_px
.depth
> 1;
168 /* Multisample surfaces with the CMS layout are not layered surfaces,
169 * yet still have physical_depth0 > 1. Assert that we don't
170 * accidentally reject a multisampled surface here. We should have
171 * rejected it earlier by explicitly checking the sample count.
173 assert(mt
->surf
.samples
== 1);
176 /* Handle the hardware restrictions...
178 * All GENs have the following restriction: "MCS buffer for non-MSRT is
179 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
181 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
182 * Non-MultiSampler Render Target Restrictions) Support is for
183 * non-mip-mapped and non-array surface types only.
185 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
186 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
187 * surfaces are supported with MCS buffer layout with these alignments in
188 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
190 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
191 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
192 * surfaces are supported with MCS buffer layout with these alignments in
193 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
195 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
198 /* There's no point in using an MCS buffer if the surface isn't in a
201 if (!brw
->mesa_format_supports_render
[mt
->format
])
208 intel_tiling_supports_hiz(const struct brw_context
*brw
,
209 enum isl_tiling tiling
)
214 return tiling
== ISL_TILING_Y0
;
218 intel_miptree_supports_hiz(const struct brw_context
*brw
,
219 const struct intel_mipmap_tree
*mt
)
224 switch (mt
->format
) {
225 case MESA_FORMAT_Z_FLOAT32
:
226 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
227 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
228 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
229 case MESA_FORMAT_Z_UNORM16
:
237 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
238 const struct intel_mipmap_tree
*mt
)
243 /* For now compression is only enabled for integer formats even though
244 * there exist supported floating point formats also. This is a heuristic
245 * decision based on current public benchmarks. In none of the cases these
246 * formats provided any improvement but a few cases were seen to regress.
247 * Hence these are left to to be enabled in the future when they are known
250 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
253 if (!intel_miptree_supports_ccs(brw
, mt
))
256 /* Many window system buffers are sRGB even if they are never rendered as
257 * sRGB. For those, we want CCS_E for when sRGBEncode is false. When the
258 * surface is used as sRGB, we fall back to CCS_D.
260 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
261 enum isl_format isl_format
= brw_isl_format_for_mesa_format(linear_format
);
262 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
266 * Determine depth format corresponding to a depth+stencil format,
267 * for separate stencil.
270 intel_depth_format_for_depthstencil_format(mesa_format format
) {
272 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
273 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
274 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
275 return MESA_FORMAT_Z_FLOAT32
;
282 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
283 unsigned depth0
, struct intel_mipmap_level
*table
)
285 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
287 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
289 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
290 if (!table
[level
].slice
)
297 for (unsigned level
= first_level
; level
<= last_level
; level
++)
298 free(table
[level
].slice
);
304 needs_separate_stencil(const struct brw_context
*brw
,
305 struct intel_mipmap_tree
*mt
,
308 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
311 if (brw
->must_use_separate_stencil
)
314 return brw
->has_separate_stencil
&&
315 intel_miptree_supports_hiz(brw
, mt
);
319 * Choose the aux usage for this miptree. This function must be called fairly
320 * late in the miptree create process after we have a tiling.
323 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
324 struct intel_mipmap_tree
*mt
)
326 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
328 if (intel_miptree_supports_mcs(brw
, mt
)) {
329 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
330 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
331 } else if (intel_tiling_supports_ccs(brw
, mt
->surf
.tiling
) &&
332 intel_miptree_supports_ccs(brw
, mt
)) {
333 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
334 intel_miptree_supports_ccs_e(brw
, mt
)) {
335 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
337 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
339 } else if (intel_tiling_supports_hiz(brw
, mt
->surf
.tiling
) &&
340 intel_miptree_supports_hiz(brw
, mt
)) {
341 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
344 /* We can do fast-clear on all auxiliary surface types that are
345 * allocated through the normal texture creation paths.
347 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
348 mt
->supports_fast_clear
= true;
353 * Choose an appropriate uncompressed format for a requested
354 * compressed format, if unsupported.
357 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
359 /* No need to lower ETC formats on these platforms,
360 * they are supported natively.
362 if (brw
->gen
>= 8 || brw
->is_baytrail
)
366 case MESA_FORMAT_ETC1_RGB8
:
367 return MESA_FORMAT_R8G8B8X8_UNORM
;
368 case MESA_FORMAT_ETC2_RGB8
:
369 return MESA_FORMAT_R8G8B8X8_UNORM
;
370 case MESA_FORMAT_ETC2_SRGB8
:
371 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
372 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
373 return MESA_FORMAT_B8G8R8A8_SRGB
;
374 case MESA_FORMAT_ETC2_RGBA8_EAC
:
375 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
376 return MESA_FORMAT_R8G8B8A8_UNORM
;
377 case MESA_FORMAT_ETC2_R11_EAC
:
378 return MESA_FORMAT_R_UNORM16
;
379 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
380 return MESA_FORMAT_R_SNORM16
;
381 case MESA_FORMAT_ETC2_RG11_EAC
:
382 return MESA_FORMAT_R16G16_UNORM
;
383 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
384 return MESA_FORMAT_R16G16_SNORM
;
386 /* Non ETC1 / ETC2 format */
392 brw_get_num_logical_layers(const struct intel_mipmap_tree
*mt
, unsigned level
)
394 if (mt
->surf
.dim
== ISL_SURF_DIM_3D
)
395 return minify(mt
->surf
.logical_level0_px
.depth
, level
);
397 return mt
->surf
.logical_level0_px
.array_len
;
401 get_num_phys_layers(const struct isl_surf
*surf
, unsigned level
)
403 /* In case of physical dimensions one needs to consider also the layout.
404 * See isl_calc_phys_level0_extent_sa().
406 if (surf
->dim
!= ISL_SURF_DIM_3D
)
407 return surf
->phys_level0_sa
.array_len
;
409 if (surf
->dim_layout
== ISL_DIM_LAYOUT_GEN4_2D
)
410 return minify(surf
->phys_level0_sa
.array_len
, level
);
412 return minify(surf
->phys_level0_sa
.depth
, level
);
415 /** \brief Assert that the level and layer are valid for the miptree. */
417 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
425 assert(level
>= mt
->first_level
);
426 assert(level
<= mt
->last_level
);
427 assert(layer
< get_num_phys_layers(&mt
->surf
, level
));
430 static enum isl_aux_state
**
431 create_aux_state_map(struct intel_mipmap_tree
*mt
,
432 enum isl_aux_state initial
)
434 const uint32_t levels
= mt
->last_level
+ 1;
436 uint32_t total_slices
= 0;
437 for (uint32_t level
= 0; level
< levels
; level
++)
438 total_slices
+= brw_get_num_logical_layers(mt
, level
);
440 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
442 /* We're going to allocate a single chunk of data for both the per-level
443 * reference array and the arrays of aux_state. This makes cleanup
444 * significantly easier.
446 const size_t total_size
= per_level_array_size
+
447 total_slices
* sizeof(enum isl_aux_state
);
448 void *data
= malloc(total_size
);
452 enum isl_aux_state
**per_level_arr
= data
;
453 enum isl_aux_state
*s
= data
+ per_level_array_size
;
454 for (uint32_t level
= 0; level
< levels
; level
++) {
455 per_level_arr
[level
] = s
;
456 const unsigned level_layers
= brw_get_num_logical_layers(mt
, level
);
457 for (uint32_t a
= 0; a
< level_layers
; a
++)
460 assert((void *)s
== data
+ total_size
);
462 return per_level_arr
;
466 free_aux_state_map(enum isl_aux_state
**state
)
472 need_to_retile_as_linear(struct brw_context
*brw
, unsigned row_pitch
,
473 enum isl_tiling tiling
, unsigned samples
)
478 if (tiling
== ISL_TILING_LINEAR
)
481 /* If the width is much smaller than a tile, don't bother tiling. */
485 if (ALIGN(row_pitch
, 512) >= 32768) {
486 perf_debug("row pitch %u too large to blit, falling back to untiled",
495 need_to_retile_as_x(const struct brw_context
*brw
, uint64_t size
,
496 enum isl_tiling tiling
)
498 /* If the BO is too large to fit in the aperture, we need to use the
499 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
500 * handle Y-tiling, so we need to fall back to X.
502 if (brw
->gen
< 6 && size
>= brw
->max_gtt_map_object_size
&&
503 tiling
== ISL_TILING_Y0
)
509 static struct intel_mipmap_tree
*
510 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
511 unsigned first_level
, unsigned last_level
,
512 unsigned width0
, unsigned height0
, unsigned depth0
,
513 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
514 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
515 unsigned row_pitch
, struct brw_bo
*bo
)
517 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
521 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
529 if (target
== GL_TEXTURE_CUBE_MAP
||
530 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
531 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
533 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
535 _mesa_enum_to_string(target
),
536 _mesa_get_format_name(format
),
537 num_samples
, width0
, height0
, depth0
,
538 first_level
, last_level
, mt
);
540 struct isl_surf_init_info init_info
= {
541 .dim
= get_isl_surf_dim(target
),
542 .format
= translate_tex_format(brw
, format
, false),
545 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
546 .levels
= last_level
- first_level
+ 1,
547 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
548 .samples
= num_samples
,
549 .row_pitch
= row_pitch
,
550 .usage
= isl_usage_flags
,
551 .tiling_flags
= tiling_flags
,
554 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
557 /* In case caller doesn't specifically request Y-tiling (needed
558 * unconditionally for depth), check for corner cases needing special
561 if (tiling_flags
& ~ISL_TILING_Y0_BIT
) {
562 if (need_to_retile_as_linear(brw
, mt
->surf
.row_pitch
,
563 mt
->surf
.tiling
, mt
->surf
.samples
)) {
564 init_info
.tiling_flags
= 1u << ISL_TILING_LINEAR
;
565 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
567 } else if (need_to_retile_as_x(brw
, mt
->surf
.size
, mt
->surf
.tiling
)) {
568 init_info
.tiling_flags
= 1u << ISL_TILING_X
;
569 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
574 /* In case of linear the buffer gets padded by fixed 64 bytes and therefore
575 * the size may not be multiple of row_pitch.
576 * See isl_apply_surface_padding().
578 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
)
579 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
582 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
584 isl_tiling_to_i915_tiling(
586 mt
->surf
.row_pitch
, alloc_flags
);
593 mt
->first_level
= first_level
;
594 mt
->last_level
= last_level
;
597 mt
->aux_state
= NULL
;
598 mt
->cpp
= isl_format_get_layout(mt
->surf
.format
)->bpb
/ 8;
599 mt
->compressed
= _mesa_is_format_compressed(format
);
600 mt
->drm_modifier
= DRM_FORMAT_MOD_INVALID
;
605 intel_miptree_release(&mt
);
610 make_separate_stencil_surface(struct brw_context
*brw
,
611 struct intel_mipmap_tree
*mt
)
613 mt
->stencil_mt
= make_surface(brw
, mt
->target
, MESA_FORMAT_S_UINT8
,
614 0, mt
->surf
.levels
- 1,
615 mt
->surf
.logical_level0_px
.width
,
616 mt
->surf
.logical_level0_px
.height
,
617 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
618 mt
->surf
.logical_level0_px
.depth
:
619 mt
->surf
.logical_level0_px
.array_len
,
620 mt
->surf
.samples
, ISL_TILING_W_BIT
,
621 ISL_SURF_USAGE_STENCIL_BIT
|
622 ISL_SURF_USAGE_TEXTURE_BIT
,
623 BO_ALLOC_FOR_RENDER
, 0, NULL
);
628 mt
->stencil_mt
->r8stencil_needs_update
= true;
633 static struct intel_mipmap_tree
*
634 miptree_create(struct brw_context
*brw
,
643 enum intel_miptree_create_flags flags
)
645 if (format
== MESA_FORMAT_S_UINT8
)
646 return make_surface(brw
, target
, format
, first_level
, last_level
,
647 width0
, height0
, depth0
, num_samples
,
649 ISL_SURF_USAGE_STENCIL_BIT
|
650 ISL_SURF_USAGE_TEXTURE_BIT
,
655 const GLenum base_format
= _mesa_get_format_base_format(format
);
656 if ((base_format
== GL_DEPTH_COMPONENT
||
657 base_format
== GL_DEPTH_STENCIL
) &&
658 !(flags
& MIPTREE_CREATE_LINEAR
)) {
659 /* Fix up the Z miptree format for how we're splitting out separate
660 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
662 const mesa_format depth_only_format
=
663 intel_depth_format_for_depthstencil_format(format
);
664 struct intel_mipmap_tree
*mt
= make_surface(
665 brw
, target
, brw
->gen
>= 6 ? depth_only_format
: format
,
666 first_level
, last_level
,
667 width0
, height0
, depth0
, num_samples
, ISL_TILING_Y0_BIT
,
668 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
669 BO_ALLOC_FOR_RENDER
, 0, NULL
);
671 if (needs_separate_stencil(brw
, mt
, format
) &&
672 !make_separate_stencil_surface(brw
, mt
)) {
673 intel_miptree_release(&mt
);
677 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
678 intel_miptree_choose_aux_usage(brw
, mt
);
683 mesa_format tex_format
= format
;
684 mesa_format etc_format
= MESA_FORMAT_NONE
;
685 uint32_t alloc_flags
= 0;
687 format
= intel_lower_compressed_format(brw
, format
);
689 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
691 if (flags
& MIPTREE_CREATE_BUSY
)
692 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
694 isl_tiling_flags_t tiling_flags
= (flags
& MIPTREE_CREATE_LINEAR
) ?
695 ISL_TILING_LINEAR_BIT
: ISL_TILING_ANY_MASK
;
697 /* TODO: This used to be because there wasn't BLORP to handle Y-tiling. */
699 tiling_flags
&= ~ISL_TILING_Y0_BIT
;
701 struct intel_mipmap_tree
*mt
= make_surface(
703 first_level
, last_level
,
704 width0
, height0
, depth0
,
705 num_samples
, tiling_flags
,
706 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
707 ISL_SURF_USAGE_TEXTURE_BIT
,
708 alloc_flags
, 0, NULL
);
712 mt
->etc_format
= etc_format
;
714 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
715 intel_miptree_choose_aux_usage(brw
, mt
);
720 struct intel_mipmap_tree
*
721 intel_miptree_create(struct brw_context
*brw
,
730 enum intel_miptree_create_flags flags
)
732 assert(num_samples
> 0);
734 struct intel_mipmap_tree
*mt
= miptree_create(
736 first_level
, last_level
,
737 width0
, height0
, depth0
, num_samples
,
744 if (!intel_miptree_alloc_aux(brw
, mt
)) {
745 intel_miptree_release(&mt
);
752 struct intel_mipmap_tree
*
753 intel_miptree_create_for_bo(struct brw_context
*brw
,
761 enum intel_miptree_create_flags flags
)
763 struct intel_mipmap_tree
*mt
;
764 uint32_t tiling
, swizzle
;
765 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
766 const GLenum base_format
= _mesa_get_format_base_format(format
);
768 if ((base_format
== GL_DEPTH_COMPONENT
||
769 base_format
== GL_DEPTH_STENCIL
)) {
770 const mesa_format depth_only_format
=
771 intel_depth_format_for_depthstencil_format(format
);
772 mt
= make_surface(brw
, target
,
773 brw
->gen
>= 6 ? depth_only_format
: format
,
774 0, 0, width
, height
, depth
, 1, ISL_TILING_Y0_BIT
,
775 ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
,
776 BO_ALLOC_FOR_RENDER
, pitch
, bo
);
780 brw_bo_reference(bo
);
782 if (!(flags
& MIPTREE_CREATE_NO_AUX
))
783 intel_miptree_choose_aux_usage(brw
, mt
);
786 } else if (format
== MESA_FORMAT_S_UINT8
) {
787 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
788 0, 0, width
, height
, depth
, 1,
790 ISL_SURF_USAGE_STENCIL_BIT
|
791 ISL_SURF_USAGE_TEXTURE_BIT
,
792 BO_ALLOC_FOR_RENDER
, pitch
, bo
);
796 assert(bo
->size
>= mt
->surf
.size
);
798 brw_bo_reference(bo
);
802 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
804 /* Nothing will be able to use this miptree with the BO if the offset isn't
807 if (tiling
!= I915_TILING_NONE
)
808 assert(offset
% 4096 == 0);
810 /* miptrees can't handle negative pitch. If you need flipping of images,
811 * that's outside of the scope of the mt.
815 /* The BO already has a tiling format and we shouldn't confuse the lower
816 * layers by making it try to find a tiling format again.
818 assert((flags
& MIPTREE_CREATE_LINEAR
) == 0);
820 mt
= make_surface(brw
, target
, format
,
821 0, 0, width
, height
, depth
, 1,
822 1lu << isl_tiling_from_i915_tiling(tiling
),
823 ISL_SURF_USAGE_RENDER_TARGET_BIT
|
824 ISL_SURF_USAGE_TEXTURE_BIT
,
829 brw_bo_reference(bo
);
833 if (!(flags
& MIPTREE_CREATE_NO_AUX
)) {
834 intel_miptree_choose_aux_usage(brw
, mt
);
836 if (!intel_miptree_alloc_aux(brw
, mt
)) {
837 intel_miptree_release(&mt
);
845 static struct intel_mipmap_tree
*
846 miptree_create_for_planar_image(struct brw_context
*brw
,
847 __DRIimage
*image
, GLenum target
)
849 const struct intel_image_format
*f
= image
->planar_format
;
850 struct intel_mipmap_tree
*planar_mt
= NULL
;
852 for (int i
= 0; i
< f
->nplanes
; i
++) {
853 const int index
= f
->planes
[i
].buffer_index
;
854 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
855 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
856 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
857 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
859 /* Disable creation of the texture's aux buffers because the driver
860 * exposes no EGL API to manage them. That is, there is no API for
861 * resolving the aux buffer's content to the main buffer nor for
862 * invalidating the aux buffer's content.
864 struct intel_mipmap_tree
*mt
=
865 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
866 image
->offsets
[index
],
868 image
->strides
[index
],
869 MIPTREE_CREATE_NO_AUX
);
878 planar_mt
->plane
[i
- 1] = mt
;
881 planar_mt
->drm_modifier
= image
->modifier
;
887 create_ccs_buf_for_image(struct brw_context
*brw
,
889 struct intel_mipmap_tree
*mt
,
890 enum isl_aux_state initial_state
)
892 struct isl_surf temp_ccs_surf
;
894 /* CCS is only supported for very simple miptrees */
895 assert(image
->aux_offset
!= 0 && image
->aux_pitch
!= 0);
896 assert(image
->tile_x
== 0 && image
->tile_y
== 0);
897 assert(mt
->surf
.samples
== 1);
898 assert(mt
->surf
.levels
== 1);
899 assert(mt
->surf
.logical_level0_px
.depth
== 1);
900 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
901 assert(mt
->first_level
== 0);
902 assert(mt
->last_level
== 0);
904 /* We shouldn't already have a CCS */
905 assert(!mt
->mcs_buf
);
907 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
,
911 assert(image
->aux_offset
< image
->bo
->size
);
912 assert(temp_ccs_surf
.size
<= image
->bo
->size
- image
->aux_offset
);
914 mt
->mcs_buf
= calloc(sizeof(*mt
->mcs_buf
), 1);
915 if (mt
->mcs_buf
== NULL
)
918 mt
->aux_state
= create_aux_state_map(mt
, initial_state
);
919 if (!mt
->aux_state
) {
925 mt
->mcs_buf
->bo
= image
->bo
;
926 brw_bo_reference(image
->bo
);
928 mt
->mcs_buf
->offset
= image
->aux_offset
;
929 mt
->mcs_buf
->size
= image
->bo
->size
- image
->aux_offset
;
930 mt
->mcs_buf
->pitch
= image
->aux_pitch
;
931 mt
->mcs_buf
->qpitch
= 0;
932 mt
->mcs_buf
->surf
= temp_ccs_surf
;
937 struct intel_mipmap_tree
*
938 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
939 __DRIimage
*image
, GLenum target
,
940 enum isl_colorspace colorspace
,
941 bool is_winsys_image
)
943 if (image
->planar_format
&& image
->planar_format
->nplanes
> 1) {
944 assert(colorspace
== ISL_COLORSPACE_NONE
||
945 colorspace
== ISL_COLORSPACE_YUV
);
946 return miptree_create_for_planar_image(brw
, image
, target
);
949 if (image
->planar_format
)
950 assert(image
->planar_format
->planes
[0].dri_format
== image
->dri_format
);
952 mesa_format format
= image
->format
;
953 switch (colorspace
) {
954 case ISL_COLORSPACE_NONE
:
955 /* Keep the image format unmodified */
958 case ISL_COLORSPACE_LINEAR
:
959 format
=_mesa_get_srgb_format_linear(format
);
962 case ISL_COLORSPACE_SRGB
:
963 format
=_mesa_get_linear_format_srgb(format
);
967 unreachable("Inalid colorspace for non-planar image");
970 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
971 /* The texture storage paths in core Mesa detect if the driver does not
972 * support the user-requested format, and then searches for a
973 * fallback format. The DRIimage code bypasses core Mesa, though. So we
974 * do the fallbacks here for important formats.
976 * We must support DRM_FOURCC_XBGR8888 textures because the Android
977 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
978 * the Chrome OS compositor consumes as dma_buf EGLImages.
980 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
983 if (!brw
->ctx
.TextureFormatSupported
[format
])
986 const struct isl_drm_modifier_info
*mod_info
=
987 isl_drm_modifier_get_info(image
->modifier
);
989 enum intel_miptree_create_flags mt_create_flags
= 0;
991 /* If this image comes in from a window system, we have different
992 * requirements than if it comes in via an EGL import operation. Window
993 * system images can use any form of auxiliary compression we wish because
994 * they get "flushed" before being handed off to the window system and we
995 * have the opportunity to do resolves. Non window-system images, on the
996 * other hand, have no resolve point so we can't have aux without a
999 if (!is_winsys_image
)
1000 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1002 /* If we have a modifier which specifies aux, don't create one yet */
1003 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
)
1004 mt_create_flags
|= MIPTREE_CREATE_NO_AUX
;
1006 /* Disable creation of the texture's aux buffers because the driver exposes
1007 * no EGL API to manage them. That is, there is no API for resolving the aux
1008 * buffer's content to the main buffer nor for invalidating the aux buffer's
1011 struct intel_mipmap_tree
*mt
=
1012 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1013 image
->offset
, image
->width
, image
->height
, 1,
1014 image
->pitch
, mt_create_flags
);
1018 mt
->target
= target
;
1019 mt
->level
[0].level_x
= image
->tile_x
;
1020 mt
->level
[0].level_y
= image
->tile_y
;
1021 mt
->drm_modifier
= image
->modifier
;
1023 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1024 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1025 * trouble resolving back to destination image due to alignment issues.
1027 if (!brw
->has_surface_tile_offset
) {
1028 uint32_t draw_x
, draw_y
;
1029 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1031 if (draw_x
!= 0 || draw_y
!= 0) {
1032 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1033 intel_miptree_release(&mt
);
1038 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
1039 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
1041 mt
->aux_usage
= mod_info
->aux_usage
;
1042 /* If we are a window system buffer, then we can support fast-clears
1043 * even if the modifier doesn't support them by doing a partial resolve
1044 * as part of the flush operation.
1046 mt
->supports_fast_clear
=
1047 is_winsys_image
|| mod_info
->supports_clear_color
;
1049 /* We don't know the actual state of the surface when we get it but we
1050 * can make a pretty good guess based on the modifier. What we do know
1051 * for sure is that it isn't in the AUX_INVALID state, so we just assume
1052 * a worst case of compression.
1054 enum isl_aux_state initial_state
=
1055 mod_info
->supports_clear_color
? ISL_AUX_STATE_COMPRESSED_CLEAR
:
1056 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
;
1058 if (!create_ccs_buf_for_image(brw
, image
, mt
, initial_state
)) {
1059 intel_miptree_release(&mt
);
1064 /* Don't assume coherency for imported EGLimages. We don't know what
1065 * external clients are going to do with it. They may scan it out.
1067 image
->bo
->cache_coherent
= false;
1073 * For a singlesample renderbuffer, this simply wraps the given BO with a
1076 * For a multisample renderbuffer, this wraps the window system's
1077 * (singlesample) BO with a singlesample miptree attached to the
1078 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1079 * that will contain the actual rendering (which is lazily resolved to
1080 * irb->singlesample_mt).
1083 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1084 struct intel_renderbuffer
*irb
,
1085 struct intel_mipmap_tree
*singlesample_mt
,
1086 uint32_t width
, uint32_t height
,
1089 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1090 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1091 mesa_format format
= rb
->Format
;
1092 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1094 /* Only the front and back buffers, which are color buffers, are allocated
1095 * through the image loader.
1097 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1098 _mesa_get_format_base_format(format
) == GL_RGBA
);
1100 assert(singlesample_mt
);
1102 if (num_samples
== 1) {
1103 intel_miptree_release(&irb
->mt
);
1104 irb
->mt
= singlesample_mt
;
1106 assert(!irb
->singlesample_mt
);
1108 intel_miptree_release(&irb
->singlesample_mt
);
1109 irb
->singlesample_mt
= singlesample_mt
;
1112 irb
->mt
->surf
.logical_level0_px
.width
!= width
||
1113 irb
->mt
->surf
.logical_level0_px
.height
!= height
) {
1114 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1119 if (!multisample_mt
)
1122 irb
->need_downsample
= false;
1123 intel_miptree_release(&irb
->mt
);
1124 irb
->mt
= multisample_mt
;
1130 intel_miptree_release(&irb
->mt
);
1134 struct intel_mipmap_tree
*
1135 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1139 uint32_t num_samples
)
1141 struct intel_mipmap_tree
*mt
;
1143 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1145 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1146 width
, height
, depth
, num_samples
,
1147 MIPTREE_CREATE_BUSY
);
1154 intel_miptree_release(&mt
);
1159 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1160 struct intel_mipmap_tree
*src
)
1165 intel_miptree_release(dst
);
1169 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1176 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1178 if (aux_buf
== NULL
)
1181 brw_bo_unreference(aux_buf
->bo
);
1187 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1192 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1193 if (--(*mt
)->refcount
<= 0) {
1196 DBG("%s deleting %p\n", __func__
, *mt
);
1198 brw_bo_unreference((*mt
)->bo
);
1199 intel_miptree_release(&(*mt
)->stencil_mt
);
1200 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1201 intel_miptree_aux_buffer_free((*mt
)->hiz_buf
);
1202 intel_miptree_aux_buffer_free((*mt
)->mcs_buf
);
1203 free_aux_state_map((*mt
)->aux_state
);
1205 intel_miptree_release(&(*mt
)->plane
[0]);
1206 intel_miptree_release(&(*mt
)->plane
[1]);
1208 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1209 free((*mt
)->level
[i
].slice
);
1219 intel_get_image_dims(struct gl_texture_image
*image
,
1220 int *width
, int *height
, int *depth
)
1222 switch (image
->TexObject
->Target
) {
1223 case GL_TEXTURE_1D_ARRAY
:
1224 /* For a 1D Array texture the OpenGL API will treat the image height as
1225 * the number of array slices. For Intel hardware, we treat the 1D array
1226 * as a 2D Array with a height of 1. So, here we want to swap image
1229 assert(image
->Depth
== 1);
1230 *width
= image
->Width
;
1232 *depth
= image
->Height
;
1234 case GL_TEXTURE_CUBE_MAP
:
1235 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1236 * though we really have 6 slices.
1238 assert(image
->Depth
== 1);
1239 *width
= image
->Width
;
1240 *height
= image
->Height
;
1244 *width
= image
->Width
;
1245 *height
= image
->Height
;
1246 *depth
= image
->Depth
;
1252 * Can the image be pulled into a unified mipmap tree? This mirrors
1253 * the completeness test in a lot of ways.
1255 * Not sure whether I want to pass gl_texture_image here.
1258 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1259 struct gl_texture_image
*image
)
1261 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1262 GLuint level
= intelImage
->base
.Base
.Level
;
1263 int width
, height
, depth
;
1265 /* glTexImage* choose the texture object based on the target passed in, and
1266 * objects can't change targets over their lifetimes, so this should be
1269 assert(image
->TexObject
->Target
== mt
->target
);
1271 mesa_format mt_format
= mt
->format
;
1272 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1273 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1274 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1275 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1276 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1277 mt_format
= mt
->etc_format
;
1279 if (image
->TexFormat
!= mt_format
)
1282 intel_get_image_dims(image
, &width
, &height
, &depth
);
1284 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1287 if (level
>= mt
->surf
.levels
)
1290 const unsigned level_depth
=
1291 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1292 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1293 mt
->surf
.logical_level0_px
.array_len
;
1295 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1296 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1297 depth
== level_depth
&&
1298 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1302 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1303 GLuint level
, GLuint slice
,
1304 GLuint
*x
, GLuint
*y
)
1306 if (level
== 0 && slice
== 0) {
1307 *x
= mt
->level
[0].level_x
;
1308 *y
= mt
->level
[0].level_y
;
1312 uint32_t x_offset_sa
, y_offset_sa
;
1314 /* Miptree itself can have an offset only if it represents a single
1315 * slice in an imported buffer object.
1316 * See intel_miptree_create_for_dri_image().
1318 assert(mt
->level
[0].level_x
== 0);
1319 assert(mt
->level
[0].level_y
== 0);
1321 /* Given level is relative to level zero while the miptree may be
1322 * represent just a subset of all levels starting from 'first_level'.
1324 assert(level
>= mt
->first_level
);
1325 level
-= mt
->first_level
;
1327 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1328 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1329 isl_surf_get_image_offset_el(&mt
->surf
, level
, slice
, z
,
1330 &x_offset_sa
, &y_offset_sa
);
1338 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1339 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1340 * and tile_h is set to 1.
1343 intel_get_tile_dims(enum isl_tiling tiling
, uint32_t cpp
,
1344 uint32_t *tile_w
, uint32_t *tile_h
)
1355 case ISL_TILING_LINEAR
:
1360 unreachable("not reached");
1366 * This function computes masks that may be used to select the bits of the X
1367 * and Y coordinates that indicate the offset within a tile. If the BO is
1368 * untiled, the masks are set to 0.
1371 intel_get_tile_masks(enum isl_tiling tiling
, uint32_t cpp
,
1372 uint32_t *mask_x
, uint32_t *mask_y
)
1374 uint32_t tile_w_bytes
, tile_h
;
1376 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1378 *mask_x
= tile_w_bytes
/ cpp
- 1;
1379 *mask_y
= tile_h
- 1;
1383 * Compute the offset (in bytes) from the start of the BO to the given x
1384 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1385 * multiples of the tile size.
1388 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1389 uint32_t x
, uint32_t y
)
1392 uint32_t pitch
= mt
->surf
.row_pitch
;
1394 switch (mt
->surf
.tiling
) {
1396 unreachable("not reached");
1397 case ISL_TILING_LINEAR
:
1398 return y
* pitch
+ x
* cpp
;
1400 assert((x
% (512 / cpp
)) == 0);
1401 assert((y
% 8) == 0);
1402 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1404 assert((x
% (128 / cpp
)) == 0);
1405 assert((y
% 32) == 0);
1406 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1411 * Rendering with tiled buffers requires that the base address of the buffer
1412 * be aligned to a page boundary. For renderbuffers, and sometimes with
1413 * textures, we may want the surface to point at a texture image level that
1414 * isn't at a page boundary.
1416 * This function returns an appropriately-aligned base offset
1417 * according to the tiling restrictions, plus any required x/y offset
1421 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1422 GLuint level
, GLuint slice
,
1427 uint32_t mask_x
, mask_y
;
1429 intel_get_tile_masks(mt
->surf
.tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1430 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1432 *tile_x
= x
& mask_x
;
1433 *tile_y
= y
& mask_y
;
1435 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1439 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1440 struct intel_mipmap_tree
*src_mt
,
1441 unsigned src_level
, unsigned src_layer
,
1442 struct intel_mipmap_tree
*dst_mt
,
1443 unsigned dst_level
, unsigned dst_layer
,
1444 unsigned width
, unsigned height
)
1447 ptrdiff_t src_stride
, dst_stride
;
1448 const unsigned cpp
= (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8);
1450 intel_miptree_map(brw
, src_mt
,
1451 src_level
, src_layer
,
1454 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1457 intel_miptree_map(brw
, dst_mt
,
1458 dst_level
, dst_layer
,
1461 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1465 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1466 _mesa_get_format_name(src_mt
->format
),
1467 src_mt
, src
, src_stride
,
1468 _mesa_get_format_name(dst_mt
->format
),
1469 dst_mt
, dst
, dst_stride
,
1472 int row_size
= cpp
* width
;
1473 if (src_stride
== row_size
&&
1474 dst_stride
== row_size
) {
1475 memcpy(dst
, src
, row_size
* height
);
1477 for (int i
= 0; i
< height
; i
++) {
1478 memcpy(dst
, src
, row_size
);
1484 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1485 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1487 /* Don't forget to copy the stencil data over, too. We could have skipped
1488 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1489 * shuffling the two data sources in/out of temporary storage instead of
1490 * the direct mapping we get this way.
1492 if (dst_mt
->stencil_mt
) {
1493 assert(src_mt
->stencil_mt
);
1494 intel_miptree_copy_slice_sw(brw
,
1495 src_mt
->stencil_mt
, src_level
, src_layer
,
1496 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1502 intel_miptree_copy_slice(struct brw_context
*brw
,
1503 struct intel_mipmap_tree
*src_mt
,
1504 unsigned src_level
, unsigned src_layer
,
1505 struct intel_mipmap_tree
*dst_mt
,
1506 unsigned dst_level
, unsigned dst_layer
)
1509 mesa_format format
= src_mt
->format
;
1510 unsigned width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1511 src_level
- src_mt
->first_level
);
1512 unsigned height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1513 src_level
- src_mt
->first_level
);
1515 assert(src_layer
< get_num_phys_layers(&src_mt
->surf
,
1516 src_level
- src_mt
->first_level
));
1518 assert(src_mt
->format
== dst_mt
->format
);
1520 if (dst_mt
->compressed
) {
1522 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1523 height
= ALIGN_NPOT(height
, j
) / j
;
1524 width
= ALIGN_NPOT(width
, i
) / i
;
1527 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1528 * below won't apply since we can't do the depth's Y tiling or the
1529 * stencil's W tiling in the blitter.
1531 if (src_mt
->stencil_mt
) {
1532 intel_miptree_copy_slice_sw(brw
,
1533 src_mt
, src_level
, src_layer
,
1534 dst_mt
, dst_level
, dst_layer
,
1539 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1540 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1542 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1545 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1546 _mesa_get_format_name(src_mt
->format
),
1547 src_mt
, src_x
, src_y
, src_mt
->surf
.row_pitch
,
1548 _mesa_get_format_name(dst_mt
->format
),
1549 dst_mt
, dst_x
, dst_y
, dst_mt
->surf
.row_pitch
,
1552 if (!intel_miptree_blit(brw
,
1553 src_mt
, src_level
, src_layer
, 0, 0, false,
1554 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1555 width
, height
, GL_COPY
)) {
1556 perf_debug("miptree validate blit for %s failed\n",
1557 _mesa_get_format_name(format
));
1559 intel_miptree_copy_slice_sw(brw
,
1560 src_mt
, src_level
, src_layer
,
1561 dst_mt
, dst_level
, dst_layer
,
1567 * Copies the image's current data to the given miptree, and associates that
1568 * miptree with the image.
1570 * If \c invalidate is true, then the actual image data does not need to be
1571 * copied, but the image still needs to be associated to the new miptree (this
1572 * is set to true if we're about to clear the image).
1575 intel_miptree_copy_teximage(struct brw_context
*brw
,
1576 struct intel_texture_image
*intelImage
,
1577 struct intel_mipmap_tree
*dst_mt
,
1580 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1581 struct intel_texture_object
*intel_obj
=
1582 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1583 int level
= intelImage
->base
.Base
.Level
;
1584 const unsigned face
= intelImage
->base
.Base
.Face
;
1585 unsigned start_layer
, end_layer
;
1587 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1589 assert(intelImage
->base
.Base
.Height
);
1591 end_layer
= intelImage
->base
.Base
.Height
- 1;
1592 } else if (face
> 0) {
1596 assert(intelImage
->base
.Base
.Depth
);
1598 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1602 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1603 intel_miptree_copy_slice(brw
,
1609 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1610 intel_obj
->needs_validate
= true;
1614 intel_miptree_init_mcs(struct brw_context
*brw
,
1615 struct intel_mipmap_tree
*mt
,
1618 assert(mt
->mcs_buf
!= NULL
);
1620 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1622 * When MCS buffer is enabled and bound to MSRT, it is required that it
1623 * is cleared prior to any rendering.
1625 * Since we don't use the MCS buffer for any purpose other than rendering,
1626 * it makes sense to just clear it immediately upon allocation.
1628 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1630 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1631 if (unlikely(map
== NULL
)) {
1632 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1633 brw_bo_unreference(mt
->mcs_buf
->bo
);
1638 memset(data
, init_value
, mt
->mcs_buf
->size
);
1639 brw_bo_unmap(mt
->mcs_buf
->bo
);
1642 static struct intel_miptree_aux_buffer
*
1643 intel_alloc_aux_buffer(struct brw_context
*brw
,
1645 const struct isl_surf
*aux_surf
,
1646 uint32_t alloc_flags
,
1647 struct intel_mipmap_tree
*mt
)
1649 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1653 buf
->size
= aux_surf
->size
;
1654 buf
->pitch
= aux_surf
->row_pitch
;
1655 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1657 /* ISL has stricter set of alignment rules then the drm allocator.
1658 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1659 * trying to recalculate based on different format block sizes.
1661 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1662 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1668 buf
->surf
= *aux_surf
;
1674 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1675 struct intel_mipmap_tree
*mt
,
1678 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1679 assert(mt
->mcs_buf
== NULL
);
1680 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1682 /* Multisampled miptrees are only supported for single level. */
1683 assert(mt
->first_level
== 0);
1684 enum isl_aux_state
**aux_state
=
1685 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1689 struct isl_surf temp_mcs_surf
;
1691 MAYBE_UNUSED
bool ok
=
1692 isl_surf_get_mcs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_mcs_surf
);
1695 /* Buffer needs to be initialised requiring the buffer to be immediately
1696 * mapped to cpu space for writing. Therefore do not use the gpu access
1697 * flag which can cause an unnecessary delay if the backing pages happened
1698 * to be just used by the GPU.
1700 const uint32_t alloc_flags
= 0;
1701 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1702 &temp_mcs_surf
, alloc_flags
, mt
);
1708 mt
->aux_state
= aux_state
;
1710 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1716 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1717 struct intel_mipmap_tree
*mt
)
1719 assert(mt
->mcs_buf
== NULL
);
1720 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1721 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1723 struct isl_surf temp_ccs_surf
;
1725 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &mt
->surf
, &temp_ccs_surf
, 0))
1728 assert(temp_ccs_surf
.size
&&
1729 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1731 enum isl_aux_state
**aux_state
=
1732 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1736 /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
1737 * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
1739 * "If Software wants to enable Color Compression without Fast clear,
1740 * Software needs to initialize MCS with zeros."
1742 * A CCS value of 0 indicates that the corresponding block is in the
1743 * pass-through state which is what we want.
1745 * For CCS_D, on the other hand, we don't care as we're about to perform a
1746 * fast-clear operation. In that case, being hot in caches more useful.
1748 const uint32_t alloc_flags
= mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
?
1749 BO_ALLOC_ZEROED
: BO_ALLOC_FOR_RENDER
;
1750 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
1751 &temp_ccs_surf
, alloc_flags
, mt
);
1757 mt
->aux_state
= aux_state
;
1763 * Helper for intel_miptree_alloc_hiz() that sets
1764 * \c mt->level[level].has_hiz. Return true if and only if
1765 * \c has_hiz was set.
1768 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1769 struct intel_mipmap_tree
*mt
,
1772 assert(mt
->hiz_buf
);
1773 assert(mt
->surf
.size
> 0);
1775 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1776 uint32_t width
= minify(mt
->surf
.phys_level0_sa
.width
, level
);
1777 uint32_t height
= minify(mt
->surf
.phys_level0_sa
.height
, level
);
1779 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1780 * and the height is 4 aligned. This allows our HiZ support
1781 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1782 * we can grow the width & height to allow the HiZ op to
1783 * force the proper size alignments.
1785 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1786 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1791 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1792 mt
->level
[level
].has_hiz
= true;
1797 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1798 struct intel_mipmap_tree
*mt
)
1800 assert(mt
->hiz_buf
== NULL
);
1801 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
1803 enum isl_aux_state
**aux_state
=
1804 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1808 struct isl_surf temp_hiz_surf
;
1810 MAYBE_UNUSED
bool ok
=
1811 isl_surf_get_hiz_surf(&brw
->isl_dev
, &mt
->surf
, &temp_hiz_surf
);
1814 const uint32_t alloc_flags
= BO_ALLOC_FOR_RENDER
;
1815 mt
->hiz_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
1816 &temp_hiz_surf
, alloc_flags
, mt
);
1823 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1824 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1826 mt
->aux_state
= aux_state
;
1833 * Allocate the initial aux surface for a miptree based on mt->aux_usage
1835 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
1836 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
1837 * compress clear color so we wait until an actual fast-clear to allocate it.
1840 intel_miptree_alloc_aux(struct brw_context
*brw
,
1841 struct intel_mipmap_tree
*mt
)
1843 switch (mt
->aux_usage
) {
1844 case ISL_AUX_USAGE_NONE
:
1847 case ISL_AUX_USAGE_HIZ
:
1848 assert(!_mesa_is_format_color_format(mt
->format
));
1849 if (!intel_miptree_alloc_hiz(brw
, mt
))
1853 case ISL_AUX_USAGE_MCS
:
1854 assert(_mesa_is_format_color_format(mt
->format
));
1855 assert(mt
->surf
.samples
> 1);
1856 if (!intel_miptree_alloc_mcs(brw
, mt
, mt
->surf
.samples
))
1860 case ISL_AUX_USAGE_CCS_D
:
1861 /* Since CCS_D can only compress clear color so we wait until an actual
1862 * fast-clear to allocate it.
1866 case ISL_AUX_USAGE_CCS_E
:
1867 assert(_mesa_is_format_color_format(mt
->format
));
1868 assert(mt
->surf
.samples
== 1);
1869 if (!intel_miptree_alloc_ccs(brw
, mt
))
1874 unreachable("Invalid aux usage");
1879 * Can the miptree sample using the hiz buffer?
1882 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
1883 struct intel_mipmap_tree
*mt
)
1885 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
1886 * so keep things conservative for now and never enable it unless we're SKL+.
1896 /* It seems the hardware won't fallback to the depth buffer if some of the
1897 * mipmap levels aren't available in the HiZ buffer. So we need all levels
1898 * of the texture to be HiZ enabled.
1900 for (unsigned level
= 0; level
< mt
->surf
.levels
; ++level
) {
1901 if (!intel_miptree_level_has_hiz(mt
, level
))
1905 /* If compressed multisampling is enabled, then we use it for the auxiliary
1908 * From the BDW PRM (Volume 2d: Command Reference: Structures
1909 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
1911 * "If this field is set to AUX_HIZ, Number of Multisamples must be
1912 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
1914 * There is no such blurb for 1D textures, but there is sufficient evidence
1915 * that this is broken on SKL+.
1917 return (mt
->surf
.samples
== 1 &&
1918 mt
->target
!= GL_TEXTURE_3D
&&
1919 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
1923 * Does the miptree slice have hiz enabled?
1926 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
1928 intel_miptree_check_level_layer(mt
, level
, 0);
1929 return mt
->level
[level
].has_hiz
;
1932 static inline uint32_t
1933 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
1934 uint32_t start_level
, uint32_t num_levels
)
1936 assert(start_level
>= mt
->first_level
);
1937 assert(start_level
<= mt
->last_level
);
1939 if (num_levels
== INTEL_REMAINING_LAYERS
)
1940 num_levels
= mt
->last_level
- start_level
+ 1;
1941 /* Check for overflow */
1942 assert(start_level
+ num_levels
>= start_level
);
1943 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
1948 static inline uint32_t
1949 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
1950 uint32_t start_layer
, uint32_t num_layers
)
1952 assert(level
<= mt
->last_level
);
1954 const uint32_t total_num_layers
= brw_get_num_logical_layers(mt
, level
);
1955 assert(start_layer
< total_num_layers
);
1956 if (num_layers
== INTEL_REMAINING_LAYERS
)
1957 num_layers
= total_num_layers
- start_layer
;
1958 /* Check for overflow */
1959 assert(start_layer
+ num_layers
>= start_layer
);
1960 assert(start_layer
+ num_layers
<= total_num_layers
);
1966 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
1967 unsigned start_level
, unsigned num_levels
,
1968 unsigned start_layer
, unsigned num_layers
)
1970 assert(_mesa_is_format_color_format(mt
->format
));
1975 /* Clamp the level range to fit the miptree */
1976 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
1978 for (uint32_t l
= 0; l
< num_levels
; l
++) {
1979 const uint32_t level
= start_level
+ l
;
1980 const uint32_t level_layers
=
1981 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
1982 for (unsigned a
= 0; a
< level_layers
; a
++) {
1983 enum isl_aux_state aux_state
=
1984 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
1985 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
1986 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
1995 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
1996 const struct intel_mipmap_tree
*mt
,
1997 unsigned level
, unsigned layer
)
2003 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2004 assert(brw
->gen
>= 8 ||
2005 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2007 /* Compression of arrayed msaa surfaces is supported. */
2008 if (mt
->surf
.samples
> 1)
2011 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2012 assert(brw
->gen
>= 8 ||
2014 mt
->surf
.logical_level0_px
.depth
== 1 &&
2015 mt
->surf
.logical_level0_px
.array_len
== 1));
2021 static enum blorp_fast_clear_op
2022 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2023 enum isl_aux_usage aux_usage
,
2024 bool fast_clear_supported
)
2026 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_CCS_D
);
2028 const bool ccs_supported
= aux_usage
== ISL_AUX_USAGE_CCS_D
;
2030 assert(ccs_supported
== fast_clear_supported
);
2032 switch (aux_state
) {
2033 case ISL_AUX_STATE_CLEAR
:
2034 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2036 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2038 return BLORP_FAST_CLEAR_OP_NONE
;
2040 case ISL_AUX_STATE_PASS_THROUGH
:
2041 return BLORP_FAST_CLEAR_OP_NONE
;
2043 case ISL_AUX_STATE_RESOLVED
:
2044 case ISL_AUX_STATE_AUX_INVALID
:
2045 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2046 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2050 unreachable("Invalid aux state for CCS_D");
2053 static enum blorp_fast_clear_op
2054 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2055 enum isl_aux_usage aux_usage
,
2056 bool fast_clear_supported
)
2058 /* CCS_E surfaces can be accessed as CCS_D if we're careful. */
2059 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2060 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2061 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2063 if (aux_usage
== ISL_AUX_USAGE_CCS_D
)
2064 assert(fast_clear_supported
);
2066 switch (aux_state
) {
2067 case ISL_AUX_STATE_CLEAR
:
2068 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2069 if (fast_clear_supported
)
2070 return BLORP_FAST_CLEAR_OP_NONE
;
2071 else if (aux_usage
== ISL_AUX_USAGE_CCS_E
)
2072 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2074 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2076 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2077 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2078 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2079 else if (!fast_clear_supported
)
2080 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2082 return BLORP_FAST_CLEAR_OP_NONE
;
2084 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2085 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2086 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2088 return BLORP_FAST_CLEAR_OP_NONE
;
2090 case ISL_AUX_STATE_PASS_THROUGH
:
2091 return BLORP_FAST_CLEAR_OP_NONE
;
2093 case ISL_AUX_STATE_RESOLVED
:
2094 case ISL_AUX_STATE_AUX_INVALID
:
2098 unreachable("Invalid aux state for CCS_E");
2102 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2103 struct intel_mipmap_tree
*mt
,
2104 uint32_t level
, uint32_t layer
,
2105 enum isl_aux_usage aux_usage
,
2106 bool fast_clear_supported
)
2108 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2110 enum blorp_fast_clear_op resolve_op
;
2111 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2112 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_usage
,
2113 fast_clear_supported
);
2115 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2116 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_usage
,
2117 fast_clear_supported
);
2120 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2121 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2122 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2124 switch (resolve_op
) {
2125 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2126 /* The CCS full resolve operation destroys the CCS and sets it to the
2127 * pass-through state. (You can also think of this as being both a
2128 * resolve and an ambiguate in one operation.)
2130 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2131 ISL_AUX_STATE_PASS_THROUGH
);
2134 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2135 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2136 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2140 unreachable("Invalid resolve op");
2146 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2147 struct intel_mipmap_tree
*mt
,
2148 uint32_t level
, uint32_t layer
,
2149 enum isl_aux_usage aux_usage
)
2151 assert(aux_usage
== ISL_AUX_USAGE_NONE
||
2152 aux_usage
== ISL_AUX_USAGE_CCS_D
||
2153 aux_usage
== ISL_AUX_USAGE_CCS_E
);
2155 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2157 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2158 switch (aux_state
) {
2159 case ISL_AUX_STATE_CLEAR
:
2160 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2161 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
||
2162 aux_usage
== ISL_AUX_USAGE_CCS_D
);
2164 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2165 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2166 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2167 } else if (aux_state
!= ISL_AUX_STATE_PARTIAL_CLEAR
) {
2168 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2169 ISL_AUX_STATE_PARTIAL_CLEAR
);
2173 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2174 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2175 assert(aux_usage
== ISL_AUX_USAGE_CCS_E
);
2176 break; /* Nothing to do */
2178 case ISL_AUX_STATE_PASS_THROUGH
:
2179 if (aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2180 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2181 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2187 case ISL_AUX_STATE_RESOLVED
:
2188 case ISL_AUX_STATE_AUX_INVALID
:
2189 unreachable("Invalid aux state for CCS_E");
2192 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2193 /* CCS_D is a bit simpler */
2194 switch (aux_state
) {
2195 case ISL_AUX_STATE_CLEAR
:
2196 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2197 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2198 ISL_AUX_STATE_PARTIAL_CLEAR
);
2201 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2202 assert(aux_usage
== ISL_AUX_USAGE_CCS_D
);
2203 break; /* Nothing to do */
2205 case ISL_AUX_STATE_PASS_THROUGH
:
2209 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2210 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2211 case ISL_AUX_STATE_RESOLVED
:
2212 case ISL_AUX_STATE_AUX_INVALID
:
2213 unreachable("Invalid aux state for CCS_D");
2219 intel_miptree_prepare_mcs_access(struct brw_context
*brw
,
2220 struct intel_mipmap_tree
*mt
,
2222 enum isl_aux_usage aux_usage
,
2223 bool fast_clear_supported
)
2225 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2227 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2228 case ISL_AUX_STATE_CLEAR
:
2229 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2230 if (!fast_clear_supported
) {
2231 brw_blorp_mcs_partial_resolve(brw
, mt
, layer
, 1);
2232 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2233 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2237 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2238 break; /* Nothing to do */
2240 case ISL_AUX_STATE_RESOLVED
:
2241 case ISL_AUX_STATE_PASS_THROUGH
:
2242 case ISL_AUX_STATE_AUX_INVALID
:
2243 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2244 unreachable("Invalid aux state for MCS");
2249 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2250 struct intel_mipmap_tree
*mt
,
2252 enum isl_aux_usage aux_usage
)
2254 assert(aux_usage
== ISL_AUX_USAGE_MCS
);
2256 switch (intel_miptree_get_aux_state(mt
, 0, layer
)) {
2257 case ISL_AUX_STATE_CLEAR
:
2258 intel_miptree_set_aux_state(brw
, mt
, 0, layer
, 1,
2259 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2262 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2263 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2264 break; /* Nothing to do */
2266 case ISL_AUX_STATE_RESOLVED
:
2267 case ISL_AUX_STATE_PASS_THROUGH
:
2268 case ISL_AUX_STATE_AUX_INVALID
:
2269 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2270 unreachable("Invalid aux state for MCS");
2275 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2276 struct intel_mipmap_tree
*mt
,
2277 uint32_t level
, uint32_t layer
,
2278 enum isl_aux_usage aux_usage
,
2279 bool fast_clear_supported
)
2281 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2283 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2284 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2285 case ISL_AUX_STATE_CLEAR
:
2286 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2287 if (aux_usage
!= ISL_AUX_USAGE_HIZ
|| !fast_clear_supported
)
2288 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2291 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2292 if (aux_usage
!= ISL_AUX_USAGE_HIZ
)
2293 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2296 case ISL_AUX_STATE_PASS_THROUGH
:
2297 case ISL_AUX_STATE_RESOLVED
:
2300 case ISL_AUX_STATE_AUX_INVALID
:
2301 if (aux_usage
== ISL_AUX_USAGE_HIZ
)
2302 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2305 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2306 unreachable("Invalid HiZ state");
2309 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2310 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2313 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2314 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2315 ISL_AUX_STATE_RESOLVED
);
2318 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2319 /* The HiZ resolve operation is actually an ambiguate */
2320 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2321 ISL_AUX_STATE_PASS_THROUGH
);
2325 unreachable("Invalid HiZ op");
2331 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2332 struct intel_mipmap_tree
*mt
,
2333 uint32_t level
, uint32_t layer
,
2334 enum isl_aux_usage aux_usage
)
2336 assert(aux_usage
== ISL_AUX_USAGE_NONE
|| aux_usage
== ISL_AUX_USAGE_HIZ
);
2338 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2339 case ISL_AUX_STATE_CLEAR
:
2340 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2341 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2342 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2345 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2346 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2347 assert(aux_usage
== ISL_AUX_USAGE_HIZ
);
2348 break; /* Nothing to do */
2350 case ISL_AUX_STATE_RESOLVED
:
2351 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2352 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2353 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2355 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2356 ISL_AUX_STATE_AUX_INVALID
);
2360 case ISL_AUX_STATE_PASS_THROUGH
:
2361 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
2362 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2363 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2367 case ISL_AUX_STATE_AUX_INVALID
:
2368 assert(aux_usage
!= ISL_AUX_USAGE_HIZ
);
2371 case ISL_AUX_STATE_PARTIAL_CLEAR
:
2372 unreachable("Invalid HiZ state");
2377 intel_miptree_prepare_access(struct brw_context
*brw
,
2378 struct intel_mipmap_tree
*mt
,
2379 uint32_t start_level
, uint32_t num_levels
,
2380 uint32_t start_layer
, uint32_t num_layers
,
2381 enum isl_aux_usage aux_usage
,
2382 bool fast_clear_supported
)
2384 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2386 switch (mt
->aux_usage
) {
2387 case ISL_AUX_USAGE_NONE
:
2391 case ISL_AUX_USAGE_MCS
:
2392 assert(mt
->mcs_buf
);
2393 assert(start_level
== 0 && num_levels
== 1);
2394 const uint32_t level_layers
=
2395 miptree_layer_range_length(mt
, 0, start_layer
, num_layers
);
2396 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2397 intel_miptree_prepare_mcs_access(brw
, mt
, start_layer
+ a
,
2398 aux_usage
, fast_clear_supported
);
2402 case ISL_AUX_USAGE_CCS_D
:
2403 case ISL_AUX_USAGE_CCS_E
:
2407 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2408 const uint32_t level
= start_level
+ l
;
2409 const uint32_t level_layers
=
2410 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2411 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2412 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2414 aux_usage
, fast_clear_supported
);
2419 case ISL_AUX_USAGE_HIZ
:
2420 assert(mt
->hiz_buf
);
2421 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2422 const uint32_t level
= start_level
+ l
;
2423 if (!intel_miptree_level_has_hiz(mt
, level
))
2426 const uint32_t level_layers
=
2427 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2428 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2429 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2430 aux_usage
, fast_clear_supported
);
2436 unreachable("Invalid aux usage");
2441 intel_miptree_finish_write(struct brw_context
*brw
,
2442 struct intel_mipmap_tree
*mt
, uint32_t level
,
2443 uint32_t start_layer
, uint32_t num_layers
,
2444 enum isl_aux_usage aux_usage
)
2446 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2448 switch (mt
->aux_usage
) {
2449 case ISL_AUX_USAGE_NONE
:
2453 case ISL_AUX_USAGE_MCS
:
2454 assert(mt
->mcs_buf
);
2455 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2456 intel_miptree_finish_mcs_write(brw
, mt
, start_layer
+ a
,
2461 case ISL_AUX_USAGE_CCS_D
:
2462 case ISL_AUX_USAGE_CCS_E
:
2466 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2467 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2472 case ISL_AUX_USAGE_HIZ
:
2473 if (!intel_miptree_level_has_hiz(mt
, level
))
2476 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2477 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2483 unreachable("Invavlid aux usage");
2488 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2489 uint32_t level
, uint32_t layer
)
2491 intel_miptree_check_level_layer(mt
, level
, layer
);
2493 if (_mesa_is_format_color_format(mt
->format
)) {
2494 assert(mt
->mcs_buf
!= NULL
);
2495 assert(mt
->surf
.samples
== 1 ||
2496 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2497 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2498 unreachable("Cannot get aux state for stencil");
2500 assert(intel_miptree_level_has_hiz(mt
, level
));
2503 return mt
->aux_state
[level
][layer
];
2507 intel_miptree_set_aux_state(struct brw_context
*brw
,
2508 struct intel_mipmap_tree
*mt
, uint32_t level
,
2509 uint32_t start_layer
, uint32_t num_layers
,
2510 enum isl_aux_state aux_state
)
2512 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2514 if (_mesa_is_format_color_format(mt
->format
)) {
2515 assert(mt
->mcs_buf
!= NULL
);
2516 assert(mt
->surf
.samples
== 1 ||
2517 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2518 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2519 unreachable("Cannot get aux state for stencil");
2521 assert(intel_miptree_level_has_hiz(mt
, level
));
2524 for (unsigned a
= 0; a
< num_layers
; a
++)
2525 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2528 /* On Gen9 color buffers may be compressed by the hardware (lossless
2529 * compression). There are, however, format restrictions and care needs to be
2530 * taken that the sampler engine is capable for re-interpreting a buffer with
2531 * format different the buffer was originally written with.
2533 * For example, SRGB formats are not compressible and the sampler engine isn't
2534 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2535 * color buffer needs to be resolved so that the sampling surface can be
2536 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2540 can_texture_with_ccs(struct brw_context
*brw
,
2541 struct intel_mipmap_tree
*mt
,
2542 enum isl_format view_format
)
2544 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2547 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2548 mt
->surf
.format
, view_format
)) {
2549 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2550 isl_format_get_layout(view_format
)->name
,
2551 _mesa_get_format_name(mt
->format
));
2559 intel_miptree_texture_aux_usage(struct brw_context
*brw
,
2560 struct intel_mipmap_tree
*mt
,
2561 enum isl_format view_format
)
2563 switch (mt
->aux_usage
) {
2564 case ISL_AUX_USAGE_HIZ
:
2565 if (intel_miptree_sample_with_hiz(brw
, mt
))
2566 return ISL_AUX_USAGE_HIZ
;
2569 case ISL_AUX_USAGE_MCS
:
2570 return ISL_AUX_USAGE_MCS
;
2572 case ISL_AUX_USAGE_CCS_D
:
2573 case ISL_AUX_USAGE_CCS_E
:
2575 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2576 return ISL_AUX_USAGE_NONE
;
2579 /* If we don't have any unresolved color, report an aux usage of
2580 * ISL_AUX_USAGE_NONE. This way, texturing won't even look at the
2581 * aux surface and we can save some bandwidth.
2583 if (!intel_miptree_has_color_unresolved(mt
, 0, INTEL_REMAINING_LEVELS
,
2584 0, INTEL_REMAINING_LAYERS
))
2585 return ISL_AUX_USAGE_NONE
;
2587 if (can_texture_with_ccs(brw
, mt
, view_format
))
2588 return ISL_AUX_USAGE_CCS_E
;
2595 return ISL_AUX_USAGE_NONE
;
2599 isl_formats_are_fast_clear_compatible(enum isl_format a
, enum isl_format b
)
2601 /* On gen8 and earlier, the hardware was only capable of handling 0/1 clear
2602 * values so sRGB curve application was a no-op for all fast-clearable
2605 * On gen9+, the hardware supports arbitrary clear values. For sRGB clear
2606 * values, the hardware interprets the floats, not as what would be
2607 * returned from the sampler (or written by the shader), but as being
2608 * between format conversion and sRGB curve application. This means that
2609 * we can switch between sRGB and UNORM without having to whack the clear
2612 return isl_format_srgb_to_linear(a
) == isl_format_srgb_to_linear(b
);
2616 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2617 struct intel_mipmap_tree
*mt
,
2618 enum isl_format view_format
,
2619 uint32_t start_level
, uint32_t num_levels
,
2620 uint32_t start_layer
, uint32_t num_layers
,
2621 bool *aux_supported_out
)
2623 enum isl_aux_usage aux_usage
=
2624 intel_miptree_texture_aux_usage(brw
, mt
, view_format
);
2625 bool clear_supported
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2627 /* Clear color is specified as ints or floats and the conversion is done by
2628 * the sampler. If we have a texture view, we would have to perform the
2629 * clear color conversion manually. Just disable clear color.
2631 if (!isl_formats_are_fast_clear_compatible(mt
->surf
.format
, view_format
))
2632 clear_supported
= false;
2634 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2635 start_layer
, num_layers
,
2636 aux_usage
, clear_supported
);
2637 if (aux_supported_out
)
2638 *aux_supported_out
= aux_usage
!= ISL_AUX_USAGE_NONE
;
2642 intel_miptree_prepare_texture(struct brw_context
*brw
,
2643 struct intel_mipmap_tree
*mt
,
2644 enum isl_format view_format
,
2645 bool *aux_supported_out
)
2647 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2648 0, INTEL_REMAINING_LEVELS
,
2649 0, INTEL_REMAINING_LAYERS
,
2654 intel_miptree_prepare_image(struct brw_context
*brw
,
2655 struct intel_mipmap_tree
*mt
)
2657 /* The data port doesn't understand any compression */
2658 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2659 0, INTEL_REMAINING_LAYERS
,
2660 ISL_AUX_USAGE_NONE
, false);
2664 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2665 struct intel_mipmap_tree
*mt
, uint32_t level
,
2666 uint32_t start_layer
, uint32_t num_layers
)
2668 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->surf
.format
, level
, 1,
2669 start_layer
, num_layers
, NULL
);
2673 intel_miptree_render_aux_usage(struct brw_context
*brw
,
2674 struct intel_mipmap_tree
*mt
,
2675 bool srgb_enabled
, bool blend_enabled
)
2677 switch (mt
->aux_usage
) {
2678 case ISL_AUX_USAGE_MCS
:
2679 assert(mt
->mcs_buf
);
2680 return ISL_AUX_USAGE_MCS
;
2682 case ISL_AUX_USAGE_CCS_D
:
2683 return mt
->mcs_buf
? ISL_AUX_USAGE_CCS_D
: ISL_AUX_USAGE_NONE
;
2685 case ISL_AUX_USAGE_CCS_E
: {
2686 mesa_format mesa_format
=
2687 srgb_enabled
? mt
->format
:_mesa_get_srgb_format_linear(mt
->format
);
2688 enum isl_format isl_format
= brw_isl_format_for_mesa_format(mesa_format
);
2690 /* If the format supports CCS_E, then we can just use it */
2691 if (isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
))
2692 return ISL_AUX_USAGE_CCS_E
;
2694 /* Otherwise, we have to fall back to CCS_D */
2696 /* gen9 hardware technically supports non-0/1 clear colors with sRGB
2697 * formats. However, there are issues with blending where it doesn't
2698 * properly apply the sRGB curve to the clear color when blending.
2700 if (blend_enabled
&& isl_format_is_srgb(isl_format
) &&
2701 !isl_color_value_is_zero_one(mt
->fast_clear_color
, isl_format
))
2702 return ISL_AUX_USAGE_NONE
;
2704 return ISL_AUX_USAGE_CCS_D
;
2708 return ISL_AUX_USAGE_NONE
;
2713 intel_miptree_prepare_render(struct brw_context
*brw
,
2714 struct intel_mipmap_tree
*mt
, uint32_t level
,
2715 uint32_t start_layer
, uint32_t layer_count
,
2716 bool srgb_enabled
, bool blend_enabled
)
2718 enum isl_aux_usage aux_usage
=
2719 intel_miptree_render_aux_usage(brw
, mt
, srgb_enabled
, blend_enabled
);
2720 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2721 aux_usage
, aux_usage
!= ISL_AUX_USAGE_NONE
);
2725 intel_miptree_finish_render(struct brw_context
*brw
,
2726 struct intel_mipmap_tree
*mt
, uint32_t level
,
2727 uint32_t start_layer
, uint32_t layer_count
,
2728 bool srgb_enabled
, bool blend_enabled
)
2730 assert(_mesa_is_format_color_format(mt
->format
));
2732 enum isl_aux_usage aux_usage
=
2733 intel_miptree_render_aux_usage(brw
, mt
, srgb_enabled
, blend_enabled
);
2734 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2739 intel_miptree_prepare_depth(struct brw_context
*brw
,
2740 struct intel_mipmap_tree
*mt
, uint32_t level
,
2741 uint32_t start_layer
, uint32_t layer_count
)
2743 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2744 mt
->aux_usage
, mt
->hiz_buf
!= NULL
);
2748 intel_miptree_finish_depth(struct brw_context
*brw
,
2749 struct intel_mipmap_tree
*mt
, uint32_t level
,
2750 uint32_t start_layer
, uint32_t layer_count
,
2753 if (depth_written
) {
2754 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2755 mt
->hiz_buf
!= NULL
);
2760 intel_miptree_prepare_external(struct brw_context
*brw
,
2761 struct intel_mipmap_tree
*mt
)
2763 enum isl_aux_usage aux_usage
= ISL_AUX_USAGE_NONE
;
2764 bool supports_fast_clear
= false;
2766 const struct isl_drm_modifier_info
*mod_info
=
2767 isl_drm_modifier_get_info(mt
->drm_modifier
);
2769 if (mod_info
&& mod_info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
2770 /* CCS_E is the only supported aux for external images and it's only
2771 * supported on very simple images.
2773 assert(mod_info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
2774 assert(_mesa_is_format_color_format(mt
->format
));
2775 assert(mt
->first_level
== 0 && mt
->last_level
== 0);
2776 assert(mt
->surf
.logical_level0_px
.depth
== 1);
2777 assert(mt
->surf
.logical_level0_px
.array_len
== 1);
2778 assert(mt
->surf
.samples
== 1);
2779 assert(mt
->mcs_buf
!= NULL
);
2781 aux_usage
= mod_info
->aux_usage
;
2782 supports_fast_clear
= mod_info
->supports_clear_color
;
2785 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2786 0, INTEL_REMAINING_LAYERS
,
2787 aux_usage
, supports_fast_clear
);
2791 * Make it possible to share the BO backing the given miptree with another
2792 * process or another miptree.
2794 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2795 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2796 * ensure that no MCS buffer gets allocated in the future.
2798 * HiZ is similarly unsafe with shared buffers.
2801 intel_miptree_make_shareable(struct brw_context
*brw
,
2802 struct intel_mipmap_tree
*mt
)
2804 /* MCS buffers are also used for multisample buffers, but we can't resolve
2805 * away a multisample MCS buffer because it's an integral part of how the
2806 * pixel data is stored. Fortunately this code path should never be
2807 * reached for multisample buffers.
2809 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2810 mt
->surf
.samples
== 1);
2812 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2813 0, INTEL_REMAINING_LAYERS
,
2814 ISL_AUX_USAGE_NONE
, false);
2817 brw_bo_unreference(mt
->mcs_buf
->bo
);
2821 /* Any pending MCS/CCS operations are no longer needed. Trying to
2822 * execute any will likely crash due to the missing aux buffer. So let's
2823 * delete all pending ops.
2825 free(mt
->aux_state
);
2826 mt
->aux_state
= NULL
;
2830 intel_miptree_aux_buffer_free(mt
->hiz_buf
);
2833 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2834 mt
->level
[l
].has_hiz
= false;
2837 /* Any pending HiZ operations are no longer needed. Trying to execute
2838 * any will likely crash due to the missing aux buffer. So let's delete
2841 free(mt
->aux_state
);
2842 mt
->aux_state
= NULL
;
2845 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2846 mt
->supports_fast_clear
= false;
2851 * \brief Get pointer offset into stencil buffer.
2853 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2854 * must decode the tile's layout in software.
2857 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2859 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2861 * Even though the returned offset is always positive, the return type is
2863 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2864 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2867 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2869 uint32_t tile_size
= 4096;
2870 uint32_t tile_width
= 64;
2871 uint32_t tile_height
= 64;
2872 uint32_t row_size
= 64 * stride
/ 2; /* Two rows are interleaved. */
2874 uint32_t tile_x
= x
/ tile_width
;
2875 uint32_t tile_y
= y
/ tile_height
;
2877 /* The byte's address relative to the tile's base addres. */
2878 uint32_t byte_x
= x
% tile_width
;
2879 uint32_t byte_y
= y
% tile_height
;
2881 uintptr_t u
= tile_y
* row_size
2882 + tile_x
* tile_size
2883 + 512 * (byte_x
/ 8)
2885 + 32 * ((byte_y
/ 4) % 2)
2886 + 16 * ((byte_x
/ 4) % 2)
2887 + 8 * ((byte_y
/ 2) % 2)
2888 + 4 * ((byte_x
/ 2) % 2)
2893 /* adjust for bit6 swizzling */
2894 if (((byte_x
/ 8) % 2) == 1) {
2895 if (((byte_y
/ 8) % 2) == 0) {
2907 intel_miptree_updownsample(struct brw_context
*brw
,
2908 struct intel_mipmap_tree
*src
,
2909 struct intel_mipmap_tree
*dst
)
2911 unsigned src_w
= src
->surf
.logical_level0_px
.width
;
2912 unsigned src_h
= src
->surf
.logical_level0_px
.height
;
2913 unsigned dst_w
= dst
->surf
.logical_level0_px
.width
;
2914 unsigned dst_h
= dst
->surf
.logical_level0_px
.height
;
2916 brw_blorp_blit_miptrees(brw
,
2917 src
, 0 /* level */, 0 /* layer */,
2918 src
->format
, SWIZZLE_XYZW
,
2919 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2922 GL_NEAREST
, false, false /*mirror x, y*/,
2925 if (src
->stencil_mt
) {
2926 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2927 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2928 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2929 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2931 brw_blorp_blit_miptrees(brw
,
2932 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2933 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2934 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2935 dst
->stencil_mt
->format
,
2938 GL_NEAREST
, false, false /*mirror x, y*/,
2939 false, false /* decode/encode srgb */);
2944 intel_update_r8stencil(struct brw_context
*brw
,
2945 struct intel_mipmap_tree
*mt
)
2947 assert(brw
->gen
>= 7);
2948 struct intel_mipmap_tree
*src
=
2949 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2950 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
2953 assert(src
->surf
.size
> 0);
2955 if (!mt
->r8stencil_mt
) {
2956 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2957 mt
->r8stencil_mt
= make_surface(
2960 MESA_FORMAT_R_UINT8
,
2961 src
->first_level
, src
->last_level
,
2962 src
->surf
.logical_level0_px
.width
,
2963 src
->surf
.logical_level0_px
.height
,
2964 src
->surf
.dim
== ISL_SURF_DIM_3D
?
2965 src
->surf
.logical_level0_px
.depth
:
2966 src
->surf
.logical_level0_px
.array_len
,
2969 ISL_SURF_USAGE_TEXTURE_BIT
,
2970 BO_ALLOC_FOR_RENDER
, 0, NULL
);
2971 assert(mt
->r8stencil_mt
);
2974 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2976 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2977 const unsigned depth
= src
->surf
.dim
== ISL_SURF_DIM_3D
?
2978 minify(src
->surf
.phys_level0_sa
.depth
, level
) :
2979 src
->surf
.phys_level0_sa
.array_len
;
2981 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2982 brw_blorp_copy_miptrees(brw
,
2986 minify(src
->surf
.logical_level0_px
.width
,
2988 minify(src
->surf
.logical_level0_px
.height
,
2993 brw_render_cache_set_check_flush(brw
, dst
->bo
);
2994 src
->r8stencil_needs_update
= false;
2998 intel_miptree_map_raw(struct brw_context
*brw
,
2999 struct intel_mipmap_tree
*mt
,
3002 struct brw_bo
*bo
= mt
->bo
;
3004 if (brw_batch_references(&brw
->batch
, bo
))
3005 intel_batchbuffer_flush(brw
);
3007 return brw_bo_map(brw
, bo
, mode
);
3011 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
3013 brw_bo_unmap(mt
->bo
);
3017 intel_miptree_map_gtt(struct brw_context
*brw
,
3018 struct intel_mipmap_tree
*mt
,
3019 struct intel_miptree_map
*map
,
3020 unsigned int level
, unsigned int slice
)
3022 unsigned int bw
, bh
;
3024 unsigned int image_x
, image_y
;
3025 intptr_t x
= map
->x
;
3026 intptr_t y
= map
->y
;
3028 /* For compressed formats, the stride is the number of bytes per
3029 * row of blocks. intel_miptree_get_image_offset() already does
3032 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3033 assert(y
% bh
== 0);
3034 assert(x
% bw
== 0);
3038 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3045 /* Note that in the case of cube maps, the caller must have passed the
3046 * slice number referencing the face.
3048 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3052 map
->stride
= mt
->surf
.row_pitch
;
3053 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
3056 DBG("%s: %d,%d %dx%d from mt %p (%s) "
3057 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
3058 map
->x
, map
->y
, map
->w
, map
->h
,
3059 mt
, _mesa_get_format_name(mt
->format
),
3060 x
, y
, map
->ptr
, map
->stride
);
3064 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
3066 intel_miptree_unmap_raw(mt
);
3070 intel_miptree_map_blit(struct brw_context
*brw
,
3071 struct intel_mipmap_tree
*mt
,
3072 struct intel_miptree_map
*map
,
3073 unsigned int level
, unsigned int slice
)
3075 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
3076 /* first_level */ 0,
3080 MIPTREE_CREATE_LINEAR
);
3082 if (!map
->linear_mt
) {
3083 fprintf(stderr
, "Failed to allocate blit temporary\n");
3086 map
->stride
= map
->linear_mt
->surf
.row_pitch
;
3088 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3089 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3090 * invalidate is set, since we'll be writing the whole rectangle from our
3091 * temporary buffer back out.
3093 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3094 if (!intel_miptree_copy(brw
,
3095 mt
, level
, slice
, map
->x
, map
->y
,
3096 map
->linear_mt
, 0, 0, 0, 0,
3098 fprintf(stderr
, "Failed to blit\n");
3103 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3105 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3106 map
->x
, map
->y
, map
->w
, map
->h
,
3107 mt
, _mesa_get_format_name(mt
->format
),
3108 level
, slice
, map
->ptr
, map
->stride
);
3113 intel_miptree_release(&map
->linear_mt
);
3119 intel_miptree_unmap_blit(struct brw_context
*brw
,
3120 struct intel_mipmap_tree
*mt
,
3121 struct intel_miptree_map
*map
,
3125 struct gl_context
*ctx
= &brw
->ctx
;
3127 intel_miptree_unmap_raw(map
->linear_mt
);
3129 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3130 bool ok
= intel_miptree_copy(brw
,
3131 map
->linear_mt
, 0, 0, 0, 0,
3132 mt
, level
, slice
, map
->x
, map
->y
,
3134 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3137 intel_miptree_release(&map
->linear_mt
);
3141 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3143 #if defined(USE_SSE41)
3145 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3146 struct intel_mipmap_tree
*mt
,
3147 struct intel_miptree_map
*map
,
3148 unsigned int level
, unsigned int slice
)
3150 assert(map
->mode
& GL_MAP_READ_BIT
);
3151 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3153 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3154 map
->x
, map
->y
, map
->w
, map
->h
,
3155 mt
, _mesa_get_format_name(mt
->format
),
3156 level
, slice
, map
->ptr
, map
->stride
);
3158 /* Map the original image */
3161 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3165 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3171 src
+= image_y
* mt
->surf
.row_pitch
;
3172 src
+= image_x
* mt
->cpp
;
3174 /* Due to the pixel offsets for the particular image being mapped, our
3175 * src pointer may not be 16-byte aligned. However, if the pitch is
3176 * divisible by 16, then the amount by which it's misaligned will remain
3177 * consistent from row to row.
3179 assert((mt
->surf
.row_pitch
% 16) == 0);
3180 const int misalignment
= ((uintptr_t) src
) & 15;
3182 /* Create an untiled temporary buffer for the mapping. */
3183 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3185 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3187 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3188 /* Offset the destination so it has the same misalignment as src. */
3189 map
->ptr
= map
->buffer
+ misalignment
;
3191 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3193 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3194 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3195 void *src_ptr
= src
+ y
* mt
->surf
.row_pitch
;
3197 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3200 intel_miptree_unmap_raw(mt
);
3204 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3205 struct intel_mipmap_tree
*mt
,
3206 struct intel_miptree_map
*map
,
3210 _mesa_align_free(map
->buffer
);
3217 intel_miptree_map_s8(struct brw_context
*brw
,
3218 struct intel_mipmap_tree
*mt
,
3219 struct intel_miptree_map
*map
,
3220 unsigned int level
, unsigned int slice
)
3222 map
->stride
= map
->w
;
3223 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3227 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3228 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3229 * invalidate is set, since we'll be writing the whole rectangle from our
3230 * temporary buffer back out.
3232 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3233 uint8_t *untiled_s8_map
= map
->ptr
;
3234 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3235 unsigned int image_x
, image_y
;
3237 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3239 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3240 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3241 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3242 x
+ image_x
+ map
->x
,
3243 y
+ image_y
+ map
->y
,
3244 brw
->has_swizzling
);
3245 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3249 intel_miptree_unmap_raw(mt
);
3251 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3252 map
->x
, map
->y
, map
->w
, map
->h
,
3253 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3255 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3256 map
->x
, map
->y
, map
->w
, map
->h
,
3257 mt
, map
->ptr
, map
->stride
);
3262 intel_miptree_unmap_s8(struct brw_context
*brw
,
3263 struct intel_mipmap_tree
*mt
,
3264 struct intel_miptree_map
*map
,
3268 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3269 unsigned int image_x
, image_y
;
3270 uint8_t *untiled_s8_map
= map
->ptr
;
3271 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3273 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3275 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3276 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3277 ptrdiff_t offset
= intel_offset_S8(mt
->surf
.row_pitch
,
3278 image_x
+ x
+ map
->x
,
3279 image_y
+ y
+ map
->y
,
3280 brw
->has_swizzling
);
3281 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3285 intel_miptree_unmap_raw(mt
);
3292 intel_miptree_map_etc(struct brw_context
*brw
,
3293 struct intel_mipmap_tree
*mt
,
3294 struct intel_miptree_map
*map
,
3298 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3299 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3300 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3303 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3304 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3306 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3307 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3308 map
->w
, map
->h
, 1));
3309 map
->ptr
= map
->buffer
;
3313 intel_miptree_unmap_etc(struct brw_context
*brw
,
3314 struct intel_mipmap_tree
*mt
,
3315 struct intel_miptree_map
*map
,
3321 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3326 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3327 + image_y
* mt
->surf
.row_pitch
3328 + image_x
* mt
->cpp
;
3330 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3331 _mesa_etc1_unpack_rgba8888(dst
, mt
->surf
.row_pitch
,
3332 map
->ptr
, map
->stride
,
3335 _mesa_unpack_etc2_format(dst
, mt
->surf
.row_pitch
,
3336 map
->ptr
, map
->stride
,
3337 map
->w
, map
->h
, mt
->etc_format
);
3339 intel_miptree_unmap_raw(mt
);
3344 * Mapping function for packed depth/stencil miptrees backed by real separate
3345 * miptrees for depth and stencil.
3347 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3348 * separate from the depth buffer. Yet at the GL API level, we have to expose
3349 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3350 * be able to map that memory for texture storage and glReadPixels-type
3351 * operations. We give Mesa core that access by mallocing a temporary and
3352 * copying the data between the actual backing store and the temporary.
3355 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3356 struct intel_mipmap_tree
*mt
,
3357 struct intel_miptree_map
*map
,
3358 unsigned int level
, unsigned int slice
)
3360 struct intel_mipmap_tree
*z_mt
= mt
;
3361 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3362 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3363 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3365 map
->stride
= map
->w
* packed_bpp
;
3366 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3370 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3371 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3372 * invalidate is set, since we'll be writing the whole rectangle from our
3373 * temporary buffer back out.
3375 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3376 uint32_t *packed_map
= map
->ptr
;
3377 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3378 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3379 unsigned int s_image_x
, s_image_y
;
3380 unsigned int z_image_x
, z_image_y
;
3382 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3383 &s_image_x
, &s_image_y
);
3384 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3385 &z_image_x
, &z_image_y
);
3387 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3388 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3389 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3390 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3393 brw
->has_swizzling
);
3394 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3395 (z_mt
->surf
.row_pitch
/ 4) +
3396 (map_x
+ z_image_x
));
3397 uint8_t s
= s_map
[s_offset
];
3398 uint32_t z
= z_map
[z_offset
];
3400 if (map_z32f_x24s8
) {
3401 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3402 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3404 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3409 intel_miptree_unmap_raw(s_mt
);
3410 intel_miptree_unmap_raw(z_mt
);
3412 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3414 map
->x
, map
->y
, map
->w
, map
->h
,
3415 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3416 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3417 map
->ptr
, map
->stride
);
3419 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3420 map
->x
, map
->y
, map
->w
, map
->h
,
3421 mt
, map
->ptr
, map
->stride
);
3426 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3427 struct intel_mipmap_tree
*mt
,
3428 struct intel_miptree_map
*map
,
3432 struct intel_mipmap_tree
*z_mt
= mt
;
3433 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3434 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3436 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3437 uint32_t *packed_map
= map
->ptr
;
3438 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3439 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3440 unsigned int s_image_x
, s_image_y
;
3441 unsigned int z_image_x
, z_image_y
;
3443 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3444 &s_image_x
, &s_image_y
);
3445 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3446 &z_image_x
, &z_image_y
);
3448 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3449 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3450 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->surf
.row_pitch
,
3451 x
+ s_image_x
+ map
->x
,
3452 y
+ s_image_y
+ map
->y
,
3453 brw
->has_swizzling
);
3454 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3455 (z_mt
->surf
.row_pitch
/ 4) +
3456 (x
+ z_image_x
+ map
->x
));
3458 if (map_z32f_x24s8
) {
3459 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3460 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3462 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3463 s_map
[s_offset
] = packed
>> 24;
3464 z_map
[z_offset
] = packed
;
3469 intel_miptree_unmap_raw(s_mt
);
3470 intel_miptree_unmap_raw(z_mt
);
3472 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3474 map
->x
, map
->y
, map
->w
, map
->h
,
3475 z_mt
, _mesa_get_format_name(z_mt
->format
),
3476 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3477 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3478 map
->ptr
, map
->stride
);
3485 * Create and attach a map to the miptree at (level, slice). Return the
3488 static struct intel_miptree_map
*
3489 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3498 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3503 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3504 mt
->level
[level
].slice
[slice
].map
= map
;
3516 * Release the map at (level, slice).
3519 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3523 struct intel_miptree_map
**map
;
3525 map
= &mt
->level
[level
].slice
[slice
].map
;
3531 can_blit_slice(struct intel_mipmap_tree
*mt
,
3532 unsigned int level
, unsigned int slice
)
3534 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3535 if (mt
->surf
.row_pitch
>= 32768)
3542 use_intel_mipree_map_blit(struct brw_context
*brw
,
3543 struct intel_mipmap_tree
*mt
,
3549 /* It's probably not worth swapping to the blit ring because of
3550 * all the overhead involved.
3552 !(mode
& GL_MAP_WRITE_BIT
) &&
3554 (mt
->surf
.tiling
== ISL_TILING_X
||
3555 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3556 (brw
->gen
>= 6 && mt
->surf
.tiling
== ISL_TILING_Y0
) ||
3557 /* Fast copy blit on skl+ supports all tiling formats. */
3559 can_blit_slice(mt
, level
, slice
))
3562 if (mt
->surf
.tiling
!= ISL_TILING_LINEAR
&&
3563 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3564 assert(can_blit_slice(mt
, level
, slice
));
3572 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3573 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3574 * arithmetic overflow.
3576 * If you call this function and use \a out_stride, then you're doing pointer
3577 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3578 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3579 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3580 * which usually have type uint32_t or GLuint.
3583 intel_miptree_map(struct brw_context
*brw
,
3584 struct intel_mipmap_tree
*mt
,
3593 ptrdiff_t *out_stride
)
3595 struct intel_miptree_map
*map
;
3597 assert(mt
->surf
.samples
== 1);
3599 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3606 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3607 map
->mode
& GL_MAP_WRITE_BIT
);
3609 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3610 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3611 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3612 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3613 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3614 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3615 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3616 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3617 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3618 #if defined(USE_SSE41)
3619 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3620 !mt
->compressed
&& cpu_has_sse4_1
&&
3621 (mt
->surf
.row_pitch
% 16 == 0)) {
3622 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3625 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3628 *out_ptr
= map
->ptr
;
3629 *out_stride
= map
->stride
;
3631 if (map
->ptr
== NULL
)
3632 intel_miptree_release_map(mt
, level
, slice
);
3636 intel_miptree_unmap(struct brw_context
*brw
,
3637 struct intel_mipmap_tree
*mt
,
3641 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3643 assert(mt
->surf
.samples
== 1);
3648 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3649 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3651 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3652 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3653 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3654 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3655 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3656 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3657 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3658 } else if (map
->linear_mt
) {
3659 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3660 #if defined(USE_SSE41)
3661 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3662 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3665 intel_miptree_unmap_gtt(mt
);
3668 intel_miptree_release_map(mt
, level
, slice
);
3672 get_isl_surf_dim(GLenum target
)
3676 case GL_TEXTURE_1D_ARRAY
:
3677 return ISL_SURF_DIM_1D
;
3680 case GL_TEXTURE_2D_ARRAY
:
3681 case GL_TEXTURE_RECTANGLE
:
3682 case GL_TEXTURE_CUBE_MAP
:
3683 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3684 case GL_TEXTURE_2D_MULTISAMPLE
:
3685 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3686 case GL_TEXTURE_EXTERNAL_OES
:
3687 return ISL_SURF_DIM_2D
;
3690 return ISL_SURF_DIM_3D
;
3693 unreachable("Invalid texture target");
3697 get_isl_dim_layout(const struct gen_device_info
*devinfo
,
3698 enum isl_tiling tiling
, GLenum target
)
3702 case GL_TEXTURE_1D_ARRAY
:
3703 return (devinfo
->gen
>= 9 && tiling
== ISL_TILING_LINEAR
?
3704 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3707 case GL_TEXTURE_2D_ARRAY
:
3708 case GL_TEXTURE_RECTANGLE
:
3709 case GL_TEXTURE_2D_MULTISAMPLE
:
3710 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3711 case GL_TEXTURE_EXTERNAL_OES
:
3712 return ISL_DIM_LAYOUT_GEN4_2D
;
3714 case GL_TEXTURE_CUBE_MAP
:
3715 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3716 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3717 ISL_DIM_LAYOUT_GEN4_2D
);
3720 return (devinfo
->gen
>= 9 ?
3721 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3724 unreachable("Invalid texture target");
3728 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3729 const struct intel_mipmap_tree
*mt
)
3732 return ISL_AUX_USAGE_HIZ
;
3735 return ISL_AUX_USAGE_NONE
;
3737 return mt
->aux_usage
;