1 /**************************************************************************
3 * Copyright 2006 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include <GL/internal/dri_interface.h>
31 #include "intel_batchbuffer.h"
32 #include "intel_mipmap_tree.h"
33 #include "intel_resolve_map.h"
34 #include "intel_tex.h"
35 #include "intel_blit.h"
36 #include "intel_fbo.h"
38 #include "brw_blorp.h"
39 #include "brw_context.h"
41 #include "main/enums.h"
42 #include "main/fbobject.h"
43 #include "main/formats.h"
44 #include "main/glformats.h"
45 #include "main/texcompress_etc.h"
46 #include "main/teximage.h"
47 #include "main/streaming-load-memcpy.h"
48 #include "x86/common_x86_asm.h"
50 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
53 intel_miptree_alloc_mcs(struct brw_context
*brw
,
54 struct intel_mipmap_tree
*mt
,
58 * Determine which MSAA layout should be used by the MSAA surface being
59 * created, based on the chip generation and the surface type.
61 static enum intel_msaa_layout
62 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
, GLenum target
,
63 bool disable_aux_buffers
)
65 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
67 return INTEL_MSAA_LAYOUT_IMS
;
69 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
70 switch (_mesa_get_format_base_format(format
)) {
71 case GL_DEPTH_COMPONENT
:
72 case GL_STENCIL_INDEX
:
73 case GL_DEPTH_STENCIL
:
74 return INTEL_MSAA_LAYOUT_IMS
;
76 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
78 * This field must be set to 0 for all SINT MSRTs when all RT channels
81 * In practice this means that we have to disable MCS for all signed
82 * integer MSAA buffers. The alternative, to disable MCS only when one
83 * of the render target channels is disabled, is impractical because it
84 * would require converting between CMS and UMS MSAA layouts on the fly,
87 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
88 return INTEL_MSAA_LAYOUT_UMS
;
89 } else if (disable_aux_buffers
) {
90 /* We can't use the CMS layout because it uses an aux buffer, the MCS
91 * buffer. So fallback to UMS, which is identical to CMS without the
93 return INTEL_MSAA_LAYOUT_UMS
;
95 return INTEL_MSAA_LAYOUT_CMS
;
102 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
103 * scaled-down bitfield representation of the color buffer which is capable of
104 * recording when blocks of the color buffer are equal to the clear value.
105 * This function returns the block size that will be used by the MCS buffer
106 * corresponding to a certain color miptree.
108 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
109 * beneath the "Fast Color Clear" bullet (p327):
111 * The following table describes the RT alignment
125 * This alignment has the following uses:
127 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
128 * buffer contains 128 blocks horizontally and 256 blocks vertically.
130 * - For figuring out alignment restrictions for a fast clear operation. Fast
131 * clear operations must always clear aligned multiples of 16 blocks
132 * horizontally and 32 blocks vertically.
134 * - For scaling down the coordinates sent through the render pipeline during
135 * a fast clear. X coordinates must be scaled down by 8 times the block
136 * width, and Y coordinates by 16 times the block height.
138 * - For scaling down the coordinates sent through the render pipeline during
139 * a "Render Target Resolve" operation. X coordinates must be scaled down
140 * by half the block width, and Y coordinates by half the block height.
143 intel_get_non_msrt_mcs_alignment(struct brw_context
*brw
,
144 struct intel_mipmap_tree
*mt
,
145 unsigned *width_px
, unsigned *height
)
147 switch (mt
->tiling
) {
149 unreachable("Non-MSRT MCS requires X or Y tiling");
150 /* In release builds, fall through */
152 *width_px
= 32 / mt
->cpp
;
156 *width_px
= 64 / mt
->cpp
;
162 intel_tiling_supports_non_msrt_mcs(struct brw_context
*brw
, unsigned tiling
)
164 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
165 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
167 * - Support is limited to tiled render targets.
169 * Gen9 changes the restriction to Y-tile only.
172 return tiling
== I915_TILING_Y
;
173 else if (brw
->gen
>= 7)
174 return tiling
!= I915_TILING_NONE
;
180 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
181 * can be used. This doesn't (and should not) inspect any of the properties of
184 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
185 * beneath the "Fast Color Clear" bullet (p326):
187 * - Support is for non-mip-mapped and non-array surface types only.
189 * And then later, on p327:
191 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
195 intel_miptree_is_fast_clear_capable(struct brw_context
*brw
,
196 struct intel_mipmap_tree
*mt
)
198 /* MCS support does not exist prior to Gen7 */
202 if (mt
->disable_aux_buffers
)
205 /* MCS is only supported for color buffers */
206 switch (_mesa_get_format_base_format(mt
->format
)) {
207 case GL_DEPTH_COMPONENT
:
208 case GL_DEPTH_STENCIL
:
209 case GL_STENCIL_INDEX
:
213 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
215 if (mt
->first_level
!= 0 || mt
->last_level
!= 0) {
217 perf_debug("Multi-LOD fast clear - giving up (%dx%dx%d).\n",
218 mt
->logical_width0
, mt
->logical_height0
, mt
->last_level
);
223 if (mt
->physical_depth0
!= 1) {
225 perf_debug("Layered fast clear - giving up. (%dx%d%d)\n",
226 mt
->logical_width0
, mt
->logical_height0
,
227 mt
->physical_depth0
);
233 /* There's no point in using an MCS buffer if the surface isn't in a
236 if (!brw
->format_supported_as_render_target
[mt
->format
])
244 * Determine depth format corresponding to a depth+stencil format,
245 * for separate stencil.
248 intel_depth_format_for_depthstencil_format(mesa_format format
) {
250 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
251 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
252 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
253 return MESA_FORMAT_Z_FLOAT32
;
261 * @param for_bo Indicates that the caller is
262 * intel_miptree_create_for_bo(). If true, then do not create
265 static struct intel_mipmap_tree
*
266 intel_miptree_create_layout(struct brw_context
*brw
,
275 enum intel_miptree_tiling_mode requested
,
276 uint32_t layout_flags
)
278 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
282 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
283 _mesa_lookup_enum_by_nr(target
),
284 _mesa_get_format_name(format
),
285 first_level
, last_level
, depth0
, mt
);
287 if (target
== GL_TEXTURE_1D_ARRAY
) {
288 /* For a 1D Array texture the OpenGL API will treat the height0
289 * parameter as the number of array slices. For Intel hardware, we treat
290 * the 1D array as a 2D Array with a height of 1.
292 * So, when we first come through this path to create a 1D Array
293 * texture, height0 stores the number of slices, and depth0 is 1. In
294 * this case, we want to swap height0 and depth0.
296 * Since some miptrees will be created based on the base miptree, we may
297 * come through this path and see height0 as 1 and depth0 being the
298 * number of slices. In this case we don't need to do the swap.
300 assert(height0
== 1 || depth0
== 1);
309 mt
->first_level
= first_level
;
310 mt
->last_level
= last_level
;
311 mt
->logical_width0
= width0
;
312 mt
->logical_height0
= height0
;
313 mt
->logical_depth0
= depth0
;
314 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
315 mt
->disable_aux_buffers
= (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) != 0;
316 exec_list_make_empty(&mt
->hiz_map
);
318 /* The cpp is bytes per (1, blockheight)-sized block for compressed
319 * textures. This is why you'll see divides by blockheight all over
322 _mesa_get_format_block_size(format
, &bw
, &bh
);
323 assert(_mesa_get_format_bytes(mt
->format
) % bw
== 0);
324 mt
->cpp
= _mesa_get_format_bytes(mt
->format
) / bw
;
326 mt
->num_samples
= num_samples
;
327 mt
->compressed
= _mesa_is_format_compressed(format
);
328 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
331 if (num_samples
> 1) {
332 /* Adjust width/height/depth for MSAA */
333 mt
->msaa_layout
= compute_msaa_layout(brw
, format
,
334 mt
->target
, mt
->disable_aux_buffers
);
335 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
336 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
337 * "If the surface is multisampled and it is a depth or stencil
338 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
339 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
342 * +----------------------------------------------------------------+
343 * | Num Multisamples | W_l = | H_l = |
344 * +----------------------------------------------------------------+
345 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
346 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
347 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
348 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
349 * +----------------------------------------------------------------+
352 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
353 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
354 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
356 * Another more complicated explanation for these adjustments comes
357 * from the Sandybridge PRM, volume 4, part 1, page 31:
359 * "Any of the other messages (sample*, LOD, load4) used with a
360 * (4x) multisampled surface will in-effect sample a surface with
361 * double the height and width as that indicated in the surface
362 * state. Each pixel position on the original-sized surface is
363 * replaced with a 2x2 of samples with the following arrangement:
368 * Thus, when sampling from a multisampled texture, it behaves as
369 * though the layout in memory for (x,y,sample) is:
371 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
372 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
374 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
375 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
377 * However, the actual layout of multisampled data in memory is:
379 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
380 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
382 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
383 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
385 * This pattern repeats for each 2x2 pixel block.
387 * As a result, when calculating the size of our 4-sample buffer for
388 * an odd width or height, we have to align before scaling up because
389 * sample 3 is in that bottom right 2x2 block.
391 switch (num_samples
) {
393 assert(brw
->gen
>= 8);
394 width0
= ALIGN(width0
, 2) * 2;
395 height0
= ALIGN(height0
, 2);
398 width0
= ALIGN(width0
, 2) * 2;
399 height0
= ALIGN(height0
, 2) * 2;
402 width0
= ALIGN(width0
, 2) * 4;
403 height0
= ALIGN(height0
, 2) * 2;
406 /* num_samples should already have been quantized to 0, 1, 2, 4, or
409 unreachable("not reached");
412 /* Non-interleaved */
413 depth0
*= num_samples
;
417 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
418 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
419 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
420 * used on Gen8 to make it pick a qpitch value which doesn't include space
421 * for the mipmaps. On Gen9 this is not necessary because it will
422 * automatically pick a packed qpitch value whenever mt->first_level ==
424 * TODO: can we use it elsewhere?
425 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
428 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
430 switch (mt
->msaa_layout
) {
431 case INTEL_MSAA_LAYOUT_NONE
:
432 case INTEL_MSAA_LAYOUT_IMS
:
433 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
435 case INTEL_MSAA_LAYOUT_UMS
:
436 case INTEL_MSAA_LAYOUT_CMS
:
437 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
442 if (target
== GL_TEXTURE_CUBE_MAP
) {
447 mt
->physical_width0
= width0
;
448 mt
->physical_height0
= height0
;
449 mt
->physical_depth0
= depth0
;
451 if (!(layout_flags
& MIPTREE_LAYOUT_FOR_BO
) &&
452 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
453 (brw
->must_use_separate_stencil
||
454 (brw
->has_separate_stencil
&&
455 intel_miptree_wants_hiz_buffer(brw
, mt
)))) {
456 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
458 stencil_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
;
460 mt
->stencil_mt
= intel_miptree_create(brw
,
469 INTEL_MIPTREE_TILING_ANY
,
472 if (!mt
->stencil_mt
) {
473 intel_miptree_release(&mt
);
477 /* Fix up the Z miptree format for how we're splitting out separate
478 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
480 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
483 if (format
== mt
->format
) {
484 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
485 _mesa_get_format_name(mt
->format
));
489 if (layout_flags
& MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
)
490 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
493 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
494 * multisampled or have an AUX buffer attached to it.
496 * GEN | MSRT | AUX_CCS_* or AUX_MCS
497 * -------------------------------------------
498 * 9 | HALIGN_16 | HALIGN_16
499 * 8 | HALIGN_ANY | HALIGN_16
503 if (intel_miptree_is_fast_clear_capable(brw
, mt
)) {
504 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
<= 1))
505 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
506 } else if (brw
->gen
>= 9 && num_samples
> 1) {
507 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
509 /* For now, nothing else has this requirement */
510 assert((layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
513 brw_miptree_layout(brw
, mt
, requested
, layout_flags
);
515 if (mt
->disable_aux_buffers
)
516 assert(mt
->msaa_layout
!= INTEL_MSAA_LAYOUT_CMS
);
523 * Choose an appropriate uncompressed format for a requested
524 * compressed format, if unsupported.
527 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
529 /* No need to lower ETC formats on these platforms,
530 * they are supported natively.
532 if (brw
->gen
>= 8 || brw
->is_baytrail
)
536 case MESA_FORMAT_ETC1_RGB8
:
537 return MESA_FORMAT_R8G8B8X8_UNORM
;
538 case MESA_FORMAT_ETC2_RGB8
:
539 return MESA_FORMAT_R8G8B8X8_UNORM
;
540 case MESA_FORMAT_ETC2_SRGB8
:
541 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
542 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
543 return MESA_FORMAT_B8G8R8A8_SRGB
;
544 case MESA_FORMAT_ETC2_RGBA8_EAC
:
545 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
546 return MESA_FORMAT_R8G8B8A8_UNORM
;
547 case MESA_FORMAT_ETC2_R11_EAC
:
548 return MESA_FORMAT_R_UNORM16
;
549 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
550 return MESA_FORMAT_R_SNORM16
;
551 case MESA_FORMAT_ETC2_RG11_EAC
:
552 return MESA_FORMAT_R16G16_UNORM
;
553 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
554 return MESA_FORMAT_R16G16_SNORM
;
556 /* Non ETC1 / ETC2 format */
562 struct intel_mipmap_tree
*
563 intel_miptree_create(struct brw_context
*brw
,
572 enum intel_miptree_tiling_mode requested_tiling
,
573 uint32_t layout_flags
)
575 struct intel_mipmap_tree
*mt
;
576 mesa_format tex_format
= format
;
577 mesa_format etc_format
= MESA_FORMAT_NONE
;
578 GLuint total_width
, total_height
;
579 uint32_t alloc_flags
= 0;
581 format
= intel_lower_compressed_format(brw
, format
);
583 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
585 assert((layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) == 0);
586 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
587 mt
= intel_miptree_create_layout(brw
, target
, format
,
588 first_level
, last_level
, width0
,
589 height0
, depth0
, num_samples
,
590 requested_tiling
, layout_flags
);
592 * pitch == 0 || height == 0 indicates the null texture
594 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
595 intel_miptree_release(&mt
);
599 total_width
= mt
->total_width
;
600 total_height
= mt
->total_height
;
602 if (format
== MESA_FORMAT_S_UINT8
) {
603 /* Align to size of W tile, 64x64. */
604 total_width
= ALIGN(total_width
, 64);
605 total_height
= ALIGN(total_height
, 64);
610 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
)) {
612 mt
->tiling
= I915_TILING_Y
;
615 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
616 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
619 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree", total_width
,
620 total_height
, mt
->cpp
, &mt
->tiling
,
621 &pitch
, alloc_flags
);
622 mt
->etc_format
= etc_format
;
625 /* If the BO is too large to fit in the aperture, we need to use the
626 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
627 * handle Y-tiling, so we need to fall back to X.
629 if (brw
->gen
< 6 && y_or_x
&& mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
630 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
631 mt
->total_width
, mt
->total_height
);
633 mt
->tiling
= I915_TILING_X
;
634 drm_intel_bo_unreference(mt
->bo
);
635 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
636 total_width
, total_height
, mt
->cpp
,
637 &mt
->tiling
, &pitch
, alloc_flags
);
644 intel_miptree_release(&mt
);
649 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
650 assert(mt
->num_samples
> 1);
651 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
652 intel_miptree_release(&mt
);
657 /* If this miptree is capable of supporting fast color clears, set
658 * fast_clear_state appropriately to ensure that fast clears will occur.
659 * Allocation of the MCS miptree will be deferred until the first fast
660 * clear actually occurs.
662 if (intel_tiling_supports_non_msrt_mcs(brw
, mt
->tiling
) &&
663 intel_miptree_is_fast_clear_capable(brw
, mt
)) {
664 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
665 assert(brw
->gen
< 8 || mt
->align_w
== 16 || num_samples
<= 1);
671 struct intel_mipmap_tree
*
672 intel_miptree_create_for_bo(struct brw_context
*brw
,
680 uint32_t layout_flags
)
682 struct intel_mipmap_tree
*mt
;
683 uint32_t tiling
, swizzle
;
686 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
688 /* Nothing will be able to use this miptree with the BO if the offset isn't
691 if (tiling
!= I915_TILING_NONE
)
692 assert(offset
% 4096 == 0);
694 /* miptrees can't handle negative pitch. If you need flipping of images,
695 * that's outside of the scope of the mt.
699 target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
701 /* 'requested' parameter of intel_miptree_create_layout() is relevant
702 * only for non bo miptree. Tiling for bo is already computed above.
703 * So, the tiling requested (INTEL_MIPTREE_TILING_ANY) below is
704 * just a place holder and will not make any change to the miptree
707 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
708 mt
= intel_miptree_create_layout(brw
, target
, format
,
710 width
, height
, depth
, 0,
711 INTEL_MIPTREE_TILING_ANY
,
716 drm_intel_bo_reference(bo
);
726 * For a singlesample renderbuffer, this simply wraps the given BO with a
729 * For a multisample renderbuffer, this wraps the window system's
730 * (singlesample) BO with a singlesample miptree attached to the
731 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
732 * that will contain the actual rendering (which is lazily resolved to
733 * irb->singlesample_mt).
736 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
737 struct intel_renderbuffer
*irb
,
739 uint32_t width
, uint32_t height
,
742 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
743 struct intel_mipmap_tree
*multisample_mt
= NULL
;
744 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
745 mesa_format format
= rb
->Format
;
746 int num_samples
= rb
->NumSamples
;
748 /* Only the front and back buffers, which are color buffers, are allocated
749 * through the image loader.
751 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
752 _mesa_get_format_base_format(format
) == GL_RGBA
);
754 singlesample_mt
= intel_miptree_create_for_bo(intel
,
763 if (!singlesample_mt
)
766 /* If this miptree is capable of supporting fast color clears, set
767 * mcs_state appropriately to ensure that fast clears will occur.
768 * Allocation of the MCS miptree will be deferred until the first fast
769 * clear actually occurs.
771 if (intel_tiling_supports_non_msrt_mcs(intel
, singlesample_mt
->tiling
) &&
772 intel_miptree_is_fast_clear_capable(intel
, singlesample_mt
))
773 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
775 if (num_samples
== 0) {
776 intel_miptree_release(&irb
->mt
);
777 irb
->mt
= singlesample_mt
;
779 assert(!irb
->singlesample_mt
);
781 intel_miptree_release(&irb
->singlesample_mt
);
782 irb
->singlesample_mt
= singlesample_mt
;
785 irb
->mt
->logical_width0
!= width
||
786 irb
->mt
->logical_height0
!= height
) {
787 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
795 irb
->need_downsample
= false;
796 intel_miptree_release(&irb
->mt
);
797 irb
->mt
= multisample_mt
;
803 intel_miptree_release(&irb
->singlesample_mt
);
804 intel_miptree_release(&irb
->mt
);
808 struct intel_mipmap_tree
*
809 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
813 uint32_t num_samples
)
815 struct intel_mipmap_tree
*mt
;
818 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
820 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
821 width
, height
, depth
, num_samples
,
822 INTEL_MIPTREE_TILING_ANY
,
823 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
);
827 if (intel_miptree_wants_hiz_buffer(brw
, mt
)) {
828 ok
= intel_miptree_alloc_hiz(brw
, mt
);
836 intel_miptree_release(&mt
);
841 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
842 struct intel_mipmap_tree
*src
)
847 intel_miptree_release(dst
);
851 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
859 intel_miptree_release(struct intel_mipmap_tree
**mt
)
864 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
865 if (--(*mt
)->refcount
<= 0) {
868 DBG("%s deleting %p\n", __func__
, *mt
);
870 drm_intel_bo_unreference((*mt
)->bo
);
871 intel_miptree_release(&(*mt
)->stencil_mt
);
872 if ((*mt
)->hiz_buf
) {
873 if ((*mt
)->hiz_buf
->mt
)
874 intel_miptree_release(&(*mt
)->hiz_buf
->mt
);
876 drm_intel_bo_unreference((*mt
)->hiz_buf
->bo
);
877 free((*mt
)->hiz_buf
);
879 intel_miptree_release(&(*mt
)->mcs_mt
);
880 intel_resolve_map_clear(&(*mt
)->hiz_map
);
882 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
883 free((*mt
)->level
[i
].slice
);
892 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
893 int *width
, int *height
, int *depth
)
895 switch (image
->TexObject
->Target
) {
896 case GL_TEXTURE_1D_ARRAY
:
897 *width
= image
->Width
;
899 *depth
= image
->Height
;
902 *width
= image
->Width
;
903 *height
= image
->Height
;
904 *depth
= image
->Depth
;
910 * Can the image be pulled into a unified mipmap tree? This mirrors
911 * the completeness test in a lot of ways.
913 * Not sure whether I want to pass gl_texture_image here.
916 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
917 struct gl_texture_image
*image
)
919 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
920 GLuint level
= intelImage
->base
.Base
.Level
;
921 int width
, height
, depth
;
923 /* glTexImage* choose the texture object based on the target passed in, and
924 * objects can't change targets over their lifetimes, so this should be
927 assert(image
->TexObject
->Target
== mt
->target
);
929 mesa_format mt_format
= mt
->format
;
930 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
931 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
932 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
933 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
934 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
935 mt_format
= mt
->etc_format
;
937 if (image
->TexFormat
!= mt_format
)
940 intel_miptree_get_dimensions_for_image(image
, &width
, &height
, &depth
);
942 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
945 int level_depth
= mt
->level
[level
].depth
;
946 if (mt
->num_samples
> 1) {
947 switch (mt
->msaa_layout
) {
948 case INTEL_MSAA_LAYOUT_NONE
:
949 case INTEL_MSAA_LAYOUT_IMS
:
951 case INTEL_MSAA_LAYOUT_UMS
:
952 case INTEL_MSAA_LAYOUT_CMS
:
953 level_depth
/= mt
->num_samples
;
958 /* Test image dimensions against the base level image adjusted for
959 * minification. This will also catch images not present in the
960 * tree, changed targets, etc.
962 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
963 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
964 depth
!= level_depth
) {
968 if (image
->NumSamples
!= mt
->num_samples
)
976 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
978 GLuint x
, GLuint y
, GLuint d
)
980 mt
->level
[level
].depth
= d
;
981 mt
->level
[level
].level_x
= x
;
982 mt
->level
[level
].level_y
= y
;
984 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
987 assert(mt
->level
[level
].slice
== NULL
);
989 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
990 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
991 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
996 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
997 GLuint level
, GLuint img
,
1000 if (img
== 0 && level
== 0)
1001 assert(x
== 0 && y
== 0);
1003 assert(img
< mt
->level
[level
].depth
);
1005 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1006 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1008 DBG("%s level %d img %d pos %d,%d\n",
1009 __func__
, level
, img
,
1010 mt
->level
[level
].slice
[img
].x_offset
,
1011 mt
->level
[level
].slice
[img
].y_offset
);
1015 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1016 GLuint level
, GLuint slice
,
1017 GLuint
*x
, GLuint
*y
)
1019 assert(slice
< mt
->level
[level
].depth
);
1021 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1022 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1026 * This function computes masks that may be used to select the bits of the X
1027 * and Y coordinates that indicate the offset within a tile. If the BO is
1028 * untiled, the masks are set to 0.
1031 intel_miptree_get_tile_masks(const struct intel_mipmap_tree
*mt
,
1032 uint32_t *mask_x
, uint32_t *mask_y
,
1033 bool map_stencil_as_y_tiled
)
1036 uint32_t tiling
= mt
->tiling
;
1038 if (map_stencil_as_y_tiled
)
1039 tiling
= I915_TILING_Y
;
1043 unreachable("not reached");
1044 case I915_TILING_NONE
:
1045 *mask_x
= *mask_y
= 0;
1048 *mask_x
= 512 / cpp
- 1;
1052 *mask_x
= 128 / cpp
- 1;
1059 * Compute the offset (in bytes) from the start of the BO to the given x
1060 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1061 * multiples of the tile size.
1064 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1065 uint32_t x
, uint32_t y
,
1066 bool map_stencil_as_y_tiled
)
1069 uint32_t pitch
= mt
->pitch
;
1070 uint32_t tiling
= mt
->tiling
;
1072 if (map_stencil_as_y_tiled
) {
1073 tiling
= I915_TILING_Y
;
1075 /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
1076 * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
1077 * the resulting surface is twice the pitch of the original miptree,
1078 * since each row in the Y-tiled view corresponds to two rows in the
1079 * actual W-tiled surface. So we need to correct the pitch before
1080 * computing the offsets.
1087 unreachable("not reached");
1088 case I915_TILING_NONE
:
1089 return y
* pitch
+ x
* cpp
;
1091 assert((x
% (512 / cpp
)) == 0);
1092 assert((y
% 8) == 0);
1093 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1095 assert((x
% (128 / cpp
)) == 0);
1096 assert((y
% 32) == 0);
1097 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1102 * Rendering with tiled buffers requires that the base address of the buffer
1103 * be aligned to a page boundary. For renderbuffers, and sometimes with
1104 * textures, we may want the surface to point at a texture image level that
1105 * isn't at a page boundary.
1107 * This function returns an appropriately-aligned base offset
1108 * according to the tiling restrictions, plus any required x/y offset
1112 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1113 GLuint level
, GLuint slice
,
1118 uint32_t mask_x
, mask_y
;
1120 intel_miptree_get_tile_masks(mt
, &mask_x
, &mask_y
, false);
1121 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1123 *tile_x
= x
& mask_x
;
1124 *tile_y
= y
& mask_y
;
1126 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
, false);
1130 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1131 struct intel_mipmap_tree
*dst_mt
,
1132 struct intel_mipmap_tree
*src_mt
,
1139 ptrdiff_t src_stride
, dst_stride
;
1140 int cpp
= dst_mt
->cpp
;
1142 intel_miptree_map(brw
, src_mt
,
1146 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1149 intel_miptree_map(brw
, dst_mt
,
1153 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1157 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1158 _mesa_get_format_name(src_mt
->format
),
1159 src_mt
, src
, src_stride
,
1160 _mesa_get_format_name(dst_mt
->format
),
1161 dst_mt
, dst
, dst_stride
,
1164 int row_size
= cpp
* width
;
1165 if (src_stride
== row_size
&&
1166 dst_stride
== row_size
) {
1167 memcpy(dst
, src
, row_size
* height
);
1169 for (int i
= 0; i
< height
; i
++) {
1170 memcpy(dst
, src
, row_size
);
1176 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1177 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1179 /* Don't forget to copy the stencil data over, too. We could have skipped
1180 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1181 * shuffling the two data sources in/out of temporary storage instead of
1182 * the direct mapping we get this way.
1184 if (dst_mt
->stencil_mt
) {
1185 assert(src_mt
->stencil_mt
);
1186 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1187 level
, slice
, width
, height
);
1192 intel_miptree_copy_slice(struct brw_context
*brw
,
1193 struct intel_mipmap_tree
*dst_mt
,
1194 struct intel_mipmap_tree
*src_mt
,
1200 mesa_format format
= src_mt
->format
;
1201 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1202 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1210 assert(depth
< src_mt
->level
[level
].depth
);
1211 assert(src_mt
->format
== dst_mt
->format
);
1213 if (dst_mt
->compressed
) {
1215 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1216 height
= ALIGN(height
, j
) / j
;
1217 width
= ALIGN(width
, i
);
1220 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1221 * below won't apply since we can't do the depth's Y tiling or the
1222 * stencil's W tiling in the blitter.
1224 if (src_mt
->stencil_mt
) {
1225 intel_miptree_copy_slice_sw(brw
,
1232 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1233 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1234 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1236 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1237 _mesa_get_format_name(src_mt
->format
),
1238 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1239 _mesa_get_format_name(dst_mt
->format
),
1240 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1243 if (!intel_miptree_blit(brw
,
1244 src_mt
, level
, slice
, 0, 0, false,
1245 dst_mt
, level
, slice
, 0, 0, false,
1246 width
, height
, GL_COPY
)) {
1247 perf_debug("miptree validate blit for %s failed\n",
1248 _mesa_get_format_name(format
));
1250 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1256 * Copies the image's current data to the given miptree, and associates that
1257 * miptree with the image.
1259 * If \c invalidate is true, then the actual image data does not need to be
1260 * copied, but the image still needs to be associated to the new miptree (this
1261 * is set to true if we're about to clear the image).
1264 intel_miptree_copy_teximage(struct brw_context
*brw
,
1265 struct intel_texture_image
*intelImage
,
1266 struct intel_mipmap_tree
*dst_mt
,
1269 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1270 struct intel_texture_object
*intel_obj
=
1271 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1272 int level
= intelImage
->base
.Base
.Level
;
1273 int face
= intelImage
->base
.Base
.Face
;
1276 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
)
1277 depth
= intelImage
->base
.Base
.Height
;
1279 depth
= intelImage
->base
.Base
.Depth
;
1282 for (int slice
= 0; slice
< depth
; slice
++) {
1283 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1287 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1288 intel_obj
->needs_validate
= true;
1292 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1293 struct intel_mipmap_tree
*mt
,
1296 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1297 assert(mt
->mcs_mt
== NULL
);
1298 assert(!mt
->disable_aux_buffers
);
1300 /* Choose the correct format for the MCS buffer. All that really matters
1301 * is that we allocate the right buffer size, since we'll always be
1302 * accessing this miptree using MCS-specific hardware mechanisms, which
1303 * infer the correct format based on num_samples.
1306 switch (num_samples
) {
1309 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1312 format
= MESA_FORMAT_R_UNORM8
;
1315 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1316 * for each sample, plus 8 padding bits).
1318 format
= MESA_FORMAT_R_UINT32
;
1321 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1324 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1326 * "The MCS surface must be stored as Tile Y."
1328 mt
->mcs_mt
= intel_miptree_create(brw
,
1334 mt
->logical_height0
,
1336 0 /* num_samples */,
1337 INTEL_MIPTREE_TILING_Y
,
1338 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
);
1340 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1342 * When MCS buffer is enabled and bound to MSRT, it is required that it
1343 * is cleared prior to any rendering.
1345 * Since we don't use the MCS buffer for any purpose other than rendering,
1346 * it makes sense to just clear it immediately upon allocation.
1348 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1350 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1351 memset(data
, 0xff, mt
->mcs_mt
->total_height
* mt
->mcs_mt
->pitch
);
1352 intel_miptree_unmap_raw(brw
, mt
->mcs_mt
);
1353 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1360 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1361 struct intel_mipmap_tree
*mt
)
1363 assert(mt
->mcs_mt
== NULL
);
1364 assert(!mt
->disable_aux_buffers
);
1366 /* The format of the MCS buffer is opaque to the driver; all that matters
1367 * is that we get its size and pitch right. We'll pretend that the format
1368 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1369 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1370 * the block width and then a further factor of 4. Since an MCS tile
1371 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1372 * we'll need to scale the height down by the block height and then a
1373 * further factor of 8.
1375 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1376 unsigned block_width_px
;
1377 unsigned block_height
;
1378 intel_get_non_msrt_mcs_alignment(brw
, mt
, &block_width_px
, &block_height
);
1379 unsigned width_divisor
= block_width_px
* 4;
1380 unsigned height_divisor
= block_height
* 8;
1381 unsigned mcs_width
=
1382 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1383 unsigned mcs_height
=
1384 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1385 assert(mt
->logical_depth0
== 1);
1386 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1388 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
1389 mt
->mcs_mt
= intel_miptree_create(brw
,
1397 0 /* num_samples */,
1398 INTEL_MIPTREE_TILING_Y
,
1406 * Helper for intel_miptree_alloc_hiz() that sets
1407 * \c mt->level[level].has_hiz. Return true if and only if
1408 * \c has_hiz was set.
1411 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1412 struct intel_mipmap_tree
*mt
,
1415 assert(mt
->hiz_buf
);
1417 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1418 uint32_t width
= minify(mt
->physical_width0
, level
);
1419 uint32_t height
= minify(mt
->physical_height0
, level
);
1421 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1422 * and the height is 4 aligned. This allows our HiZ support
1423 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1424 * we can grow the width & height to allow the HiZ op to
1425 * force the proper size alignments.
1427 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1428 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1433 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1434 mt
->level
[level
].has_hiz
= true;
1440 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1441 * buffer dimensions and allocates a bo for the hiz buffer.
1443 static struct intel_miptree_aux_buffer
*
1444 intel_gen7_hiz_buf_create(struct brw_context
*brw
,
1445 struct intel_mipmap_tree
*mt
)
1447 unsigned z_width
= mt
->logical_width0
;
1448 unsigned z_height
= mt
->logical_height0
;
1449 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1450 unsigned hz_width
, hz_height
;
1451 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1456 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1457 * adjustments required for Z_Height and Z_Width based on multisampling.
1460 switch (mt
->num_samples
) {
1474 unreachable("unsupported sample count");
1478 const unsigned vertical_align
= 8; /* 'j' in the docs */
1479 const unsigned H0
= z_height
;
1480 const unsigned h0
= ALIGN(H0
, vertical_align
);
1481 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1482 const unsigned Z0
= z_depth
;
1484 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1485 hz_width
= ALIGN(z_width
, 16);
1487 if (mt
->target
== GL_TEXTURE_3D
) {
1491 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1492 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1493 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1494 hz_height
+= h_i
* Z_i
;
1495 H_i
= minify(H_i
, 1);
1496 Z_i
= minify(Z_i
, 1);
1499 * (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i)))
1501 hz_height
= DIV_ROUND_UP(hz_height
, 2);
1503 const unsigned hz_qpitch
= h0
+ h1
+ (12 * vertical_align
);
1504 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1505 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1506 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth * 6/2) /8 ) * 8 */
1507 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
* 6, 2 * 8) * 8;
1509 /* HZ_Height (rows) = Ceiling ( ( Q_pitch * Z_depth/2) /8 ) * 8 */
1510 hz_height
= DIV_ROUND_UP(hz_qpitch
* Z0
, 2 * 8) * 8;
1514 unsigned long pitch
;
1515 uint32_t tiling
= I915_TILING_Y
;
1516 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1517 hz_width
, hz_height
, 1,
1519 BO_ALLOC_FOR_RENDER
);
1523 } else if (tiling
!= I915_TILING_Y
) {
1524 drm_intel_bo_unreference(buf
->bo
);
1536 * Helper for intel_miptree_alloc_hiz() that determines the required hiz
1537 * buffer dimensions and allocates a bo for the hiz buffer.
1539 static struct intel_miptree_aux_buffer
*
1540 intel_gen8_hiz_buf_create(struct brw_context
*brw
,
1541 struct intel_mipmap_tree
*mt
)
1543 unsigned z_width
= mt
->logical_width0
;
1544 unsigned z_height
= mt
->logical_height0
;
1545 const unsigned z_depth
= MAX2(mt
->logical_depth0
, 1);
1546 unsigned hz_width
, hz_height
;
1547 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1552 /* Gen7 PRM Volume 2, Part 1, 11.5.3 "Hierarchical Depth Buffer" documents
1553 * adjustments required for Z_Height and Z_Width based on multisampling.
1555 switch (mt
->num_samples
) {
1569 unreachable("unsupported sample count");
1572 const unsigned vertical_align
= 8; /* 'j' in the docs */
1573 const unsigned H0
= z_height
;
1574 const unsigned h0
= ALIGN(H0
, vertical_align
);
1575 const unsigned h1
= ALIGN(minify(H0
, 1), vertical_align
);
1576 const unsigned Z0
= z_depth
;
1578 /* HZ_Width (bytes) = ceiling(Z_Width / 16) * 16 */
1579 hz_width
= ALIGN(z_width
, 16);
1583 unsigned sum_h_i
= 0;
1584 unsigned hz_height_3d_sum
= 0;
1585 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1586 unsigned i
= level
- mt
->first_level
;
1587 unsigned h_i
= ALIGN(H_i
, vertical_align
);
1588 /* sum(i=2 to m; h_i) */
1592 /* sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1593 hz_height_3d_sum
+= h_i
* Z_i
;
1594 H_i
= minify(H_i
, 1);
1595 Z_i
= minify(Z_i
, 1);
1597 /* HZ_QPitch = h0 + max(h1, sum(i=2 to m; h_i)) */
1598 buf
->qpitch
= h0
+ MAX2(h1
, sum_h_i
);
1600 if (mt
->target
== GL_TEXTURE_3D
) {
1601 /* (1/2) * sum(i=0 to m; h_i * max(1, floor(Z_Depth/2**i))) */
1602 hz_height
= DIV_ROUND_UP(hz_height_3d_sum
, 2);
1604 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * Z_Depth */
1605 hz_height
= DIV_ROUND_UP(buf
->qpitch
, 2 * 8) * 8 * Z0
;
1606 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARRAY
||
1607 mt
->target
== GL_TEXTURE_CUBE_MAP
) {
1608 /* HZ_Height (rows) = ceiling( (HZ_QPitch/2)/8) *8 * 6 * Z_Depth
1610 * We can can just take our hz_height calculation from above, and
1611 * multiply by 6 for the cube map and cube map array types.
1617 unsigned long pitch
;
1618 uint32_t tiling
= I915_TILING_Y
;
1619 buf
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "hiz",
1620 hz_width
, hz_height
, 1,
1622 BO_ALLOC_FOR_RENDER
);
1626 } else if (tiling
!= I915_TILING_Y
) {
1627 drm_intel_bo_unreference(buf
->bo
);
1638 static struct intel_miptree_aux_buffer
*
1639 intel_hiz_miptree_buf_create(struct brw_context
*brw
,
1640 struct intel_mipmap_tree
*mt
)
1642 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1643 uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
1646 layout_flags
|= MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
;
1651 buf
->mt
= intel_miptree_create(brw
,
1657 mt
->logical_height0
,
1660 INTEL_MIPTREE_TILING_ANY
,
1667 buf
->bo
= buf
->mt
->bo
;
1668 buf
->pitch
= buf
->mt
->pitch
;
1669 buf
->qpitch
= buf
->mt
->qpitch
;
1675 intel_miptree_wants_hiz_buffer(struct brw_context
*brw
,
1676 struct intel_mipmap_tree
*mt
)
1681 if (mt
->hiz_buf
!= NULL
)
1684 if (mt
->disable_aux_buffers
)
1687 switch (mt
->format
) {
1688 case MESA_FORMAT_Z_FLOAT32
:
1689 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
1690 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
1691 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
1692 case MESA_FORMAT_Z_UNORM16
:
1700 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1701 struct intel_mipmap_tree
*mt
)
1703 assert(mt
->hiz_buf
== NULL
);
1704 assert(!mt
->disable_aux_buffers
);
1706 if (brw
->gen
== 7) {
1707 mt
->hiz_buf
= intel_gen7_hiz_buf_create(brw
, mt
);
1708 } else if (brw
->gen
>= 8) {
1709 mt
->hiz_buf
= intel_gen8_hiz_buf_create(brw
, mt
);
1711 mt
->hiz_buf
= intel_hiz_miptree_buf_create(brw
, mt
);
1717 /* Mark that all slices need a HiZ resolve. */
1718 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1719 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
1722 for (int layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1723 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
1724 exec_node_init(&m
->link
);
1727 m
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1729 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
1737 * Does the miptree slice have hiz enabled?
1740 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
1742 intel_miptree_check_level_layer(mt
, level
, 0);
1743 return mt
->level
[level
].has_hiz
;
1747 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1751 if (!intel_miptree_level_has_hiz(mt
, level
))
1754 intel_resolve_map_set(&mt
->hiz_map
,
1755 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1760 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1764 if (!intel_miptree_level_has_hiz(mt
, level
))
1767 intel_resolve_map_set(&mt
->hiz_map
,
1768 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1772 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1776 uint32_t end_layer
= mt
->level
[level
].depth
;
1778 for (layer
= 0; layer
< end_layer
; layer
++) {
1779 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
1784 intel_miptree_slice_resolve(struct brw_context
*brw
,
1785 struct intel_mipmap_tree
*mt
,
1788 enum gen6_hiz_op need
)
1790 intel_miptree_check_level_layer(mt
, level
, layer
);
1792 struct intel_resolve_map
*item
=
1793 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1795 if (!item
|| item
->need
!= need
)
1798 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
1799 intel_resolve_map_remove(item
);
1804 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
1805 struct intel_mipmap_tree
*mt
,
1809 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1810 GEN6_HIZ_OP_HIZ_RESOLVE
);
1814 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
1815 struct intel_mipmap_tree
*mt
,
1819 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1820 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1824 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
1825 struct intel_mipmap_tree
*mt
,
1826 enum gen6_hiz_op need
)
1828 bool did_resolve
= false;
1830 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
1831 if (map
->need
!= need
)
1834 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
1835 intel_resolve_map_remove(map
);
1843 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
1844 struct intel_mipmap_tree
*mt
)
1846 return intel_miptree_all_slices_resolve(brw
, mt
,
1847 GEN6_HIZ_OP_HIZ_RESOLVE
);
1851 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
1852 struct intel_mipmap_tree
*mt
)
1854 return intel_miptree_all_slices_resolve(brw
, mt
,
1855 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1860 intel_miptree_resolve_color(struct brw_context
*brw
,
1861 struct intel_mipmap_tree
*mt
)
1863 switch (mt
->fast_clear_state
) {
1864 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
1865 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
1866 /* No resolve needed */
1868 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
1869 case INTEL_FAST_CLEAR_STATE_CLEAR
:
1870 /* Fast color clear resolves only make sense for non-MSAA buffers. */
1871 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
)
1872 brw_meta_resolve_color(brw
, mt
);
1879 * Make it possible to share the BO backing the given miptree with another
1880 * process or another miptree.
1882 * Fast color clears are unsafe with shared buffers, so we need to resolve and
1883 * then discard the MCS buffer, if present. We also set the fast_clear_state
1884 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
1885 * allocated in the future.
1888 intel_miptree_make_shareable(struct brw_context
*brw
,
1889 struct intel_mipmap_tree
*mt
)
1891 /* MCS buffers are also used for multisample buffers, but we can't resolve
1892 * away a multisample MCS buffer because it's an integral part of how the
1893 * pixel data is stored. Fortunately this code path should never be
1894 * reached for multisample buffers.
1896 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
1899 intel_miptree_resolve_color(brw
, mt
);
1900 intel_miptree_release(&mt
->mcs_mt
);
1901 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
1907 * \brief Get pointer offset into stencil buffer.
1909 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1910 * must decode the tile's layout in software.
1913 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1915 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1917 * Even though the returned offset is always positive, the return type is
1919 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1920 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1923 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1925 uint32_t tile_size
= 4096;
1926 uint32_t tile_width
= 64;
1927 uint32_t tile_height
= 64;
1928 uint32_t row_size
= 64 * stride
;
1930 uint32_t tile_x
= x
/ tile_width
;
1931 uint32_t tile_y
= y
/ tile_height
;
1933 /* The byte's address relative to the tile's base addres. */
1934 uint32_t byte_x
= x
% tile_width
;
1935 uint32_t byte_y
= y
% tile_height
;
1937 uintptr_t u
= tile_y
* row_size
1938 + tile_x
* tile_size
1939 + 512 * (byte_x
/ 8)
1941 + 32 * ((byte_y
/ 4) % 2)
1942 + 16 * ((byte_x
/ 4) % 2)
1943 + 8 * ((byte_y
/ 2) % 2)
1944 + 4 * ((byte_x
/ 2) % 2)
1949 /* adjust for bit6 swizzling */
1950 if (((byte_x
/ 8) % 2) == 1) {
1951 if (((byte_y
/ 8) % 2) == 0) {
1963 intel_miptree_updownsample(struct brw_context
*brw
,
1964 struct intel_mipmap_tree
*src
,
1965 struct intel_mipmap_tree
*dst
)
1968 brw_blorp_blit_miptrees(brw
,
1969 src
, 0 /* level */, 0 /* layer */, src
->format
,
1970 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
1972 src
->logical_width0
, src
->logical_height0
,
1974 dst
->logical_width0
, dst
->logical_height0
,
1975 GL_NEAREST
, false, false /*mirror x, y*/);
1976 } else if (src
->format
== MESA_FORMAT_S_UINT8
) {
1977 brw_meta_stencil_updownsample(brw
, src
, dst
);
1979 brw_meta_updownsample(brw
, src
, dst
);
1982 if (src
->stencil_mt
) {
1983 if (brw
->gen
>= 8) {
1984 brw_meta_stencil_updownsample(brw
, src
->stencil_mt
, dst
);
1988 brw_blorp_blit_miptrees(brw
,
1989 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
1990 src
->stencil_mt
->format
,
1991 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
1992 dst
->stencil_mt
->format
,
1994 src
->logical_width0
, src
->logical_height0
,
1996 dst
->logical_width0
, dst
->logical_height0
,
1997 GL_NEAREST
, false, false /*mirror x, y*/);
2002 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
2004 /* CPU accesses to color buffers don't understand fast color clears, so
2005 * resolve any pending fast color clears before we map.
2007 intel_miptree_resolve_color(brw
, mt
);
2009 drm_intel_bo
*bo
= mt
->bo
;
2011 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
2012 intel_batchbuffer_flush(brw
);
2014 if (mt
->tiling
!= I915_TILING_NONE
)
2015 brw_bo_map_gtt(brw
, bo
, "miptree");
2017 brw_bo_map(brw
, bo
, true, "miptree");
2023 intel_miptree_unmap_raw(struct brw_context
*brw
,
2024 struct intel_mipmap_tree
*mt
)
2026 drm_intel_bo_unmap(mt
->bo
);
2030 intel_miptree_map_gtt(struct brw_context
*brw
,
2031 struct intel_mipmap_tree
*mt
,
2032 struct intel_miptree_map
*map
,
2033 unsigned int level
, unsigned int slice
)
2035 unsigned int bw
, bh
;
2037 unsigned int image_x
, image_y
;
2038 intptr_t x
= map
->x
;
2039 intptr_t y
= map
->y
;
2041 /* For compressed formats, the stride is the number of bytes per
2042 * row of blocks. intel_miptree_get_image_offset() already does
2045 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2046 assert(y
% bh
== 0);
2049 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
2054 /* Note that in the case of cube maps, the caller must have passed the
2055 * slice number referencing the face.
2057 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2061 map
->stride
= mt
->pitch
;
2062 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
2065 DBG("%s: %d,%d %dx%d from mt %p (%s) "
2066 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
2067 map
->x
, map
->y
, map
->w
, map
->h
,
2068 mt
, _mesa_get_format_name(mt
->format
),
2069 x
, y
, map
->ptr
, map
->stride
);
2073 intel_miptree_unmap_gtt(struct brw_context
*brw
,
2074 struct intel_mipmap_tree
*mt
,
2075 struct intel_miptree_map
*map
,
2079 intel_miptree_unmap_raw(brw
, mt
);
2083 intel_miptree_map_blit(struct brw_context
*brw
,
2084 struct intel_mipmap_tree
*mt
,
2085 struct intel_miptree_map
*map
,
2086 unsigned int level
, unsigned int slice
)
2088 map
->mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
2091 0, INTEL_MIPTREE_TILING_NONE
, 0);
2094 fprintf(stderr
, "Failed to allocate blit temporary\n");
2097 map
->stride
= map
->mt
->pitch
;
2099 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2100 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2101 * invalidate is set, since we'll be writing the whole rectangle from our
2102 * temporary buffer back out.
2104 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2105 if (!intel_miptree_blit(brw
,
2107 map
->x
, map
->y
, false,
2110 map
->w
, map
->h
, GL_COPY
)) {
2111 fprintf(stderr
, "Failed to blit\n");
2116 map
->ptr
= intel_miptree_map_raw(brw
, map
->mt
);
2118 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2119 map
->x
, map
->y
, map
->w
, map
->h
,
2120 mt
, _mesa_get_format_name(mt
->format
),
2121 level
, slice
, map
->ptr
, map
->stride
);
2126 intel_miptree_release(&map
->mt
);
2132 intel_miptree_unmap_blit(struct brw_context
*brw
,
2133 struct intel_mipmap_tree
*mt
,
2134 struct intel_miptree_map
*map
,
2138 struct gl_context
*ctx
= &brw
->ctx
;
2140 intel_miptree_unmap_raw(brw
, map
->mt
);
2142 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2143 bool ok
= intel_miptree_blit(brw
,
2147 map
->x
, map
->y
, false,
2148 map
->w
, map
->h
, GL_COPY
);
2149 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
2152 intel_miptree_release(&map
->mt
);
2156 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
2158 #if defined(USE_SSE41)
2160 intel_miptree_map_movntdqa(struct brw_context
*brw
,
2161 struct intel_mipmap_tree
*mt
,
2162 struct intel_miptree_map
*map
,
2163 unsigned int level
, unsigned int slice
)
2165 assert(map
->mode
& GL_MAP_READ_BIT
);
2166 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
2168 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
2169 map
->x
, map
->y
, map
->w
, map
->h
,
2170 mt
, _mesa_get_format_name(mt
->format
),
2171 level
, slice
, map
->ptr
, map
->stride
);
2173 /* Map the original image */
2176 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2180 void *src
= intel_miptree_map_raw(brw
, mt
);
2183 src
+= image_y
* mt
->pitch
;
2184 src
+= image_x
* mt
->cpp
;
2186 /* Due to the pixel offsets for the particular image being mapped, our
2187 * src pointer may not be 16-byte aligned. However, if the pitch is
2188 * divisible by 16, then the amount by which it's misaligned will remain
2189 * consistent from row to row.
2191 assert((mt
->pitch
% 16) == 0);
2192 const int misalignment
= ((uintptr_t) src
) & 15;
2194 /* Create an untiled temporary buffer for the mapping. */
2195 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
2197 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
2199 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
2200 /* Offset the destination so it has the same misalignment as src. */
2201 map
->ptr
= map
->buffer
+ misalignment
;
2203 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
2205 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2206 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
2207 void *src_ptr
= src
+ y
* mt
->pitch
;
2209 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
2212 intel_miptree_unmap_raw(brw
, mt
);
2216 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
2217 struct intel_mipmap_tree
*mt
,
2218 struct intel_miptree_map
*map
,
2222 _mesa_align_free(map
->buffer
);
2229 intel_miptree_map_s8(struct brw_context
*brw
,
2230 struct intel_mipmap_tree
*mt
,
2231 struct intel_miptree_map
*map
,
2232 unsigned int level
, unsigned int slice
)
2234 map
->stride
= map
->w
;
2235 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2239 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2240 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2241 * invalidate is set, since we'll be writing the whole rectangle from our
2242 * temporary buffer back out.
2244 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2245 uint8_t *untiled_s8_map
= map
->ptr
;
2246 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2247 unsigned int image_x
, image_y
;
2249 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2251 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2252 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2253 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2254 x
+ image_x
+ map
->x
,
2255 y
+ image_y
+ map
->y
,
2256 brw
->has_swizzling
);
2257 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
2261 intel_miptree_unmap_raw(brw
, mt
);
2263 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
2264 map
->x
, map
->y
, map
->w
, map
->h
,
2265 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
2267 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2268 map
->x
, map
->y
, map
->w
, map
->h
,
2269 mt
, map
->ptr
, map
->stride
);
2274 intel_miptree_unmap_s8(struct brw_context
*brw
,
2275 struct intel_mipmap_tree
*mt
,
2276 struct intel_miptree_map
*map
,
2280 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2281 unsigned int image_x
, image_y
;
2282 uint8_t *untiled_s8_map
= map
->ptr
;
2283 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
2285 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2287 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2288 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2289 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
2292 brw
->has_swizzling
);
2293 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
2297 intel_miptree_unmap_raw(brw
, mt
);
2304 intel_miptree_map_etc(struct brw_context
*brw
,
2305 struct intel_mipmap_tree
*mt
,
2306 struct intel_miptree_map
*map
,
2310 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
2311 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
2312 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2315 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2316 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2318 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2319 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2320 map
->w
, map
->h
, 1));
2321 map
->ptr
= map
->buffer
;
2325 intel_miptree_unmap_etc(struct brw_context
*brw
,
2326 struct intel_mipmap_tree
*mt
,
2327 struct intel_miptree_map
*map
,
2333 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2338 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2339 + image_y
* mt
->pitch
2340 + image_x
* mt
->cpp
;
2342 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2343 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2344 map
->ptr
, map
->stride
,
2347 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2348 map
->ptr
, map
->stride
,
2349 map
->w
, map
->h
, mt
->etc_format
);
2351 intel_miptree_unmap_raw(brw
, mt
);
2356 * Mapping function for packed depth/stencil miptrees backed by real separate
2357 * miptrees for depth and stencil.
2359 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2360 * separate from the depth buffer. Yet at the GL API level, we have to expose
2361 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2362 * be able to map that memory for texture storage and glReadPixels-type
2363 * operations. We give Mesa core that access by mallocing a temporary and
2364 * copying the data between the actual backing store and the temporary.
2367 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2368 struct intel_mipmap_tree
*mt
,
2369 struct intel_miptree_map
*map
,
2370 unsigned int level
, unsigned int slice
)
2372 struct intel_mipmap_tree
*z_mt
= mt
;
2373 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2374 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2375 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2377 map
->stride
= map
->w
* packed_bpp
;
2378 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2382 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2383 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2384 * invalidate is set, since we'll be writing the whole rectangle from our
2385 * temporary buffer back out.
2387 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2388 uint32_t *packed_map
= map
->ptr
;
2389 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2390 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2391 unsigned int s_image_x
, s_image_y
;
2392 unsigned int z_image_x
, z_image_y
;
2394 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2395 &s_image_x
, &s_image_y
);
2396 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2397 &z_image_x
, &z_image_y
);
2399 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2400 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2401 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2402 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2405 brw
->has_swizzling
);
2406 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2408 (map_x
+ z_image_x
));
2409 uint8_t s
= s_map
[s_offset
];
2410 uint32_t z
= z_map
[z_offset
];
2412 if (map_z32f_x24s8
) {
2413 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2414 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2416 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2421 intel_miptree_unmap_raw(brw
, s_mt
);
2422 intel_miptree_unmap_raw(brw
, z_mt
);
2424 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2426 map
->x
, map
->y
, map
->w
, map
->h
,
2427 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2428 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2429 map
->ptr
, map
->stride
);
2431 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
2432 map
->x
, map
->y
, map
->w
, map
->h
,
2433 mt
, map
->ptr
, map
->stride
);
2438 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2439 struct intel_mipmap_tree
*mt
,
2440 struct intel_miptree_map
*map
,
2444 struct intel_mipmap_tree
*z_mt
= mt
;
2445 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2446 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2448 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2449 uint32_t *packed_map
= map
->ptr
;
2450 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2451 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2452 unsigned int s_image_x
, s_image_y
;
2453 unsigned int z_image_x
, z_image_y
;
2455 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2456 &s_image_x
, &s_image_y
);
2457 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2458 &z_image_x
, &z_image_y
);
2460 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2461 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2462 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2463 x
+ s_image_x
+ map
->x
,
2464 y
+ s_image_y
+ map
->y
,
2465 brw
->has_swizzling
);
2466 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2468 (x
+ z_image_x
+ map
->x
));
2470 if (map_z32f_x24s8
) {
2471 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2472 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2474 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2475 s_map
[s_offset
] = packed
>> 24;
2476 z_map
[z_offset
] = packed
;
2481 intel_miptree_unmap_raw(brw
, s_mt
);
2482 intel_miptree_unmap_raw(brw
, z_mt
);
2484 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2486 map
->x
, map
->y
, map
->w
, map
->h
,
2487 z_mt
, _mesa_get_format_name(z_mt
->format
),
2488 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2489 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2490 map
->ptr
, map
->stride
);
2497 * Create and attach a map to the miptree at (level, slice). Return the
2500 static struct intel_miptree_map
*
2501 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2510 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2515 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2516 mt
->level
[level
].slice
[slice
].map
= map
;
2528 * Release the map at (level, slice).
2531 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2535 struct intel_miptree_map
**map
;
2537 map
= &mt
->level
[level
].slice
[slice
].map
;
2543 can_blit_slice(struct intel_mipmap_tree
*mt
,
2544 unsigned int level
, unsigned int slice
)
2548 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2549 if (image_x
>= 32768 || image_y
>= 32768)
2552 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2553 if (mt
->pitch
>= 32768)
2560 use_intel_mipree_map_blit(struct brw_context
*brw
,
2561 struct intel_mipmap_tree
*mt
,
2567 /* It's probably not worth swapping to the blit ring because of
2568 * all the overhead involved.
2570 !(mode
& GL_MAP_WRITE_BIT
) &&
2572 (mt
->tiling
== I915_TILING_X
||
2573 /* Prior to Sandybridge, the blitter can't handle Y tiling */
2574 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
)) &&
2575 can_blit_slice(mt
, level
, slice
))
2578 if (mt
->tiling
!= I915_TILING_NONE
&&
2579 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2580 assert(can_blit_slice(mt
, level
, slice
));
2588 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
2589 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
2590 * arithmetic overflow.
2592 * If you call this function and use \a out_stride, then you're doing pointer
2593 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
2594 * bugs. The caller must still take care to avoid 32-bit overflow errors in
2595 * all arithmetic expressions that contain buffer offsets and pixel sizes,
2596 * which usually have type uint32_t or GLuint.
2599 intel_miptree_map(struct brw_context
*brw
,
2600 struct intel_mipmap_tree
*mt
,
2609 ptrdiff_t *out_stride
)
2611 struct intel_miptree_map
*map
;
2613 assert(mt
->num_samples
<= 1);
2615 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2622 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2623 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2624 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2627 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2628 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2629 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2630 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2631 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2632 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2633 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2634 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
2635 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2636 #if defined(USE_SSE41)
2637 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
2638 !mt
->compressed
&& cpu_has_sse4_1
&&
2639 (mt
->pitch
% 16 == 0)) {
2640 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2643 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2646 *out_ptr
= map
->ptr
;
2647 *out_stride
= map
->stride
;
2649 if (map
->ptr
== NULL
)
2650 intel_miptree_release_map(mt
, level
, slice
);
2654 intel_miptree_unmap(struct brw_context
*brw
,
2655 struct intel_mipmap_tree
*mt
,
2659 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2661 assert(mt
->num_samples
<= 1);
2666 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
2667 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2669 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2670 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2671 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2672 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2673 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2674 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2675 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2676 } else if (map
->mt
) {
2677 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2678 #if defined(USE_SSE41)
2679 } else if (map
->buffer
&& cpu_has_sse4_1
) {
2680 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2683 intel_miptree_unmap_gtt(brw
, mt
, map
, level
, slice
);
2686 intel_miptree_release_map(mt
, level
, slice
);