2 * Copyright 2006 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <GL/internal/dri_interface.h>
29 #include "intel_batchbuffer.h"
30 #include "intel_image.h"
31 #include "intel_mipmap_tree.h"
32 #include "intel_tex.h"
33 #include "intel_blit.h"
34 #include "intel_fbo.h"
36 #include "brw_blorp.h"
37 #include "brw_context.h"
38 #include "brw_state.h"
40 #include "main/enums.h"
41 #include "main/fbobject.h"
42 #include "main/formats.h"
43 #include "main/glformats.h"
44 #include "main/texcompress_etc.h"
45 #include "main/teximage.h"
46 #include "main/streaming-load-memcpy.h"
47 #include "x86/common_x86_asm.h"
49 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
51 static void *intel_miptree_map_raw(struct brw_context
*brw
,
52 struct intel_mipmap_tree
*mt
,
55 static void intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
);
58 intel_miptree_alloc_aux(struct brw_context
*brw
,
59 struct intel_mipmap_tree
*mt
);
62 is_mcs_supported(const struct brw_context
*brw
, mesa_format format
,
63 uint32_t layout_flags
)
65 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
69 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
70 switch (_mesa_get_format_base_format(format
)) {
71 case GL_DEPTH_COMPONENT
:
72 case GL_STENCIL_INDEX
:
73 case GL_DEPTH_STENCIL
:
76 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
78 * This field must be set to 0 for all SINT MSRTs when all RT channels
81 * In practice this means that we have to disable MCS for all signed
82 * integer MSAA buffers. The alternative, to disable MCS only when one
83 * of the render target channels is disabled, is impractical because it
84 * would require converting between CMS and UMS MSAA layouts on the fly,
87 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
89 } else if (layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
) {
90 /* We can't use the CMS layout because it uses an aux buffer, the MCS
91 * buffer. So fallback to UMS, which is identical to CMS without the
101 * Determine which MSAA layout should be used by the MSAA surface being
102 * created, based on the chip generation and the surface type.
104 static enum isl_msaa_layout
105 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
,
106 uint32_t layout_flags
)
108 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
110 return ISL_MSAA_LAYOUT_INTERLEAVED
;
112 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
113 switch (_mesa_get_format_base_format(format
)) {
114 case GL_DEPTH_COMPONENT
:
115 case GL_STENCIL_INDEX
:
116 case GL_DEPTH_STENCIL
:
117 return ISL_MSAA_LAYOUT_INTERLEAVED
;
119 return ISL_MSAA_LAYOUT_ARRAY
;
124 intel_tiling_supports_ccs(const struct brw_context
*brw
, unsigned tiling
)
126 /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
127 * Target(s)", beneath the "Fast Color Clear" bullet (p326):
129 * - Support is limited to tiled render targets.
131 * Gen9 changes the restriction to Y-tile only.
134 return tiling
== I915_TILING_Y
;
135 else if (brw
->gen
>= 7)
136 return tiling
!= I915_TILING_NONE
;
142 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
143 * can be used. This doesn't (and should not) inspect any of the properties of
146 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
147 * beneath the "Fast Color Clear" bullet (p326):
149 * - Support is for non-mip-mapped and non-array surface types only.
151 * And then later, on p327:
153 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
156 * From the Skylake documentation, it is made clear that X-tiling is no longer
159 * - MCS and Lossless compression is supported for TiledY/TileYs/TileYf
163 intel_miptree_supports_ccs(struct brw_context
*brw
,
164 const struct intel_mipmap_tree
*mt
)
166 /* MCS support does not exist prior to Gen7 */
170 /* This function applies only to non-multisampled render targets. */
171 if (mt
->num_samples
> 1)
174 /* MCS is only supported for color buffers */
175 switch (_mesa_get_format_base_format(mt
->format
)) {
176 case GL_DEPTH_COMPONENT
:
177 case GL_DEPTH_STENCIL
:
178 case GL_STENCIL_INDEX
:
182 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
185 const bool mip_mapped
= mt
->first_level
!= 0 || mt
->last_level
!= 0;
186 const bool arrayed
= mt
->physical_depth0
!= 1;
189 /* Multisample surfaces with the CMS layout are not layered surfaces,
190 * yet still have physical_depth0 > 1. Assert that we don't
191 * accidentally reject a multisampled surface here. We should have
192 * rejected it earlier by explicitly checking the sample count.
194 assert(mt
->num_samples
== 1);
197 /* Handle the hardware restrictions...
199 * All GENs have the following restriction: "MCS buffer for non-MSRT is
200 * supported only for RT formats 32bpp, 64bpp, and 128bpp."
202 * From the HSW PRM Volume 7: 3D-Media-GPGPU, page 652: (Color Clear of
203 * Non-MultiSampler Render Target Restrictions) Support is for
204 * non-mip-mapped and non-array surface types only.
206 * From the BDW PRM Volume 7: 3D-Media-GPGPU, page 649: (Color Clear of
207 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
208 * surfaces are supported with MCS buffer layout with these alignments in
209 * the RT space: Horizontal Alignment = 256 and Vertical Alignment = 128.
211 * From the SKL PRM Volume 7: 3D-Media-GPGPU, page 632: (Color Clear of
212 * Non-MultiSampler Render Target Restriction). Mip-mapped and arrayed
213 * surfaces are supported with MCS buffer layout with these alignments in
214 * the RT space: Horizontal Alignment = 128 and Vertical Alignment = 64.
216 if (brw
->gen
< 8 && (mip_mapped
|| arrayed
))
219 /* There's no point in using an MCS buffer if the surface isn't in a
222 if (!brw
->mesa_format_supports_render
[mt
->format
])
226 mesa_format linear_format
= _mesa_get_srgb_format_linear(mt
->format
);
227 const enum isl_format isl_format
=
228 brw_isl_format_for_mesa_format(linear_format
);
229 return isl_format_supports_ccs_e(&brw
->screen
->devinfo
, isl_format
);
235 intel_tiling_supports_hiz(const struct brw_context
*brw
, unsigned tiling
)
240 return tiling
== I915_TILING_Y
;
244 intel_miptree_supports_hiz(const struct brw_context
*brw
,
245 const struct intel_mipmap_tree
*mt
)
250 switch (mt
->format
) {
251 case MESA_FORMAT_Z_FLOAT32
:
252 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
253 case MESA_FORMAT_Z24_UNORM_X8_UINT
:
254 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
255 case MESA_FORMAT_Z_UNORM16
:
263 intel_miptree_supports_ccs_e(struct brw_context
*brw
,
264 const struct intel_mipmap_tree
*mt
)
266 /* For now compression is only enabled for integer formats even though
267 * there exist supported floating point formats also. This is a heuristic
268 * decision based on current public benchmarks. In none of the cases these
269 * formats provided any improvement but a few cases were seen to regress.
270 * Hence these are left to to be enabled in the future when they are known
273 if (_mesa_get_format_datatype(mt
->format
) == GL_FLOAT
)
276 if (!intel_miptree_supports_ccs(brw
, mt
))
279 /* Fast clear can be also used to clear srgb surfaces by using equivalent
280 * linear format. This trick, however, can't be extended to be used with
281 * lossless compression and therefore a check is needed to see if the format
284 return _mesa_get_srgb_format_linear(mt
->format
) == mt
->format
;
288 * Determine depth format corresponding to a depth+stencil format,
289 * for separate stencil.
292 intel_depth_format_for_depthstencil_format(mesa_format format
) {
294 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
295 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
296 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
297 return MESA_FORMAT_Z_FLOAT32
;
304 create_mapping_table(GLenum target
, unsigned first_level
, unsigned last_level
,
305 unsigned depth0
, struct intel_mipmap_level
*table
)
307 for (unsigned level
= first_level
; level
<= last_level
; level
++) {
309 target
== GL_TEXTURE_3D
? minify(depth0
, level
) : depth0
;
311 table
[level
].slice
= calloc(d
, sizeof(*table
[0].slice
));
312 if (!table
[level
].slice
)
319 for (unsigned level
= first_level
; level
<= last_level
; level
++)
320 free(table
[level
].slice
);
326 needs_separate_stencil(const struct brw_context
*brw
,
327 struct intel_mipmap_tree
*mt
,
328 mesa_format format
, uint32_t layout_flags
)
331 if (layout_flags
& MIPTREE_LAYOUT_FOR_BO
)
334 if (_mesa_get_format_base_format(format
) != GL_DEPTH_STENCIL
)
337 if (brw
->must_use_separate_stencil
)
340 return brw
->has_separate_stencil
&&
341 intel_miptree_supports_hiz(brw
, mt
);
345 * @param for_bo Indicates that the caller is
346 * intel_miptree_create_for_bo(). If true, then do not create
349 static struct intel_mipmap_tree
*
350 intel_miptree_create_layout(struct brw_context
*brw
,
359 uint32_t layout_flags
)
361 assert(num_samples
> 0);
363 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
367 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __func__
,
368 _mesa_enum_to_string(target
),
369 _mesa_get_format_name(format
),
370 first_level
, last_level
, depth0
, mt
);
372 if (target
== GL_TEXTURE_1D_ARRAY
)
373 assert(height0
== 1);
377 mt
->first_level
= first_level
;
378 mt
->last_level
= last_level
;
379 mt
->logical_width0
= width0
;
380 mt
->logical_height0
= height0
;
381 mt
->logical_depth0
= depth0
;
382 mt
->is_scanout
= (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
) != 0;
383 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
384 mt
->supports_fast_clear
= false;
385 mt
->aux_state
= NULL
;
386 mt
->cpp
= _mesa_get_format_bytes(format
);
387 mt
->num_samples
= num_samples
;
388 mt
->compressed
= _mesa_is_format_compressed(format
);
389 mt
->surf
.msaa_layout
= ISL_MSAA_LAYOUT_NONE
;
392 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
393 layout_flags
|= MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
;
395 int depth_multiply
= 1;
396 if (num_samples
> 1) {
397 /* Adjust width/height/depth for MSAA */
398 mt
->surf
.msaa_layout
= compute_msaa_layout(brw
, format
, layout_flags
);
399 if (mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_INTERLEAVED
) {
400 /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
401 * "If the surface is multisampled and it is a depth or stencil
402 * surface or Multisampled Surface StorageFormat in SURFACE_STATE is
403 * MSFMT_DEPTH_STENCIL, WL and HL must be adjusted as follows before
406 * +----------------------------------------------------------------+
407 * | Num Multisamples | W_l = | H_l = |
408 * +----------------------------------------------------------------+
409 * | 2 | ceiling(W_l / 2) * 4 | H_l (no adjustment) |
410 * | 4 | ceiling(W_l / 2) * 4 | ceiling(H_l / 2) * 4 |
411 * | 8 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 4 |
412 * | 16 | ceiling(W_l / 2) * 8 | ceiling(H_l / 2) * 8 |
413 * +----------------------------------------------------------------+
416 * Note that MSFMT_DEPTH_STENCIL just means the IMS (interleaved)
417 * format rather than UMS/CMS (array slices). The Sandybridge PRM,
418 * Volume 1, Part 1, Page 111 has the same formula for 4x MSAA.
420 * Another more complicated explanation for these adjustments comes
421 * from the Sandybridge PRM, volume 4, part 1, page 31:
423 * "Any of the other messages (sample*, LOD, load4) used with a
424 * (4x) multisampled surface will in-effect sample a surface with
425 * double the height and width as that indicated in the surface
426 * state. Each pixel position on the original-sized surface is
427 * replaced with a 2x2 of samples with the following arrangement:
432 * Thus, when sampling from a multisampled texture, it behaves as
433 * though the layout in memory for (x,y,sample) is:
435 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
436 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
438 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
439 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
441 * However, the actual layout of multisampled data in memory is:
443 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
444 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
446 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
447 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
449 * This pattern repeats for each 2x2 pixel block.
451 * As a result, when calculating the size of our 4-sample buffer for
452 * an odd width or height, we have to align before scaling up because
453 * sample 3 is in that bottom right 2x2 block.
455 switch (num_samples
) {
457 assert(brw
->gen
>= 8);
458 width0
= ALIGN(width0
, 2) * 2;
459 height0
= ALIGN(height0
, 2);
462 width0
= ALIGN(width0
, 2) * 2;
463 height0
= ALIGN(height0
, 2) * 2;
466 width0
= ALIGN(width0
, 2) * 4;
467 height0
= ALIGN(height0
, 2) * 2;
470 width0
= ALIGN(width0
, 2) * 4;
471 height0
= ALIGN(height0
, 2) * 4;
474 /* num_samples should already have been quantized to 0, 1, 2, 4, 8
477 unreachable("not reached");
480 /* Non-interleaved */
481 depth_multiply
= num_samples
;
482 depth0
*= depth_multiply
;
486 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
492 /* Set array_layout to ALL_SLICES_AT_EACH_LOD when array_spacing_lod0 can
493 * be used. array_spacing_lod0 is only used for non-IMS MSAA surfaces on
494 * Gen 7 and 8. On Gen 8 and 9 this layout is not available but it is still
495 * used on Gen8 to make it pick a qpitch value which doesn't include space
496 * for the mipmaps. On Gen9 this is not necessary because it will
497 * automatically pick a packed qpitch value whenever mt->first_level ==
499 * TODO: can we use it elsewhere?
500 * TODO: also disable this on Gen8 and pick the qpitch value like Gen9
503 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
505 switch (mt
->surf
.msaa_layout
) {
506 case ISL_MSAA_LAYOUT_NONE
:
507 case ISL_MSAA_LAYOUT_INTERLEAVED
:
508 mt
->array_layout
= ALL_LOD_IN_EACH_SLICE
;
510 case ISL_MSAA_LAYOUT_ARRAY
:
511 mt
->array_layout
= ALL_SLICES_AT_EACH_LOD
;
516 if (target
== GL_TEXTURE_CUBE_MAP
)
517 assert(depth0
== 6 * depth_multiply
);
519 mt
->physical_width0
= width0
;
520 mt
->physical_height0
= height0
;
521 mt
->physical_depth0
= depth0
;
523 if (needs_separate_stencil(brw
, mt
, format
, layout_flags
)) {
524 uint32_t stencil_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
;
526 stencil_flags
|= MIPTREE_LAYOUT_TILING_ANY
;
529 mt
->stencil_mt
= intel_miptree_create(brw
,
540 if (!mt
->stencil_mt
) {
541 intel_miptree_release(&mt
);
544 mt
->stencil_mt
->r8stencil_needs_update
= true;
546 /* Fix up the Z miptree format for how we're splitting out separate
547 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
549 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
552 if (format
== mt
->format
) {
553 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
554 _mesa_get_format_name(mt
->format
));
558 if (layout_flags
& MIPTREE_LAYOUT_GEN6_HIZ_STENCIL
)
559 mt
->array_layout
= GEN6_HIZ_STENCIL
;
562 * Obey HALIGN_16 constraints for Gen8 and Gen9 buffers which are
563 * multisampled or have an AUX buffer attached to it.
565 * GEN | MSRT | AUX_CCS_* or AUX_MCS
566 * -------------------------------------------
567 * 9 | HALIGN_16 | HALIGN_16
568 * 8 | HALIGN_ANY | HALIGN_16
572 if (intel_miptree_supports_ccs(brw
, mt
)) {
573 if (brw
->gen
>= 9 || (brw
->gen
== 8 && num_samples
== 1))
574 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
575 } else if (brw
->gen
>= 9 && num_samples
> 1) {
576 layout_flags
|= MIPTREE_LAYOUT_FORCE_HALIGN16
;
578 const UNUSED
bool is_lossless_compressed_aux
=
579 brw
->gen
>= 9 && num_samples
== 1 &&
580 mt
->format
== MESA_FORMAT_R_UINT32
;
582 /* For now, nothing else has this requirement */
583 assert(is_lossless_compressed_aux
||
584 (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
587 if (!brw_miptree_layout(brw
, mt
, layout_flags
)) {
588 intel_miptree_release(&mt
);
597 * Choose the aux usage for this miptree. This function must be called fairly
598 * late in the miptree create process after we have a tiling.
601 intel_miptree_choose_aux_usage(struct brw_context
*brw
,
602 struct intel_mipmap_tree
*mt
)
604 assert(mt
->aux_usage
== ISL_AUX_USAGE_NONE
);
606 const unsigned no_flags
= 0;
607 if (mt
->num_samples
> 1 && is_mcs_supported(brw
, mt
->format
, no_flags
)) {
608 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
609 mt
->aux_usage
= ISL_AUX_USAGE_MCS
;
610 } else if (intel_tiling_supports_ccs(brw
, mt
->tiling
) &&
611 intel_miptree_supports_ccs(brw
, mt
)) {
612 if (!unlikely(INTEL_DEBUG
& DEBUG_NO_RBC
) &&
613 brw
->gen
>= 9 && !mt
->is_scanout
&&
614 intel_miptree_supports_ccs_e(brw
, mt
)) {
615 mt
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
617 mt
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
619 } else if (intel_tiling_supports_hiz(brw
, mt
->tiling
) &&
620 intel_miptree_supports_hiz(brw
, mt
)) {
621 mt
->aux_usage
= ISL_AUX_USAGE_HIZ
;
624 /* We can do fast-clear on all auxiliary surface types that are
625 * allocated through the normal texture creation paths.
627 if (mt
->aux_usage
!= ISL_AUX_USAGE_NONE
)
628 mt
->supports_fast_clear
= true;
633 * Choose an appropriate uncompressed format for a requested
634 * compressed format, if unsupported.
637 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
639 /* No need to lower ETC formats on these platforms,
640 * they are supported natively.
642 if (brw
->gen
>= 8 || brw
->is_baytrail
)
646 case MESA_FORMAT_ETC1_RGB8
:
647 return MESA_FORMAT_R8G8B8X8_UNORM
;
648 case MESA_FORMAT_ETC2_RGB8
:
649 return MESA_FORMAT_R8G8B8X8_UNORM
;
650 case MESA_FORMAT_ETC2_SRGB8
:
651 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
652 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
653 return MESA_FORMAT_B8G8R8A8_SRGB
;
654 case MESA_FORMAT_ETC2_RGBA8_EAC
:
655 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
656 return MESA_FORMAT_R8G8B8A8_UNORM
;
657 case MESA_FORMAT_ETC2_R11_EAC
:
658 return MESA_FORMAT_R_UNORM16
;
659 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
660 return MESA_FORMAT_R_SNORM16
;
661 case MESA_FORMAT_ETC2_RG11_EAC
:
662 return MESA_FORMAT_R16G16_UNORM
;
663 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
664 return MESA_FORMAT_R16G16_SNORM
;
666 /* Non ETC1 / ETC2 format */
671 /** \brief Assert that the level and layer are valid for the miptree. */
673 intel_miptree_check_level_layer(const struct intel_mipmap_tree
*mt
,
681 assert(level
>= mt
->first_level
);
682 assert(level
<= mt
->last_level
);
684 if (mt
->surf
.size
> 0)
685 assert(layer
< (mt
->surf
.dim
== ISL_SURF_DIM_3D
?
686 minify(mt
->surf
.phys_level0_sa
.depth
, level
) :
687 mt
->surf
.phys_level0_sa
.array_len
));
689 assert(layer
< mt
->level
[level
].depth
);
692 static enum isl_aux_state
**
693 create_aux_state_map(struct intel_mipmap_tree
*mt
,
694 enum isl_aux_state initial
)
696 const uint32_t levels
= mt
->last_level
+ 1;
698 uint32_t total_slices
= 0;
699 for (uint32_t level
= 0; level
< levels
; level
++)
700 total_slices
+= mt
->level
[level
].depth
;
702 const size_t per_level_array_size
= levels
* sizeof(enum isl_aux_state
*);
704 /* We're going to allocate a single chunk of data for both the per-level
705 * reference array and the arrays of aux_state. This makes cleanup
706 * significantly easier.
708 const size_t total_size
= per_level_array_size
+
709 total_slices
* sizeof(enum isl_aux_state
);
710 void *data
= malloc(total_size
);
714 enum isl_aux_state
**per_level_arr
= data
;
715 enum isl_aux_state
*s
= data
+ per_level_array_size
;
716 for (uint32_t level
= 0; level
< levels
; level
++) {
717 per_level_arr
[level
] = s
;
718 for (uint32_t a
= 0; a
< mt
->level
[level
].depth
; a
++)
721 assert((void *)s
== data
+ total_size
);
723 return per_level_arr
;
727 free_aux_state_map(enum isl_aux_state
**state
)
732 static struct intel_mipmap_tree
*
733 make_surface(struct brw_context
*brw
, GLenum target
, mesa_format format
,
734 unsigned first_level
, unsigned last_level
,
735 unsigned width0
, unsigned height0
, unsigned depth0
,
736 unsigned num_samples
, isl_tiling_flags_t tiling_flags
,
737 isl_surf_usage_flags_t isl_usage_flags
, uint32_t alloc_flags
,
738 unsigned row_pitch
, struct brw_bo
*bo
)
740 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
744 if (!create_mapping_table(target
, first_level
, last_level
, depth0
,
752 if (target
== GL_TEXTURE_CUBE_MAP
||
753 target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
754 isl_usage_flags
|= ISL_SURF_USAGE_CUBE_BIT
;
756 DBG("%s: %s %s %ux %u:%u:%u %d..%d <-- %p\n",
758 _mesa_enum_to_string(target
),
759 _mesa_get_format_name(format
),
760 num_samples
, width0
, height0
, depth0
,
761 first_level
, last_level
, mt
);
763 struct isl_surf_init_info init_info
= {
764 .dim
= get_isl_surf_dim(target
),
765 .format
= translate_tex_format(brw
, format
, false),
768 .depth
= target
== GL_TEXTURE_3D
? depth0
: 1,
769 .levels
= last_level
- first_level
+ 1,
770 .array_len
= target
== GL_TEXTURE_3D
? 1 : depth0
,
771 .samples
= num_samples
,
772 .row_pitch
= row_pitch
,
773 .usage
= isl_usage_flags
,
774 .tiling_flags
= tiling_flags
,
777 if (!isl_surf_init_s(&brw
->isl_dev
, &mt
->surf
, &init_info
))
780 assert(mt
->surf
.size
% mt
->surf
.row_pitch
== 0);
783 mt
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, "isl-miptree",
785 isl_tiling_to_bufmgr_tiling(
787 mt
->surf
.row_pitch
, alloc_flags
);
794 mt
->first_level
= first_level
;
795 mt
->last_level
= last_level
;
798 mt
->aux_state
= NULL
;
803 intel_miptree_release(&mt
);
807 static struct intel_mipmap_tree
*
808 miptree_create(struct brw_context
*brw
,
817 uint32_t layout_flags
)
819 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
)
820 return make_surface(brw
, target
, format
, first_level
, last_level
,
821 width0
, height0
, depth0
, num_samples
,
823 ISL_SURF_USAGE_STENCIL_BIT
|
824 ISL_SURF_USAGE_TEXTURE_BIT
,
825 BO_ALLOC_FOR_RENDER
, 0, NULL
);
827 struct intel_mipmap_tree
*mt
;
828 mesa_format tex_format
= format
;
829 mesa_format etc_format
= MESA_FORMAT_NONE
;
830 uint32_t alloc_flags
= 0;
832 format
= intel_lower_compressed_format(brw
, format
);
834 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
836 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
837 mt
= intel_miptree_create_layout(brw
, target
, format
,
838 first_level
, last_level
, width0
,
839 height0
, depth0
, num_samples
,
844 if (mt
->tiling
== (I915_TILING_Y
| I915_TILING_X
))
845 mt
->tiling
= I915_TILING_Y
;
847 if (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
)
848 alloc_flags
|= BO_ALLOC_FOR_RENDER
;
850 mt
->etc_format
= etc_format
;
852 if (format
== MESA_FORMAT_S_UINT8
) {
853 /* Align to size of W tile, 64x64. */
854 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
855 ALIGN(mt
->total_width
, 64),
856 ALIGN(mt
->total_height
, 64),
857 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
860 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
861 mt
->total_width
, mt
->total_height
,
862 mt
->cpp
, mt
->tiling
, &mt
->pitch
,
866 if (layout_flags
& MIPTREE_LAYOUT_FOR_SCANOUT
)
867 mt
->bo
->cache_coherent
= false;
869 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
870 intel_miptree_choose_aux_usage(brw
, mt
);
875 struct intel_mipmap_tree
*
876 intel_miptree_create(struct brw_context
*brw
,
885 uint32_t layout_flags
)
887 assert(num_samples
> 0);
889 struct intel_mipmap_tree
*mt
= miptree_create(
891 first_level
, last_level
,
892 width0
, height0
, depth0
, num_samples
,
897 /* If the BO is too large to fit in the aperture, we need to use the
898 * BLT engine to support it. Prior to Sandybridge, the BLT paths can't
899 * handle Y-tiling, so we need to fall back to X.
901 if (brw
->gen
< 6 && mt
->bo
->size
>= brw
->max_gtt_map_object_size
&&
902 mt
->tiling
== I915_TILING_Y
) {
903 const uint32_t alloc_flags
=
904 (layout_flags
& MIPTREE_LAYOUT_ACCELERATED_UPLOAD
) ?
905 BO_ALLOC_FOR_RENDER
: 0;
906 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
907 mt
->total_width
, mt
->total_height
);
909 mt
->tiling
= I915_TILING_X
;
910 brw_bo_unreference(mt
->bo
);
911 mt
->bo
= brw_bo_alloc_tiled_2d(brw
->bufmgr
, "miptree",
912 mt
->total_width
, mt
->total_height
, mt
->cpp
,
913 mt
->tiling
, &mt
->pitch
, alloc_flags
);
919 intel_miptree_release(&mt
);
923 if (!intel_miptree_alloc_aux(brw
, mt
)) {
924 intel_miptree_release(&mt
);
931 struct intel_mipmap_tree
*
932 intel_miptree_create_for_bo(struct brw_context
*brw
,
940 uint32_t layout_flags
)
942 struct intel_mipmap_tree
*mt
;
943 uint32_t tiling
, swizzle
;
944 const GLenum target
= depth
> 1 ? GL_TEXTURE_2D_ARRAY
: GL_TEXTURE_2D
;
946 if (brw
->gen
== 6 && format
== MESA_FORMAT_S_UINT8
) {
947 mt
= make_surface(brw
, target
, MESA_FORMAT_S_UINT8
,
948 0, 0, width
, height
, depth
, 1,
950 ISL_SURF_USAGE_STENCIL_BIT
|
951 ISL_SURF_USAGE_TEXTURE_BIT
,
952 BO_ALLOC_FOR_RENDER
, pitch
, bo
);
956 assert(bo
->size
>= mt
->surf
.size
);
958 brw_bo_reference(bo
);
962 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
964 /* Nothing will be able to use this miptree with the BO if the offset isn't
967 if (tiling
!= I915_TILING_NONE
)
968 assert(offset
% 4096 == 0);
970 /* miptrees can't handle negative pitch. If you need flipping of images,
971 * that's outside of the scope of the mt.
975 /* The BO already has a tiling format and we shouldn't confuse the lower
976 * layers by making it try to find a tiling format again.
978 assert((layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) == 0);
979 assert((layout_flags
& MIPTREE_LAYOUT_TILING_NONE
) == 0);
981 layout_flags
|= MIPTREE_LAYOUT_FOR_BO
;
982 mt
= intel_miptree_create_layout(brw
, target
, format
,
984 width
, height
, depth
,
990 brw_bo_reference(bo
);
996 if (!(layout_flags
& MIPTREE_LAYOUT_DISABLE_AUX
))
997 intel_miptree_choose_aux_usage(brw
, mt
);
1002 static struct intel_mipmap_tree
*
1003 miptree_create_for_planar_image(struct brw_context
*brw
,
1004 __DRIimage
*image
, GLenum target
)
1006 struct intel_image_format
*f
= image
->planar_format
;
1007 struct intel_mipmap_tree
*planar_mt
= NULL
;
1009 for (int i
= 0; i
< f
->nplanes
; i
++) {
1010 const int index
= f
->planes
[i
].buffer_index
;
1011 const uint32_t dri_format
= f
->planes
[i
].dri_format
;
1012 const mesa_format format
= driImageFormatToGLFormat(dri_format
);
1013 const uint32_t width
= image
->width
>> f
->planes
[i
].width_shift
;
1014 const uint32_t height
= image
->height
>> f
->planes
[i
].height_shift
;
1016 /* Disable creation of the texture's aux buffers because the driver
1017 * exposes no EGL API to manage them. That is, there is no API for
1018 * resolving the aux buffer's content to the main buffer nor for
1019 * invalidating the aux buffer's content.
1021 struct intel_mipmap_tree
*mt
=
1022 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1023 image
->offsets
[index
],
1025 image
->strides
[index
],
1026 MIPTREE_LAYOUT_DISABLE_AUX
);
1030 mt
->target
= target
;
1035 planar_mt
->plane
[i
- 1] = mt
;
1041 struct intel_mipmap_tree
*
1042 intel_miptree_create_for_dri_image(struct brw_context
*brw
,
1043 __DRIimage
*image
, GLenum target
,
1044 enum isl_colorspace colorspace
,
1045 bool is_winsys_image
)
1047 if (image
->planar_format
&& image
->planar_format
->nplanes
> 0) {
1048 assert(colorspace
== ISL_COLORSPACE_NONE
||
1049 colorspace
== ISL_COLORSPACE_YUV
);
1050 return miptree_create_for_planar_image(brw
, image
, target
);
1053 mesa_format format
= image
->format
;
1054 switch (colorspace
) {
1055 case ISL_COLORSPACE_NONE
:
1056 /* Keep the image format unmodified */
1059 case ISL_COLORSPACE_LINEAR
:
1060 format
=_mesa_get_srgb_format_linear(format
);
1063 case ISL_COLORSPACE_SRGB
:
1064 format
=_mesa_get_linear_format_srgb(format
);
1068 unreachable("Inalid colorspace for non-planar image");
1071 if (!brw
->ctx
.TextureFormatSupported
[format
]) {
1072 /* The texture storage paths in core Mesa detect if the driver does not
1073 * support the user-requested format, and then searches for a
1074 * fallback format. The DRIimage code bypasses core Mesa, though. So we
1075 * do the fallbacks here for important formats.
1077 * We must support DRM_FOURCC_XBGR8888 textures because the Android
1078 * framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which
1079 * the Chrome OS compositor consumes as dma_buf EGLImages.
1081 format
= _mesa_format_fallback_rgbx_to_rgba(format
);
1084 if (!brw
->ctx
.TextureFormatSupported
[format
])
1087 /* If this image comes in from a window system, we have different
1088 * requirements than if it comes in via an EGL import operation. Window
1089 * system images can use any form of auxiliary compression we wish because
1090 * they get "flushed" before being handed off to the window system and we
1091 * have the opportunity to do resolves. Window system buffers also may be
1092 * used for scanout so we need to flag that appropriately.
1094 const uint32_t mt_layout_flags
=
1095 is_winsys_image
? MIPTREE_LAYOUT_FOR_SCANOUT
: MIPTREE_LAYOUT_DISABLE_AUX
;
1097 /* Disable creation of the texture's aux buffers because the driver exposes
1098 * no EGL API to manage them. That is, there is no API for resolving the aux
1099 * buffer's content to the main buffer nor for invalidating the aux buffer's
1102 struct intel_mipmap_tree
*mt
=
1103 intel_miptree_create_for_bo(brw
, image
->bo
, format
,
1104 image
->offset
, image
->width
, image
->height
, 1,
1105 image
->pitch
, mt_layout_flags
);
1109 mt
->target
= target
;
1110 mt
->level
[0].level_x
= image
->tile_x
;
1111 mt
->level
[0].level_y
= image
->tile_y
;
1112 mt
->level
[0].slice
[0].x_offset
= image
->tile_x
;
1113 mt
->level
[0].slice
[0].y_offset
= image
->tile_y
;
1115 /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
1116 * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
1117 * trouble resolving back to destination image due to alignment issues.
1119 if (!brw
->has_surface_tile_offset
) {
1120 uint32_t draw_x
, draw_y
;
1121 intel_miptree_get_tile_offsets(mt
, 0, 0, &draw_x
, &draw_y
);
1123 if (draw_x
!= 0 || draw_y
!= 0) {
1124 _mesa_error(&brw
->ctx
, GL_INVALID_OPERATION
, __func__
);
1125 intel_miptree_release(&mt
);
1130 if (!intel_miptree_alloc_aux(brw
, mt
)) {
1131 intel_miptree_release(&mt
);
1139 * For a singlesample renderbuffer, this simply wraps the given BO with a
1142 * For a multisample renderbuffer, this wraps the window system's
1143 * (singlesample) BO with a singlesample miptree attached to the
1144 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
1145 * that will contain the actual rendering (which is lazily resolved to
1146 * irb->singlesample_mt).
1149 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
1150 struct intel_renderbuffer
*irb
,
1151 struct intel_mipmap_tree
*singlesample_mt
,
1152 uint32_t width
, uint32_t height
,
1155 struct intel_mipmap_tree
*multisample_mt
= NULL
;
1156 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
1157 mesa_format format
= rb
->Format
;
1158 const unsigned num_samples
= MAX2(rb
->NumSamples
, 1);
1160 /* Only the front and back buffers, which are color buffers, are allocated
1161 * through the image loader.
1163 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
1164 _mesa_get_format_base_format(format
) == GL_RGBA
);
1166 assert(singlesample_mt
);
1168 if (num_samples
== 1) {
1169 intel_miptree_release(&irb
->mt
);
1170 irb
->mt
= singlesample_mt
;
1172 assert(!irb
->singlesample_mt
);
1174 intel_miptree_release(&irb
->singlesample_mt
);
1175 irb
->singlesample_mt
= singlesample_mt
;
1178 irb
->mt
->logical_width0
!= width
||
1179 irb
->mt
->logical_height0
!= height
) {
1180 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
1185 if (!multisample_mt
)
1188 irb
->need_downsample
= false;
1189 intel_miptree_release(&irb
->mt
);
1190 irb
->mt
= multisample_mt
;
1196 intel_miptree_release(&irb
->mt
);
1200 struct intel_mipmap_tree
*
1201 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
1205 uint32_t num_samples
)
1207 struct intel_mipmap_tree
*mt
;
1209 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
1210 const uint32_t layout_flags
= MIPTREE_LAYOUT_ACCELERATED_UPLOAD
|
1211 MIPTREE_LAYOUT_TILING_ANY
|
1212 MIPTREE_LAYOUT_FOR_SCANOUT
;
1214 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
1215 width
, height
, depth
, num_samples
,
1223 intel_miptree_release(&mt
);
1228 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
1229 struct intel_mipmap_tree
*src
)
1234 intel_miptree_release(dst
);
1238 DBG("%s %p refcount now %d\n", __func__
, src
, src
->refcount
);
1245 intel_miptree_aux_buffer_free(struct intel_miptree_aux_buffer
*aux_buf
)
1247 if (aux_buf
== NULL
)
1250 brw_bo_unreference(aux_buf
->bo
);
1256 intel_miptree_release(struct intel_mipmap_tree
**mt
)
1261 DBG("%s %p refcount will be %d\n", __func__
, *mt
, (*mt
)->refcount
- 1);
1262 if (--(*mt
)->refcount
<= 0) {
1265 DBG("%s deleting %p\n", __func__
, *mt
);
1267 brw_bo_unreference((*mt
)->bo
);
1268 intel_miptree_release(&(*mt
)->stencil_mt
);
1269 intel_miptree_release(&(*mt
)->r8stencil_mt
);
1270 intel_miptree_aux_buffer_free((*mt
)->hiz_buf
);
1271 intel_miptree_aux_buffer_free((*mt
)->mcs_buf
);
1272 free_aux_state_map((*mt
)->aux_state
);
1274 intel_miptree_release(&(*mt
)->plane
[0]);
1275 intel_miptree_release(&(*mt
)->plane
[1]);
1277 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
1278 free((*mt
)->level
[i
].slice
);
1288 intel_get_image_dims(struct gl_texture_image
*image
,
1289 int *width
, int *height
, int *depth
)
1291 switch (image
->TexObject
->Target
) {
1292 case GL_TEXTURE_1D_ARRAY
:
1293 /* For a 1D Array texture the OpenGL API will treat the image height as
1294 * the number of array slices. For Intel hardware, we treat the 1D array
1295 * as a 2D Array with a height of 1. So, here we want to swap image
1298 assert(image
->Depth
== 1);
1299 *width
= image
->Width
;
1301 *depth
= image
->Height
;
1303 case GL_TEXTURE_CUBE_MAP
:
1304 /* For Cube maps, the mesa/main api layer gives us a depth of 1 even
1305 * though we really have 6 slices.
1307 assert(image
->Depth
== 1);
1308 *width
= image
->Width
;
1309 *height
= image
->Height
;
1313 *width
= image
->Width
;
1314 *height
= image
->Height
;
1315 *depth
= image
->Depth
;
1321 * Can the image be pulled into a unified mipmap tree? This mirrors
1322 * the completeness test in a lot of ways.
1324 * Not sure whether I want to pass gl_texture_image here.
1327 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
1328 struct gl_texture_image
*image
)
1330 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
1331 GLuint level
= intelImage
->base
.Base
.Level
;
1332 int width
, height
, depth
;
1334 /* glTexImage* choose the texture object based on the target passed in, and
1335 * objects can't change targets over their lifetimes, so this should be
1338 assert(image
->TexObject
->Target
== mt
->target
);
1340 mesa_format mt_format
= mt
->format
;
1341 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
1342 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
1343 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
1344 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
1345 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
1346 mt_format
= mt
->etc_format
;
1348 if (image
->TexFormat
!= mt_format
)
1351 intel_get_image_dims(image
, &width
, &height
, &depth
);
1353 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
1356 if (mt
->surf
.size
> 0) {
1357 if (level
>= mt
->surf
.levels
)
1360 const unsigned level_depth
=
1361 mt
->surf
.dim
== ISL_SURF_DIM_3D
?
1362 minify(mt
->surf
.logical_level0_px
.depth
, level
) :
1363 mt
->surf
.logical_level0_px
.array_len
;
1365 return width
== minify(mt
->surf
.logical_level0_px
.width
, level
) &&
1366 height
== minify(mt
->surf
.logical_level0_px
.height
, level
) &&
1367 depth
== level_depth
&&
1368 MAX2(image
->NumSamples
, 1) == mt
->surf
.samples
;
1371 int level_depth
= mt
->level
[level
].depth
;
1372 if (mt
->num_samples
> 1 && mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
)
1373 level_depth
/= mt
->num_samples
;
1375 /* Test image dimensions against the base level image adjusted for
1376 * minification. This will also catch images not present in the
1377 * tree, changed targets, etc.
1379 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
1380 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
1381 depth
!= level_depth
) {
1385 /* Core uses sample number of zero to indicate single-sampled. */
1386 if (MAX2(image
->NumSamples
, 1) != mt
->num_samples
)
1394 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
1396 GLuint x
, GLuint y
, GLuint d
)
1398 mt
->level
[level
].depth
= d
;
1399 mt
->level
[level
].level_x
= x
;
1400 mt
->level
[level
].level_y
= y
;
1402 DBG("%s level %d, depth %d, offset %d,%d\n", __func__
,
1405 assert(mt
->level
[level
].slice
);
1407 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
1408 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
1413 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
1414 GLuint level
, GLuint img
,
1417 if (img
== 0 && level
== 0)
1418 assert(x
== 0 && y
== 0);
1420 assert(img
< mt
->level
[level
].depth
);
1422 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
1423 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
1425 DBG("%s level %d img %d pos %d,%d\n",
1426 __func__
, level
, img
,
1427 mt
->level
[level
].slice
[img
].x_offset
,
1428 mt
->level
[level
].slice
[img
].y_offset
);
1432 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
1433 GLuint level
, GLuint slice
,
1434 GLuint
*x
, GLuint
*y
)
1436 if (mt
->surf
.size
> 0) {
1437 uint32_t x_offset_sa
, y_offset_sa
;
1439 /* Given level is relative to level zero while the miptree may be
1440 * represent just a subset of all levels starting from 'first_level'.
1442 assert(level
>= mt
->first_level
);
1443 level
-= mt
->first_level
;
1445 const unsigned z
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? slice
: 0;
1446 slice
= mt
->surf
.dim
== ISL_SURF_DIM_3D
? 0 : slice
;
1447 isl_surf_get_image_offset_sa(&mt
->surf
, level
, slice
, z
,
1448 &x_offset_sa
, &y_offset_sa
);
1455 assert(slice
< mt
->level
[level
].depth
);
1457 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
1458 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
1463 * This function computes the tile_w (in bytes) and tile_h (in rows) of
1464 * different tiling patterns. If the BO is untiled, tile_w is set to cpp
1465 * and tile_h is set to 1.
1468 intel_get_tile_dims(uint32_t tiling
, uint32_t cpp
,
1469 uint32_t *tile_w
, uint32_t *tile_h
)
1480 case I915_TILING_NONE
:
1485 unreachable("not reached");
1491 * This function computes masks that may be used to select the bits of the X
1492 * and Y coordinates that indicate the offset within a tile. If the BO is
1493 * untiled, the masks are set to 0.
1496 intel_get_tile_masks(uint32_t tiling
, uint32_t cpp
,
1497 uint32_t *mask_x
, uint32_t *mask_y
)
1499 uint32_t tile_w_bytes
, tile_h
;
1501 intel_get_tile_dims(tiling
, cpp
, &tile_w_bytes
, &tile_h
);
1503 *mask_x
= tile_w_bytes
/ cpp
- 1;
1504 *mask_y
= tile_h
- 1;
1508 * Compute the offset (in bytes) from the start of the BO to the given x
1509 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1510 * multiples of the tile size.
1513 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1514 uint32_t x
, uint32_t y
)
1517 uint32_t pitch
= mt
->pitch
;
1518 uint32_t tiling
= mt
->tiling
;
1522 unreachable("not reached");
1523 case I915_TILING_NONE
:
1524 return y
* pitch
+ x
* cpp
;
1526 assert((x
% (512 / cpp
)) == 0);
1527 assert((y
% 8) == 0);
1528 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1530 assert((x
% (128 / cpp
)) == 0);
1531 assert((y
% 32) == 0);
1532 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1537 * Rendering with tiled buffers requires that the base address of the buffer
1538 * be aligned to a page boundary. For renderbuffers, and sometimes with
1539 * textures, we may want the surface to point at a texture image level that
1540 * isn't at a page boundary.
1542 * This function returns an appropriately-aligned base offset
1543 * according to the tiling restrictions, plus any required x/y offset
1547 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1548 GLuint level
, GLuint slice
,
1553 uint32_t mask_x
, mask_y
;
1555 intel_get_tile_masks(mt
->tiling
, mt
->cpp
, &mask_x
, &mask_y
);
1556 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1558 *tile_x
= x
& mask_x
;
1559 *tile_y
= y
& mask_y
;
1561 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
);
1565 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1566 struct intel_mipmap_tree
*src_mt
,
1567 unsigned src_level
, unsigned src_layer
,
1568 struct intel_mipmap_tree
*dst_mt
,
1569 unsigned dst_level
, unsigned dst_layer
,
1570 unsigned width
, unsigned height
)
1573 ptrdiff_t src_stride
, dst_stride
;
1574 const unsigned cpp
= dst_mt
->surf
.size
> 0 ?
1575 (isl_format_get_layout(dst_mt
->surf
.format
)->bpb
/ 8) : dst_mt
->cpp
;
1577 intel_miptree_map(brw
, src_mt
,
1578 src_level
, src_layer
,
1581 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1584 intel_miptree_map(brw
, dst_mt
,
1585 dst_level
, dst_layer
,
1588 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1592 DBG("sw blit %s mt %p %p/%"PRIdPTR
" -> %s mt %p %p/%"PRIdPTR
" (%dx%d)\n",
1593 _mesa_get_format_name(src_mt
->format
),
1594 src_mt
, src
, src_stride
,
1595 _mesa_get_format_name(dst_mt
->format
),
1596 dst_mt
, dst
, dst_stride
,
1599 int row_size
= cpp
* width
;
1600 if (src_stride
== row_size
&&
1601 dst_stride
== row_size
) {
1602 memcpy(dst
, src
, row_size
* height
);
1604 for (int i
= 0; i
< height
; i
++) {
1605 memcpy(dst
, src
, row_size
);
1611 intel_miptree_unmap(brw
, dst_mt
, dst_level
, dst_layer
);
1612 intel_miptree_unmap(brw
, src_mt
, src_level
, src_layer
);
1614 /* Don't forget to copy the stencil data over, too. We could have skipped
1615 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1616 * shuffling the two data sources in/out of temporary storage instead of
1617 * the direct mapping we get this way.
1619 if (dst_mt
->stencil_mt
) {
1620 assert(src_mt
->stencil_mt
);
1621 intel_miptree_copy_slice_sw(brw
,
1622 src_mt
->stencil_mt
, src_level
, src_layer
,
1623 dst_mt
->stencil_mt
, dst_level
, dst_layer
,
1629 intel_miptree_copy_slice(struct brw_context
*brw
,
1630 struct intel_mipmap_tree
*src_mt
,
1631 unsigned src_level
, unsigned src_layer
,
1632 struct intel_mipmap_tree
*dst_mt
,
1633 unsigned dst_level
, unsigned dst_layer
)
1636 mesa_format format
= src_mt
->format
;
1637 uint32_t width
, height
;
1639 if (src_mt
->surf
.size
> 0) {
1640 width
= minify(src_mt
->surf
.phys_level0_sa
.width
,
1641 src_level
- src_mt
->first_level
);
1642 height
= minify(src_mt
->surf
.phys_level0_sa
.height
,
1643 src_level
- src_mt
->first_level
);
1645 if (src_mt
->surf
.dim
== ISL_SURF_DIM_3D
)
1646 assert(src_layer
< minify(src_mt
->surf
.phys_level0_sa
.depth
,
1647 src_level
- src_mt
->first_level
));
1649 assert(src_layer
< src_mt
->surf
.phys_level0_sa
.array_len
);
1651 width
= minify(src_mt
->physical_width0
,
1652 src_level
- src_mt
->first_level
);
1653 height
= minify(src_mt
->physical_height0
,
1654 src_level
- src_mt
->first_level
);
1655 assert(src_layer
< src_mt
->level
[src_level
].depth
);
1658 assert(src_mt
->format
== dst_mt
->format
);
1660 if (dst_mt
->compressed
) {
1662 _mesa_get_format_block_size(dst_mt
->format
, &i
, &j
);
1663 height
= ALIGN_NPOT(height
, j
) / j
;
1664 width
= ALIGN_NPOT(width
, i
) / i
;
1667 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1668 * below won't apply since we can't do the depth's Y tiling or the
1669 * stencil's W tiling in the blitter.
1671 if (src_mt
->stencil_mt
) {
1672 intel_miptree_copy_slice_sw(brw
,
1673 src_mt
, src_level
, src_layer
,
1674 dst_mt
, dst_level
, dst_layer
,
1679 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1680 intel_miptree_get_image_offset(dst_mt
, dst_level
, dst_layer
,
1682 intel_miptree_get_image_offset(src_mt
, src_level
, src_layer
,
1685 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1686 _mesa_get_format_name(src_mt
->format
),
1687 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1688 _mesa_get_format_name(dst_mt
->format
),
1689 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1692 if (!intel_miptree_blit(brw
,
1693 src_mt
, src_level
, src_layer
, 0, 0, false,
1694 dst_mt
, dst_level
, dst_layer
, 0, 0, false,
1695 width
, height
, GL_COPY
)) {
1696 perf_debug("miptree validate blit for %s failed\n",
1697 _mesa_get_format_name(format
));
1699 intel_miptree_copy_slice_sw(brw
,
1700 src_mt
, src_level
, src_layer
,
1701 dst_mt
, dst_level
, dst_layer
,
1707 * Copies the image's current data to the given miptree, and associates that
1708 * miptree with the image.
1710 * If \c invalidate is true, then the actual image data does not need to be
1711 * copied, but the image still needs to be associated to the new miptree (this
1712 * is set to true if we're about to clear the image).
1715 intel_miptree_copy_teximage(struct brw_context
*brw
,
1716 struct intel_texture_image
*intelImage
,
1717 struct intel_mipmap_tree
*dst_mt
,
1720 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1721 struct intel_texture_object
*intel_obj
=
1722 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1723 int level
= intelImage
->base
.Base
.Level
;
1724 const unsigned face
= intelImage
->base
.Base
.Face
;
1725 unsigned start_layer
, end_layer
;
1727 if (intel_obj
->base
.Target
== GL_TEXTURE_1D_ARRAY
) {
1729 assert(intelImage
->base
.Base
.Height
);
1731 end_layer
= intelImage
->base
.Base
.Height
- 1;
1732 } else if (face
> 0) {
1736 assert(intelImage
->base
.Base
.Depth
);
1738 end_layer
= intelImage
->base
.Base
.Depth
- 1;
1742 for (unsigned i
= start_layer
; i
<= end_layer
; i
++) {
1743 intel_miptree_copy_slice(brw
,
1749 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1750 intel_obj
->needs_validate
= true;
1754 intel_miptree_init_mcs(struct brw_context
*brw
,
1755 struct intel_mipmap_tree
*mt
,
1758 assert(mt
->mcs_buf
!= NULL
);
1760 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1762 * When MCS buffer is enabled and bound to MSRT, it is required that it
1763 * is cleared prior to any rendering.
1765 * Since we don't use the MCS buffer for any purpose other than rendering,
1766 * it makes sense to just clear it immediately upon allocation.
1768 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1770 void *map
= brw_bo_map(brw
, mt
->mcs_buf
->bo
, MAP_WRITE
);
1771 if (unlikely(map
== NULL
)) {
1772 fprintf(stderr
, "Failed to map mcs buffer into GTT\n");
1773 brw_bo_unreference(mt
->mcs_buf
->bo
);
1778 memset(data
, init_value
, mt
->mcs_buf
->size
);
1779 brw_bo_unmap(mt
->mcs_buf
->bo
);
1782 static struct intel_miptree_aux_buffer
*
1783 intel_alloc_aux_buffer(struct brw_context
*brw
,
1785 const struct isl_surf
*aux_surf
,
1786 uint32_t alloc_flags
,
1787 struct intel_mipmap_tree
*mt
)
1789 struct intel_miptree_aux_buffer
*buf
= calloc(sizeof(*buf
), 1);
1793 buf
->size
= aux_surf
->size
;
1794 buf
->pitch
= aux_surf
->row_pitch
;
1795 buf
->qpitch
= isl_surf_get_array_pitch_sa_rows(aux_surf
);
1797 /* ISL has stricter set of alignment rules then the drm allocator.
1798 * Therefore one can pass the ISL dimensions in terms of bytes instead of
1799 * trying to recalculate based on different format block sizes.
1801 buf
->bo
= brw_bo_alloc_tiled(brw
->bufmgr
, name
, buf
->size
,
1802 I915_TILING_Y
, buf
->pitch
, alloc_flags
);
1808 buf
->surf
= *aux_surf
;
1814 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1815 struct intel_mipmap_tree
*mt
,
1818 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1819 assert(mt
->mcs_buf
== NULL
);
1820 assert(mt
->aux_usage
== ISL_AUX_USAGE_MCS
);
1822 /* Multisampled miptrees are only supported for single level. */
1823 assert(mt
->first_level
== 0);
1824 enum isl_aux_state
**aux_state
=
1825 create_aux_state_map(mt
, ISL_AUX_STATE_CLEAR
);
1829 struct isl_surf temp_main_surf
;
1830 struct isl_surf temp_mcs_surf
;
1832 /* Create first an ISL presentation for the main color surface and let ISL
1833 * calculate equivalent MCS surface against it.
1835 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1836 MAYBE_UNUSED
bool ok
=
1837 isl_surf_get_mcs_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_mcs_surf
);
1840 /* Buffer needs to be initialised requiring the buffer to be immediately
1841 * mapped to cpu space for writing. Therefore do not use the gpu access
1842 * flag which can cause an unnecessary delay if the backing pages happened
1843 * to be just used by the GPU.
1845 const uint32_t alloc_flags
= 0;
1846 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "mcs-miptree",
1847 &temp_mcs_surf
, alloc_flags
, mt
);
1853 mt
->aux_state
= aux_state
;
1855 intel_miptree_init_mcs(brw
, mt
, 0xFF);
1861 intel_miptree_alloc_ccs(struct brw_context
*brw
,
1862 struct intel_mipmap_tree
*mt
)
1864 assert(mt
->mcs_buf
== NULL
);
1865 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1866 mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1868 struct isl_surf temp_main_surf
;
1869 struct isl_surf temp_ccs_surf
;
1871 /* Create first an ISL presentation for the main color surface and let ISL
1872 * calculate equivalent CCS surface against it.
1874 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1875 if (!isl_surf_get_ccs_surf(&brw
->isl_dev
, &temp_main_surf
,
1879 assert(temp_ccs_surf
.size
&&
1880 (temp_ccs_surf
.size
% temp_ccs_surf
.row_pitch
== 0));
1882 enum isl_aux_state
**aux_state
=
1883 create_aux_state_map(mt
, ISL_AUX_STATE_PASS_THROUGH
);
1887 /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
1888 * state. From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
1890 * "If Software wants to enable Color Compression without Fast clear,
1891 * Software needs to initialize MCS with zeros."
1893 * A CCS value of 0 indicates that the corresponding block is in the
1894 * pass-through state which is what we want.
1896 * For CCS_D, on the other hand, we don't care as we're about to perform a
1897 * fast-clear operation. In that case, being hot in caches more useful.
1899 const uint32_t alloc_flags
= mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
?
1900 BO_ALLOC_ZEROED
: BO_ALLOC_FOR_RENDER
;
1901 mt
->mcs_buf
= intel_alloc_aux_buffer(brw
, "ccs-miptree",
1902 &temp_ccs_surf
, alloc_flags
, mt
);
1908 mt
->aux_state
= aux_state
;
1914 * Helper for intel_miptree_alloc_hiz() that sets
1915 * \c mt->level[level].has_hiz. Return true if and only if
1916 * \c has_hiz was set.
1919 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1920 struct intel_mipmap_tree
*mt
,
1923 assert(mt
->hiz_buf
);
1925 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1926 uint32_t width
= minify(mt
->physical_width0
, level
);
1927 uint32_t height
= minify(mt
->physical_height0
, level
);
1929 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1930 * and the height is 4 aligned. This allows our HiZ support
1931 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1932 * we can grow the width & height to allow the HiZ op to
1933 * force the proper size alignments.
1935 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1936 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1941 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1942 mt
->level
[level
].has_hiz
= true;
1947 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1948 struct intel_mipmap_tree
*mt
)
1950 assert(mt
->hiz_buf
== NULL
);
1951 assert(mt
->aux_usage
== ISL_AUX_USAGE_HIZ
);
1953 enum isl_aux_state
**aux_state
=
1954 create_aux_state_map(mt
, ISL_AUX_STATE_AUX_INVALID
);
1958 struct isl_surf temp_main_surf
;
1959 struct isl_surf temp_hiz_surf
;
1961 intel_miptree_get_isl_surf(brw
, mt
, &temp_main_surf
);
1962 MAYBE_UNUSED
bool ok
=
1963 isl_surf_get_hiz_surf(&brw
->isl_dev
, &temp_main_surf
, &temp_hiz_surf
);
1966 const uint32_t alloc_flags
= BO_ALLOC_FOR_RENDER
;
1967 mt
->hiz_buf
= intel_alloc_aux_buffer(brw
, "hiz-miptree",
1968 &temp_hiz_surf
, alloc_flags
, mt
);
1975 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
)
1976 intel_miptree_level_enable_hiz(brw
, mt
, level
);
1978 mt
->aux_state
= aux_state
;
1985 * Allocate the initial aux surface for a miptree based on mt->aux_usage
1987 * Since MCS, HiZ, and CCS_E can compress more than just clear color, we
1988 * create the auxiliary surfaces up-front. CCS_D, on the other hand, can only
1989 * compress clear color so we wait until an actual fast-clear to allocate it.
1992 intel_miptree_alloc_aux(struct brw_context
*brw
,
1993 struct intel_mipmap_tree
*mt
)
1995 switch (mt
->aux_usage
) {
1996 case ISL_AUX_USAGE_NONE
:
1999 case ISL_AUX_USAGE_HIZ
:
2000 assert(!_mesa_is_format_color_format(mt
->format
));
2001 if (!intel_miptree_alloc_hiz(brw
, mt
))
2005 case ISL_AUX_USAGE_MCS
:
2006 assert(_mesa_is_format_color_format(mt
->format
));
2007 assert(mt
->num_samples
> 1);
2008 if (!intel_miptree_alloc_mcs(brw
, mt
, mt
->num_samples
))
2012 case ISL_AUX_USAGE_CCS_D
:
2013 /* Since CCS_D can only compress clear color so we wait until an actual
2014 * fast-clear to allocate it.
2018 case ISL_AUX_USAGE_CCS_E
:
2019 assert(_mesa_is_format_color_format(mt
->format
));
2020 assert(mt
->num_samples
== 1);
2021 if (!intel_miptree_alloc_ccs(brw
, mt
))
2026 unreachable("Invalid aux usage");
2031 * Can the miptree sample using the hiz buffer?
2034 intel_miptree_sample_with_hiz(struct brw_context
*brw
,
2035 struct intel_mipmap_tree
*mt
)
2037 /* It's unclear how well supported sampling from the hiz buffer is on GEN8,
2038 * so keep things conservative for now and never enable it unless we're SKL+.
2048 /* It seems the hardware won't fallback to the depth buffer if some of the
2049 * mipmap levels aren't available in the HiZ buffer. So we need all levels
2050 * of the texture to be HiZ enabled.
2052 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
2053 if (!intel_miptree_level_has_hiz(mt
, level
))
2057 /* If compressed multisampling is enabled, then we use it for the auxiliary
2060 * From the BDW PRM (Volume 2d: Command Reference: Structures
2061 * RENDER_SURFACE_STATE.AuxiliarySurfaceMode):
2063 * "If this field is set to AUX_HIZ, Number of Multisamples must be
2064 * MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D.
2066 * There is no such blurb for 1D textures, but there is sufficient evidence
2067 * that this is broken on SKL+.
2069 return (mt
->num_samples
== 1 &&
2070 mt
->target
!= GL_TEXTURE_3D
&&
2071 mt
->target
!= GL_TEXTURE_1D
/* gen9+ restriction */);
2075 * Does the miptree slice have hiz enabled?
2078 intel_miptree_level_has_hiz(const struct intel_mipmap_tree
*mt
, uint32_t level
)
2080 intel_miptree_check_level_layer(mt
, level
, 0);
2081 return mt
->level
[level
].has_hiz
;
2085 intel_miptree_has_color_unresolved(const struct intel_mipmap_tree
*mt
,
2086 unsigned start_level
, unsigned num_levels
,
2087 unsigned start_layer
, unsigned num_layers
)
2089 assert(_mesa_is_format_color_format(mt
->format
));
2094 /* Clamp the level range to fit the miptree */
2095 assert(start_level
+ num_levels
>= start_level
);
2096 const uint32_t last_level
=
2097 MIN2(mt
->last_level
, start_level
+ num_levels
- 1);
2098 start_level
= MAX2(mt
->first_level
, start_level
);
2099 num_levels
= last_level
- start_level
+ 1;
2101 for (uint32_t level
= start_level
; level
<= last_level
; level
++) {
2102 const uint32_t level_layers
= MIN2(num_layers
, mt
->level
[level
].depth
);
2103 for (unsigned a
= 0; a
< level_layers
; a
++) {
2104 enum isl_aux_state aux_state
=
2105 intel_miptree_get_aux_state(mt
, level
, start_layer
+ a
);
2106 assert(aux_state
!= ISL_AUX_STATE_AUX_INVALID
);
2107 if (aux_state
!= ISL_AUX_STATE_PASS_THROUGH
)
2116 intel_miptree_check_color_resolve(const struct brw_context
*brw
,
2117 const struct intel_mipmap_tree
*mt
,
2118 unsigned level
, unsigned layer
)
2124 /* Fast color clear is supported for mipmapped surfaces only on Gen8+. */
2125 assert(brw
->gen
>= 8 ||
2126 (level
== 0 && mt
->first_level
== 0 && mt
->last_level
== 0));
2128 /* Compression of arrayed msaa surfaces is supported. */
2129 if (mt
->num_samples
> 1)
2132 /* Fast color clear is supported for non-msaa arrays only on Gen8+. */
2133 assert(brw
->gen
>= 8 || (layer
== 0 && mt
->logical_depth0
== 1));
2139 static enum blorp_fast_clear_op
2140 get_ccs_d_resolve_op(enum isl_aux_state aux_state
,
2141 bool ccs_supported
, bool fast_clear_supported
)
2143 assert(ccs_supported
== fast_clear_supported
);
2145 switch (aux_state
) {
2146 case ISL_AUX_STATE_CLEAR
:
2147 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2149 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2151 return BLORP_FAST_CLEAR_OP_NONE
;
2153 case ISL_AUX_STATE_PASS_THROUGH
:
2154 return BLORP_FAST_CLEAR_OP_NONE
;
2156 case ISL_AUX_STATE_RESOLVED
:
2157 case ISL_AUX_STATE_AUX_INVALID
:
2158 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2162 unreachable("Invalid aux state for CCS_D");
2165 static enum blorp_fast_clear_op
2166 get_ccs_e_resolve_op(enum isl_aux_state aux_state
,
2167 bool ccs_supported
, bool fast_clear_supported
)
2169 switch (aux_state
) {
2170 case ISL_AUX_STATE_CLEAR
:
2171 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2173 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2174 else if (!fast_clear_supported
)
2175 return BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
2177 return BLORP_FAST_CLEAR_OP_NONE
;
2179 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2181 return BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
2183 return BLORP_FAST_CLEAR_OP_NONE
;
2185 case ISL_AUX_STATE_PASS_THROUGH
:
2186 return BLORP_FAST_CLEAR_OP_NONE
;
2188 case ISL_AUX_STATE_RESOLVED
:
2189 case ISL_AUX_STATE_AUX_INVALID
:
2193 unreachable("Invalid aux state for CCS_E");
2197 intel_miptree_prepare_ccs_access(struct brw_context
*brw
,
2198 struct intel_mipmap_tree
*mt
,
2199 uint32_t level
, uint32_t layer
,
2201 bool fast_clear_supported
)
2203 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2205 enum blorp_fast_clear_op resolve_op
;
2206 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2207 resolve_op
= get_ccs_e_resolve_op(aux_state
, aux_supported
,
2208 fast_clear_supported
);
2210 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2211 resolve_op
= get_ccs_d_resolve_op(aux_state
, aux_supported
,
2212 fast_clear_supported
);
2215 if (resolve_op
!= BLORP_FAST_CLEAR_OP_NONE
) {
2216 intel_miptree_check_color_resolve(brw
, mt
, level
, layer
);
2217 brw_blorp_resolve_color(brw
, mt
, level
, layer
, resolve_op
);
2219 switch (resolve_op
) {
2220 case BLORP_FAST_CLEAR_OP_RESOLVE_FULL
:
2221 /* The CCS full resolve operation destroys the CCS and sets it to the
2222 * pass-through state. (You can also think of this as being both a
2223 * resolve and an ambiguate in one operation.)
2225 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2226 ISL_AUX_STATE_PASS_THROUGH
);
2229 case BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
:
2230 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2231 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2235 unreachable("Invalid resolve op");
2241 intel_miptree_finish_ccs_write(struct brw_context
*brw
,
2242 struct intel_mipmap_tree
*mt
,
2243 uint32_t level
, uint32_t layer
,
2244 bool written_with_ccs
)
2246 enum isl_aux_state aux_state
= intel_miptree_get_aux_state(mt
, level
, layer
);
2248 if (mt
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
2249 switch (aux_state
) {
2250 case ISL_AUX_STATE_CLEAR
:
2251 assert(written_with_ccs
);
2252 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2253 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2256 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2257 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2258 assert(written_with_ccs
);
2259 break; /* Nothing to do */
2261 case ISL_AUX_STATE_PASS_THROUGH
:
2262 if (written_with_ccs
) {
2263 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2264 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2270 case ISL_AUX_STATE_RESOLVED
:
2271 case ISL_AUX_STATE_AUX_INVALID
:
2272 unreachable("Invalid aux state for CCS_E");
2275 assert(mt
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
2276 /* CCS_D is a bit simpler */
2277 switch (aux_state
) {
2278 case ISL_AUX_STATE_CLEAR
:
2279 assert(written_with_ccs
);
2280 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2281 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2284 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2285 assert(written_with_ccs
);
2286 break; /* Nothing to do */
2288 case ISL_AUX_STATE_PASS_THROUGH
:
2292 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2293 case ISL_AUX_STATE_RESOLVED
:
2294 case ISL_AUX_STATE_AUX_INVALID
:
2295 unreachable("Invalid aux state for CCS_D");
2301 intel_miptree_finish_mcs_write(struct brw_context
*brw
,
2302 struct intel_mipmap_tree
*mt
,
2303 uint32_t level
, uint32_t layer
,
2304 bool written_with_aux
)
2306 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2307 case ISL_AUX_STATE_CLEAR
:
2308 assert(written_with_aux
);
2309 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2310 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2313 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2314 assert(written_with_aux
);
2315 break; /* Nothing to do */
2317 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2318 case ISL_AUX_STATE_RESOLVED
:
2319 case ISL_AUX_STATE_PASS_THROUGH
:
2320 case ISL_AUX_STATE_AUX_INVALID
:
2321 unreachable("Invalid aux state for MCS");
2326 intel_miptree_prepare_hiz_access(struct brw_context
*brw
,
2327 struct intel_mipmap_tree
*mt
,
2328 uint32_t level
, uint32_t layer
,
2329 bool hiz_supported
, bool fast_clear_supported
)
2331 enum blorp_hiz_op hiz_op
= BLORP_HIZ_OP_NONE
;
2332 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2333 case ISL_AUX_STATE_CLEAR
:
2334 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2335 if (!hiz_supported
|| !fast_clear_supported
)
2336 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2339 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2341 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
2344 case ISL_AUX_STATE_PASS_THROUGH
:
2345 case ISL_AUX_STATE_RESOLVED
:
2348 case ISL_AUX_STATE_AUX_INVALID
:
2350 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
2354 if (hiz_op
!= BLORP_HIZ_OP_NONE
) {
2355 intel_hiz_exec(brw
, mt
, level
, layer
, 1, hiz_op
);
2358 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
2359 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2360 ISL_AUX_STATE_RESOLVED
);
2363 case BLORP_HIZ_OP_HIZ_RESOLVE
:
2364 /* The HiZ resolve operation is actually an ambiguate */
2365 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2366 ISL_AUX_STATE_PASS_THROUGH
);
2370 unreachable("Invalid HiZ op");
2376 intel_miptree_finish_hiz_write(struct brw_context
*brw
,
2377 struct intel_mipmap_tree
*mt
,
2378 uint32_t level
, uint32_t layer
,
2379 bool written_with_hiz
)
2381 switch (intel_miptree_get_aux_state(mt
, level
, layer
)) {
2382 case ISL_AUX_STATE_CLEAR
:
2383 assert(written_with_hiz
);
2384 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2385 ISL_AUX_STATE_COMPRESSED_CLEAR
);
2388 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR
:
2389 case ISL_AUX_STATE_COMPRESSED_CLEAR
:
2390 assert(written_with_hiz
);
2391 break; /* Nothing to do */
2393 case ISL_AUX_STATE_RESOLVED
:
2394 if (written_with_hiz
) {
2395 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2396 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2398 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2399 ISL_AUX_STATE_AUX_INVALID
);
2403 case ISL_AUX_STATE_PASS_THROUGH
:
2404 if (written_with_hiz
) {
2405 intel_miptree_set_aux_state(brw
, mt
, level
, layer
, 1,
2406 ISL_AUX_STATE_COMPRESSED_NO_CLEAR
);
2410 case ISL_AUX_STATE_AUX_INVALID
:
2411 assert(!written_with_hiz
);
2416 static inline uint32_t
2417 miptree_level_range_length(const struct intel_mipmap_tree
*mt
,
2418 uint32_t start_level
, uint32_t num_levels
)
2420 assert(start_level
>= mt
->first_level
);
2421 assert(start_level
<= mt
->last_level
);
2423 if (num_levels
== INTEL_REMAINING_LAYERS
)
2424 num_levels
= mt
->last_level
- start_level
+ 1;
2425 /* Check for overflow */
2426 assert(start_level
+ num_levels
>= start_level
);
2427 assert(start_level
+ num_levels
<= mt
->last_level
+ 1);
2432 static inline uint32_t
2433 miptree_layer_range_length(const struct intel_mipmap_tree
*mt
, uint32_t level
,
2434 uint32_t start_layer
, uint32_t num_layers
)
2436 assert(level
<= mt
->last_level
);
2437 uint32_t total_num_layers
;
2439 if (mt
->surf
.size
> 0)
2440 total_num_layers
= mt
->surf
.dim
== ISL_SURF_DIM_3D
?
2441 minify(mt
->surf
.phys_level0_sa
.depth
, level
) :
2442 mt
->surf
.phys_level0_sa
.array_len
;
2444 total_num_layers
= mt
->level
[level
].depth
;
2446 assert(start_layer
< total_num_layers
);
2447 if (num_layers
== INTEL_REMAINING_LAYERS
)
2448 num_layers
= total_num_layers
- start_layer
;
2449 /* Check for overflow */
2450 assert(start_layer
+ num_layers
>= start_layer
);
2451 assert(start_layer
+ num_layers
<= total_num_layers
);
2457 intel_miptree_prepare_access(struct brw_context
*brw
,
2458 struct intel_mipmap_tree
*mt
,
2459 uint32_t start_level
, uint32_t num_levels
,
2460 uint32_t start_layer
, uint32_t num_layers
,
2461 bool aux_supported
, bool fast_clear_supported
)
2463 num_levels
= miptree_level_range_length(mt
, start_level
, num_levels
);
2465 if (_mesa_is_format_color_format(mt
->format
)) {
2469 if (mt
->num_samples
> 1) {
2470 /* Nothing to do for MSAA */
2471 assert(aux_supported
&& fast_clear_supported
);
2473 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2474 const uint32_t level
= start_level
+ l
;
2475 const uint32_t level_layers
=
2476 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2477 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2478 intel_miptree_prepare_ccs_access(brw
, mt
, level
,
2479 start_layer
+ a
, aux_supported
,
2480 fast_clear_supported
);
2484 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2485 /* Nothing to do for stencil */
2490 for (uint32_t l
= 0; l
< num_levels
; l
++) {
2491 const uint32_t level
= start_level
+ l
;
2492 if (!intel_miptree_level_has_hiz(mt
, level
))
2495 const uint32_t level_layers
=
2496 miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2497 for (uint32_t a
= 0; a
< level_layers
; a
++) {
2498 intel_miptree_prepare_hiz_access(brw
, mt
, level
, start_layer
+ a
,
2500 fast_clear_supported
);
2507 intel_miptree_finish_write(struct brw_context
*brw
,
2508 struct intel_mipmap_tree
*mt
, uint32_t level
,
2509 uint32_t start_layer
, uint32_t num_layers
,
2510 bool written_with_aux
)
2512 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2514 if (_mesa_is_format_color_format(mt
->format
)) {
2518 if (mt
->num_samples
> 1) {
2519 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2520 intel_miptree_finish_mcs_write(brw
, mt
, level
, start_layer
+ a
,
2524 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2525 intel_miptree_finish_ccs_write(brw
, mt
, level
, start_layer
+ a
,
2529 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2530 /* Nothing to do for stencil */
2532 if (!intel_miptree_level_has_hiz(mt
, level
))
2535 for (uint32_t a
= 0; a
< num_layers
; a
++) {
2536 intel_miptree_finish_hiz_write(brw
, mt
, level
, start_layer
+ a
,
2543 intel_miptree_get_aux_state(const struct intel_mipmap_tree
*mt
,
2544 uint32_t level
, uint32_t layer
)
2546 intel_miptree_check_level_layer(mt
, level
, layer
);
2548 if (_mesa_is_format_color_format(mt
->format
)) {
2549 assert(mt
->mcs_buf
!= NULL
);
2550 assert(mt
->num_samples
== 1 ||
2551 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2552 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2553 unreachable("Cannot get aux state for stencil");
2555 assert(intel_miptree_level_has_hiz(mt
, level
));
2558 return mt
->aux_state
[level
][layer
];
2562 intel_miptree_set_aux_state(struct brw_context
*brw
,
2563 struct intel_mipmap_tree
*mt
, uint32_t level
,
2564 uint32_t start_layer
, uint32_t num_layers
,
2565 enum isl_aux_state aux_state
)
2567 num_layers
= miptree_layer_range_length(mt
, level
, start_layer
, num_layers
);
2569 if (_mesa_is_format_color_format(mt
->format
)) {
2570 assert(mt
->mcs_buf
!= NULL
);
2571 assert(mt
->num_samples
== 1 ||
2572 mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_ARRAY
);
2573 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2574 unreachable("Cannot get aux state for stencil");
2576 assert(intel_miptree_level_has_hiz(mt
, level
));
2579 for (unsigned a
= 0; a
< num_layers
; a
++)
2580 mt
->aux_state
[level
][start_layer
+ a
] = aux_state
;
2583 /* On Gen9 color buffers may be compressed by the hardware (lossless
2584 * compression). There are, however, format restrictions and care needs to be
2585 * taken that the sampler engine is capable for re-interpreting a buffer with
2586 * format different the buffer was originally written with.
2588 * For example, SRGB formats are not compressible and the sampler engine isn't
2589 * capable of treating RGBA_UNORM as SRGB_ALPHA. In such a case the underlying
2590 * color buffer needs to be resolved so that the sampling surface can be
2591 * sampled as non-compressed (i.e., without the auxiliary MCS buffer being
2595 can_texture_with_ccs(struct brw_context
*brw
,
2596 struct intel_mipmap_tree
*mt
,
2597 mesa_format view_format
)
2599 if (mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
2602 enum isl_format isl_mt_format
= brw_isl_format_for_mesa_format(mt
->format
);
2603 enum isl_format isl_view_format
= brw_isl_format_for_mesa_format(view_format
);
2605 if (!isl_formats_are_ccs_e_compatible(&brw
->screen
->devinfo
,
2606 isl_mt_format
, isl_view_format
)) {
2607 perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
2608 _mesa_get_format_name(view_format
),
2609 _mesa_get_format_name(mt
->format
));
2617 intel_miptree_prepare_texture_slices(struct brw_context
*brw
,
2618 struct intel_mipmap_tree
*mt
,
2619 mesa_format view_format
,
2620 uint32_t start_level
, uint32_t num_levels
,
2621 uint32_t start_layer
, uint32_t num_layers
,
2622 bool *aux_supported_out
)
2624 bool aux_supported
, clear_supported
;
2625 if (_mesa_is_format_color_format(mt
->format
)) {
2626 if (mt
->num_samples
> 1) {
2627 aux_supported
= clear_supported
= true;
2629 aux_supported
= can_texture_with_ccs(brw
, mt
, view_format
);
2631 /* Clear color is specified as ints or floats and the conversion is
2632 * done by the sampler. If we have a texture view, we would have to
2633 * perform the clear color conversion manually. Just disable clear
2636 clear_supported
= aux_supported
&& (mt
->format
== view_format
);
2638 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2639 aux_supported
= clear_supported
= false;
2641 aux_supported
= clear_supported
= intel_miptree_sample_with_hiz(brw
, mt
);
2644 intel_miptree_prepare_access(brw
, mt
, start_level
, num_levels
,
2645 start_layer
, num_layers
,
2646 aux_supported
, clear_supported
);
2647 if (aux_supported_out
)
2648 *aux_supported_out
= aux_supported
;
2652 intel_miptree_prepare_texture(struct brw_context
*brw
,
2653 struct intel_mipmap_tree
*mt
,
2654 mesa_format view_format
,
2655 bool *aux_supported_out
)
2657 intel_miptree_prepare_texture_slices(brw
, mt
, view_format
,
2658 0, INTEL_REMAINING_LEVELS
,
2659 0, INTEL_REMAINING_LAYERS
,
2664 intel_miptree_prepare_image(struct brw_context
*brw
,
2665 struct intel_mipmap_tree
*mt
)
2667 /* The data port doesn't understand any compression */
2668 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2669 0, INTEL_REMAINING_LAYERS
, false, false);
2673 intel_miptree_prepare_fb_fetch(struct brw_context
*brw
,
2674 struct intel_mipmap_tree
*mt
, uint32_t level
,
2675 uint32_t start_layer
, uint32_t num_layers
)
2677 intel_miptree_prepare_texture_slices(brw
, mt
, mt
->format
, level
, 1,
2678 start_layer
, num_layers
, NULL
);
2682 intel_miptree_prepare_render(struct brw_context
*brw
,
2683 struct intel_mipmap_tree
*mt
, uint32_t level
,
2684 uint32_t start_layer
, uint32_t layer_count
,
2687 /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
2688 * the single-sampled color renderbuffers because the CCS buffer isn't
2689 * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
2690 * enabled because otherwise the surface state will be programmed with
2691 * the linear equivalent format anyway.
2693 if (brw
->gen
== 9 && srgb_enabled
&& mt
->num_samples
== 1 &&
2694 _mesa_get_srgb_format_linear(mt
->format
) != mt
->format
) {
2696 /* Lossless compression is not supported for SRGB formats, it
2697 * should be impossible to get here with such surfaces.
2699 assert(mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
);
2700 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2706 intel_miptree_finish_render(struct brw_context
*brw
,
2707 struct intel_mipmap_tree
*mt
, uint32_t level
,
2708 uint32_t start_layer
, uint32_t layer_count
)
2710 assert(_mesa_is_format_color_format(mt
->format
));
2711 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2712 mt
->mcs_buf
!= NULL
);
2716 intel_miptree_prepare_depth(struct brw_context
*brw
,
2717 struct intel_mipmap_tree
*mt
, uint32_t level
,
2718 uint32_t start_layer
, uint32_t layer_count
)
2720 intel_miptree_prepare_access(brw
, mt
, level
, 1, start_layer
, layer_count
,
2721 mt
->hiz_buf
!= NULL
, mt
->hiz_buf
!= NULL
);
2725 intel_miptree_finish_depth(struct brw_context
*brw
,
2726 struct intel_mipmap_tree
*mt
, uint32_t level
,
2727 uint32_t start_layer
, uint32_t layer_count
,
2730 if (depth_written
) {
2731 intel_miptree_finish_write(brw
, mt
, level
, start_layer
, layer_count
,
2732 mt
->hiz_buf
!= NULL
);
2737 * Make it possible to share the BO backing the given miptree with another
2738 * process or another miptree.
2740 * Fast color clears are unsafe with shared buffers, so we need to resolve and
2741 * then discard the MCS buffer, if present. We also set the no_ccs flag to
2742 * ensure that no MCS buffer gets allocated in the future.
2744 * HiZ is similarly unsafe with shared buffers.
2747 intel_miptree_make_shareable(struct brw_context
*brw
,
2748 struct intel_mipmap_tree
*mt
)
2750 /* MCS buffers are also used for multisample buffers, but we can't resolve
2751 * away a multisample MCS buffer because it's an integral part of how the
2752 * pixel data is stored. Fortunately this code path should never be
2753 * reached for multisample buffers.
2755 assert(mt
->surf
.msaa_layout
== ISL_MSAA_LAYOUT_NONE
||
2756 mt
->num_samples
== 1);
2758 intel_miptree_prepare_access(brw
, mt
, 0, INTEL_REMAINING_LEVELS
,
2759 0, INTEL_REMAINING_LAYERS
, false, false);
2762 brw_bo_unreference(mt
->mcs_buf
->bo
);
2766 /* Any pending MCS/CCS operations are no longer needed. Trying to
2767 * execute any will likely crash due to the missing aux buffer. So let's
2768 * delete all pending ops.
2770 free(mt
->aux_state
);
2771 mt
->aux_state
= NULL
;
2775 intel_miptree_aux_buffer_free(mt
->hiz_buf
);
2778 for (uint32_t l
= mt
->first_level
; l
<= mt
->last_level
; ++l
) {
2779 mt
->level
[l
].has_hiz
= false;
2782 /* Any pending HiZ operations are no longer needed. Trying to execute
2783 * any will likely crash due to the missing aux buffer. So let's delete
2786 free(mt
->aux_state
);
2787 mt
->aux_state
= NULL
;
2790 mt
->aux_usage
= ISL_AUX_USAGE_NONE
;
2795 * \brief Get pointer offset into stencil buffer.
2797 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
2798 * must decode the tile's layout in software.
2801 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
2803 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
2805 * Even though the returned offset is always positive, the return type is
2807 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
2808 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
2811 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
2813 uint32_t tile_size
= 4096;
2814 uint32_t tile_width
= 64;
2815 uint32_t tile_height
= 64;
2816 uint32_t row_size
= 64 * stride
;
2818 uint32_t tile_x
= x
/ tile_width
;
2819 uint32_t tile_y
= y
/ tile_height
;
2821 /* The byte's address relative to the tile's base addres. */
2822 uint32_t byte_x
= x
% tile_width
;
2823 uint32_t byte_y
= y
% tile_height
;
2825 uintptr_t u
= tile_y
* row_size
2826 + tile_x
* tile_size
2827 + 512 * (byte_x
/ 8)
2829 + 32 * ((byte_y
/ 4) % 2)
2830 + 16 * ((byte_x
/ 4) % 2)
2831 + 8 * ((byte_y
/ 2) % 2)
2832 + 4 * ((byte_x
/ 2) % 2)
2837 /* adjust for bit6 swizzling */
2838 if (((byte_x
/ 8) % 2) == 1) {
2839 if (((byte_y
/ 8) % 2) == 0) {
2851 intel_miptree_updownsample(struct brw_context
*brw
,
2852 struct intel_mipmap_tree
*src
,
2853 struct intel_mipmap_tree
*dst
)
2855 unsigned src_w
, src_h
, dst_w
, dst_h
;
2857 if (src
->surf
.size
> 0) {
2858 src_w
= src
->surf
.logical_level0_px
.width
;
2859 src_h
= src
->surf
.logical_level0_px
.height
;
2861 src_w
= src
->logical_width0
;
2862 src_h
= src
->logical_height0
;
2865 if (dst
->surf
.size
> 0) {
2866 dst_w
= dst
->surf
.logical_level0_px
.width
;
2867 dst_h
= dst
->surf
.logical_level0_px
.height
;
2869 dst_w
= dst
->logical_width0
;
2870 dst_h
= dst
->logical_height0
;
2873 brw_blorp_blit_miptrees(brw
,
2874 src
, 0 /* level */, 0 /* layer */,
2875 src
->format
, SWIZZLE_XYZW
,
2876 dst
, 0 /* level */, 0 /* layer */, dst
->format
,
2879 GL_NEAREST
, false, false /*mirror x, y*/,
2882 if (src
->stencil_mt
) {
2883 if (src
->stencil_mt
->surf
.size
> 0) {
2884 src_w
= src
->stencil_mt
->surf
.logical_level0_px
.width
;
2885 src_h
= src
->stencil_mt
->surf
.logical_level0_px
.height
;
2887 src_w
= src
->stencil_mt
->logical_width0
;
2888 src_h
= src
->stencil_mt
->logical_height0
;
2891 if (dst
->stencil_mt
->surf
.size
> 0) {
2892 dst_w
= dst
->stencil_mt
->surf
.logical_level0_px
.width
;
2893 dst_h
= dst
->stencil_mt
->surf
.logical_level0_px
.height
;
2895 dst_w
= dst
->stencil_mt
->logical_width0
;
2896 dst_h
= dst
->stencil_mt
->logical_height0
;
2899 brw_blorp_blit_miptrees(brw
,
2900 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
2901 src
->stencil_mt
->format
, SWIZZLE_XYZW
,
2902 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
2903 dst
->stencil_mt
->format
,
2906 GL_NEAREST
, false, false /*mirror x, y*/,
2907 false, false /* decode/encode srgb */);
2912 intel_update_r8stencil(struct brw_context
*brw
,
2913 struct intel_mipmap_tree
*mt
)
2915 assert(brw
->gen
>= 7);
2916 struct intel_mipmap_tree
*src
=
2917 mt
->format
== MESA_FORMAT_S_UINT8
? mt
: mt
->stencil_mt
;
2918 if (!src
|| brw
->gen
>= 8 || !src
->r8stencil_needs_update
)
2921 if (!mt
->r8stencil_mt
) {
2922 const uint32_t r8stencil_flags
=
2923 MIPTREE_LAYOUT_ACCELERATED_UPLOAD
| MIPTREE_LAYOUT_TILING_Y
|
2924 MIPTREE_LAYOUT_DISABLE_AUX
;
2925 assert(brw
->gen
> 6); /* Handle MIPTREE_LAYOUT_GEN6_HIZ_STENCIL */
2926 mt
->r8stencil_mt
= intel_miptree_create(brw
,
2928 MESA_FORMAT_R_UINT8
,
2931 src
->logical_width0
,
2932 src
->logical_height0
,
2933 src
->logical_depth0
,
2936 assert(mt
->r8stencil_mt
);
2939 struct intel_mipmap_tree
*dst
= mt
->r8stencil_mt
;
2941 for (int level
= src
->first_level
; level
<= src
->last_level
; level
++) {
2942 const unsigned depth
= src
->level
[level
].depth
;
2944 for (unsigned layer
= 0; layer
< depth
; layer
++) {
2945 brw_blorp_copy_miptrees(brw
,
2949 minify(src
->logical_width0
, level
),
2950 minify(src
->logical_height0
, level
));
2954 brw_render_cache_set_check_flush(brw
, dst
->bo
);
2955 src
->r8stencil_needs_update
= false;
2959 intel_miptree_map_raw(struct brw_context
*brw
,
2960 struct intel_mipmap_tree
*mt
,
2963 struct brw_bo
*bo
= mt
->bo
;
2965 if (brw_batch_references(&brw
->batch
, bo
))
2966 intel_batchbuffer_flush(brw
);
2968 return brw_bo_map(brw
, bo
, mode
);
2972 intel_miptree_unmap_raw(struct intel_mipmap_tree
*mt
)
2974 brw_bo_unmap(mt
->bo
);
2978 intel_miptree_map_gtt(struct brw_context
*brw
,
2979 struct intel_mipmap_tree
*mt
,
2980 struct intel_miptree_map
*map
,
2981 unsigned int level
, unsigned int slice
)
2983 unsigned int bw
, bh
;
2985 unsigned int image_x
, image_y
;
2986 intptr_t x
= map
->x
;
2987 intptr_t y
= map
->y
;
2989 /* For compressed formats, the stride is the number of bytes per
2990 * row of blocks. intel_miptree_get_image_offset() already does
2993 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
2994 assert(y
% bh
== 0);
2995 assert(x
% bw
== 0);
2999 base
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3006 /* Note that in the case of cube maps, the caller must have passed the
3007 * slice number referencing the face.
3009 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3013 map
->stride
= mt
->pitch
;
3014 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
3017 DBG("%s: %d,%d %dx%d from mt %p (%s) "
3018 "%"PRIiPTR
",%"PRIiPTR
" = %p/%d\n", __func__
,
3019 map
->x
, map
->y
, map
->w
, map
->h
,
3020 mt
, _mesa_get_format_name(mt
->format
),
3021 x
, y
, map
->ptr
, map
->stride
);
3025 intel_miptree_unmap_gtt(struct intel_mipmap_tree
*mt
)
3027 intel_miptree_unmap_raw(mt
);
3031 intel_miptree_map_blit(struct brw_context
*brw
,
3032 struct intel_mipmap_tree
*mt
,
3033 struct intel_miptree_map
*map
,
3034 unsigned int level
, unsigned int slice
)
3036 map
->linear_mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
3037 /* first_level */ 0,
3041 MIPTREE_LAYOUT_TILING_NONE
);
3043 if (!map
->linear_mt
) {
3044 fprintf(stderr
, "Failed to allocate blit temporary\n");
3047 map
->stride
= map
->linear_mt
->pitch
;
3049 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3050 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3051 * invalidate is set, since we'll be writing the whole rectangle from our
3052 * temporary buffer back out.
3054 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3055 if (!intel_miptree_copy(brw
,
3056 mt
, level
, slice
, map
->x
, map
->y
,
3057 map
->linear_mt
, 0, 0, 0, 0,
3059 fprintf(stderr
, "Failed to blit\n");
3064 map
->ptr
= intel_miptree_map_raw(brw
, map
->linear_mt
, map
->mode
);
3066 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3067 map
->x
, map
->y
, map
->w
, map
->h
,
3068 mt
, _mesa_get_format_name(mt
->format
),
3069 level
, slice
, map
->ptr
, map
->stride
);
3074 intel_miptree_release(&map
->linear_mt
);
3080 intel_miptree_unmap_blit(struct brw_context
*brw
,
3081 struct intel_mipmap_tree
*mt
,
3082 struct intel_miptree_map
*map
,
3086 struct gl_context
*ctx
= &brw
->ctx
;
3088 intel_miptree_unmap_raw(map
->linear_mt
);
3090 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3091 bool ok
= intel_miptree_copy(brw
,
3092 map
->linear_mt
, 0, 0, 0, 0,
3093 mt
, level
, slice
, map
->x
, map
->y
,
3095 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
3098 intel_miptree_release(&map
->linear_mt
);
3102 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
3104 #if defined(USE_SSE41)
3106 intel_miptree_map_movntdqa(struct brw_context
*brw
,
3107 struct intel_mipmap_tree
*mt
,
3108 struct intel_miptree_map
*map
,
3109 unsigned int level
, unsigned int slice
)
3111 assert(map
->mode
& GL_MAP_READ_BIT
);
3112 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
3114 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __func__
,
3115 map
->x
, map
->y
, map
->w
, map
->h
,
3116 mt
, _mesa_get_format_name(mt
->format
),
3117 level
, slice
, map
->ptr
, map
->stride
);
3119 /* Map the original image */
3122 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3126 void *src
= intel_miptree_map_raw(brw
, mt
, map
->mode
);
3132 src
+= image_y
* mt
->pitch
;
3133 src
+= image_x
* mt
->cpp
;
3135 /* Due to the pixel offsets for the particular image being mapped, our
3136 * src pointer may not be 16-byte aligned. However, if the pitch is
3137 * divisible by 16, then the amount by which it's misaligned will remain
3138 * consistent from row to row.
3140 assert((mt
->pitch
% 16) == 0);
3141 const int misalignment
= ((uintptr_t) src
) & 15;
3143 /* Create an untiled temporary buffer for the mapping. */
3144 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
3146 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
3148 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
3149 /* Offset the destination so it has the same misalignment as src. */
3150 map
->ptr
= map
->buffer
+ misalignment
;
3152 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
3154 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3155 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
3156 void *src_ptr
= src
+ y
* mt
->pitch
;
3158 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
3161 intel_miptree_unmap_raw(mt
);
3165 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
3166 struct intel_mipmap_tree
*mt
,
3167 struct intel_miptree_map
*map
,
3171 _mesa_align_free(map
->buffer
);
3178 intel_miptree_map_s8(struct brw_context
*brw
,
3179 struct intel_mipmap_tree
*mt
,
3180 struct intel_miptree_map
*map
,
3181 unsigned int level
, unsigned int slice
)
3183 map
->stride
= map
->w
;
3184 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3188 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3189 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3190 * invalidate is set, since we'll be writing the whole rectangle from our
3191 * temporary buffer back out.
3193 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3194 /* ISL uses a stencil pitch value that is expected by hardware whereas
3195 * traditional miptree uses half of that. Below the value gets supplied
3196 * to intel_offset_S8() which expects the legacy interpretation.
3198 const unsigned pitch
= mt
->surf
.size
> 0 ?
3199 mt
->surf
.row_pitch
/ 2 : mt
->pitch
;
3200 uint8_t *untiled_s8_map
= map
->ptr
;
3201 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_READ_BIT
);
3202 unsigned int image_x
, image_y
;
3204 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3206 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3207 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3208 ptrdiff_t offset
= intel_offset_S8(pitch
,
3209 x
+ image_x
+ map
->x
,
3210 y
+ image_y
+ map
->y
,
3211 brw
->has_swizzling
);
3212 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
3216 intel_miptree_unmap_raw(mt
);
3218 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __func__
,
3219 map
->x
, map
->y
, map
->w
, map
->h
,
3220 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
3222 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3223 map
->x
, map
->y
, map
->w
, map
->h
,
3224 mt
, map
->ptr
, map
->stride
);
3229 intel_miptree_unmap_s8(struct brw_context
*brw
,
3230 struct intel_mipmap_tree
*mt
,
3231 struct intel_miptree_map
*map
,
3235 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3236 /* ISL uses a stencil pitch value that is expected by hardware whereas
3237 * traditional miptree uses half of that. Below the value gets supplied
3238 * to intel_offset_S8() which expects the legacy interpretation.
3240 const unsigned pitch
= mt
->surf
.size
> 0 ?
3241 mt
->surf
.row_pitch
/ 2: mt
->pitch
;
3242 unsigned int image_x
, image_y
;
3243 uint8_t *untiled_s8_map
= map
->ptr
;
3244 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
);
3246 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3248 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3249 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3250 ptrdiff_t offset
= intel_offset_S8(pitch
,
3251 image_x
+ x
+ map
->x
,
3252 image_y
+ y
+ map
->y
,
3253 brw
->has_swizzling
);
3254 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
3258 intel_miptree_unmap_raw(mt
);
3265 intel_miptree_map_etc(struct brw_context
*brw
,
3266 struct intel_mipmap_tree
*mt
,
3267 struct intel_miptree_map
*map
,
3271 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
3272 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
3273 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
3276 assert(map
->mode
& GL_MAP_WRITE_BIT
);
3277 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
3279 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
3280 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
3281 map
->w
, map
->h
, 1));
3282 map
->ptr
= map
->buffer
;
3286 intel_miptree_unmap_etc(struct brw_context
*brw
,
3287 struct intel_mipmap_tree
*mt
,
3288 struct intel_miptree_map
*map
,
3294 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
3299 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
, GL_MAP_WRITE_BIT
)
3300 + image_y
* mt
->pitch
3301 + image_x
* mt
->cpp
;
3303 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
3304 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
3305 map
->ptr
, map
->stride
,
3308 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
3309 map
->ptr
, map
->stride
,
3310 map
->w
, map
->h
, mt
->etc_format
);
3312 intel_miptree_unmap_raw(mt
);
3317 * Mapping function for packed depth/stencil miptrees backed by real separate
3318 * miptrees for depth and stencil.
3320 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
3321 * separate from the depth buffer. Yet at the GL API level, we have to expose
3322 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
3323 * be able to map that memory for texture storage and glReadPixels-type
3324 * operations. We give Mesa core that access by mallocing a temporary and
3325 * copying the data between the actual backing store and the temporary.
3328 intel_miptree_map_depthstencil(struct brw_context
*brw
,
3329 struct intel_mipmap_tree
*mt
,
3330 struct intel_miptree_map
*map
,
3331 unsigned int level
, unsigned int slice
)
3333 struct intel_mipmap_tree
*z_mt
= mt
;
3334 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3335 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3336 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
3338 map
->stride
= map
->w
* packed_bpp
;
3339 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
3343 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
3344 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
3345 * invalidate is set, since we'll be writing the whole rectangle from our
3346 * temporary buffer back out.
3348 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
3349 /* ISL uses a stencil pitch value that is expected by hardware whereas
3350 * traditional miptree uses half of that. Below the value gets supplied
3351 * to intel_offset_S8() which expects the legacy interpretation.
3353 const unsigned s_pitch
= s_mt
->surf
.size
> 0 ?
3354 s_mt
->surf
.row_pitch
/ 2 : s_mt
->pitch
;
3355 uint32_t *packed_map
= map
->ptr
;
3356 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_READ_BIT
);
3357 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_READ_BIT
);
3358 unsigned int s_image_x
, s_image_y
;
3359 unsigned int z_image_x
, z_image_y
;
3361 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3362 &s_image_x
, &s_image_y
);
3363 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3364 &z_image_x
, &z_image_y
);
3366 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3367 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3368 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
3369 ptrdiff_t s_offset
= intel_offset_S8(s_pitch
,
3372 brw
->has_swizzling
);
3373 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
3375 (map_x
+ z_image_x
));
3376 uint8_t s
= s_map
[s_offset
];
3377 uint32_t z
= z_map
[z_offset
];
3379 if (map_z32f_x24s8
) {
3380 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
3381 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
3383 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
3388 intel_miptree_unmap_raw(s_mt
);
3389 intel_miptree_unmap_raw(z_mt
);
3391 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
3393 map
->x
, map
->y
, map
->w
, map
->h
,
3394 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3395 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3396 map
->ptr
, map
->stride
);
3398 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __func__
,
3399 map
->x
, map
->y
, map
->w
, map
->h
,
3400 mt
, map
->ptr
, map
->stride
);
3405 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
3406 struct intel_mipmap_tree
*mt
,
3407 struct intel_miptree_map
*map
,
3411 struct intel_mipmap_tree
*z_mt
= mt
;
3412 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
3413 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
3415 if (map
->mode
& GL_MAP_WRITE_BIT
) {
3416 /* ISL uses a stencil pitch value that is expected by hardware whereas
3417 * traditional miptree uses half of that. Below the value gets supplied
3418 * to intel_offset_S8() which expects the legacy interpretation.
3420 const unsigned s_pitch
= s_mt
->surf
.size
> 0 ?
3421 s_mt
->surf
.row_pitch
/ 2 : s_mt
->pitch
;
3422 uint32_t *packed_map
= map
->ptr
;
3423 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
, GL_MAP_WRITE_BIT
);
3424 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
, GL_MAP_WRITE_BIT
);
3425 unsigned int s_image_x
, s_image_y
;
3426 unsigned int z_image_x
, z_image_y
;
3428 intel_miptree_get_image_offset(s_mt
, level
, slice
,
3429 &s_image_x
, &s_image_y
);
3430 intel_miptree_get_image_offset(z_mt
, level
, slice
,
3431 &z_image_x
, &z_image_y
);
3433 for (uint32_t y
= 0; y
< map
->h
; y
++) {
3434 for (uint32_t x
= 0; x
< map
->w
; x
++) {
3435 ptrdiff_t s_offset
= intel_offset_S8(s_pitch
,
3436 x
+ s_image_x
+ map
->x
,
3437 y
+ s_image_y
+ map
->y
,
3438 brw
->has_swizzling
);
3439 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
3441 (x
+ z_image_x
+ map
->x
));
3443 if (map_z32f_x24s8
) {
3444 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
3445 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
3447 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
3448 s_map
[s_offset
] = packed
>> 24;
3449 z_map
[z_offset
] = packed
;
3454 intel_miptree_unmap_raw(s_mt
);
3455 intel_miptree_unmap_raw(z_mt
);
3457 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
3459 map
->x
, map
->y
, map
->w
, map
->h
,
3460 z_mt
, _mesa_get_format_name(z_mt
->format
),
3461 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
3462 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
3463 map
->ptr
, map
->stride
);
3470 * Create and attach a map to the miptree at (level, slice). Return the
3473 static struct intel_miptree_map
*
3474 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
3483 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
3488 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
3489 mt
->level
[level
].slice
[slice
].map
= map
;
3501 * Release the map at (level, slice).
3504 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
3508 struct intel_miptree_map
**map
;
3510 map
= &mt
->level
[level
].slice
[slice
].map
;
3516 can_blit_slice(struct intel_mipmap_tree
*mt
,
3517 unsigned int level
, unsigned int slice
)
3519 /* See intel_miptree_blit() for details on the 32k pitch limit. */
3520 if (mt
->pitch
>= 32768)
3527 use_intel_mipree_map_blit(struct brw_context
*brw
,
3528 struct intel_mipmap_tree
*mt
,
3534 /* It's probably not worth swapping to the blit ring because of
3535 * all the overhead involved.
3537 !(mode
& GL_MAP_WRITE_BIT
) &&
3539 (mt
->tiling
== I915_TILING_X
||
3540 /* Prior to Sandybridge, the blitter can't handle Y tiling */
3541 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
) ||
3542 /* Fast copy blit on skl+ supports all tiling formats. */
3544 can_blit_slice(mt
, level
, slice
))
3547 if (mt
->tiling
!= I915_TILING_NONE
&&
3548 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
3549 assert(can_blit_slice(mt
, level
, slice
));
3557 * Parameter \a out_stride has type ptrdiff_t not because the buffer stride may
3558 * exceed 32 bits but to diminish the likelihood subtle bugs in pointer
3559 * arithmetic overflow.
3561 * If you call this function and use \a out_stride, then you're doing pointer
3562 * arithmetic on \a out_ptr. The type of \a out_stride doesn't prevent all
3563 * bugs. The caller must still take care to avoid 32-bit overflow errors in
3564 * all arithmetic expressions that contain buffer offsets and pixel sizes,
3565 * which usually have type uint32_t or GLuint.
3568 intel_miptree_map(struct brw_context
*brw
,
3569 struct intel_mipmap_tree
*mt
,
3578 ptrdiff_t *out_stride
)
3580 struct intel_miptree_map
*map
;
3582 assert(mt
->num_samples
== 1 || mt
->surf
.samples
== 1);
3584 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
3591 intel_miptree_access_raw(brw
, mt
, level
, slice
,
3592 map
->mode
& GL_MAP_WRITE_BIT
);
3594 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3595 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
3596 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3597 !(mode
& BRW_MAP_DIRECT_BIT
)) {
3598 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
3599 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
3600 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
3601 } else if (use_intel_mipree_map_blit(brw
, mt
, mode
, level
, slice
)) {
3602 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
3603 #if defined(USE_SSE41)
3604 } else if (!(mode
& GL_MAP_WRITE_BIT
) &&
3605 !mt
->compressed
&& cpu_has_sse4_1
&&
3606 (mt
->pitch
% 16 == 0)) {
3607 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
3610 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
3613 *out_ptr
= map
->ptr
;
3614 *out_stride
= map
->stride
;
3616 if (map
->ptr
== NULL
)
3617 intel_miptree_release_map(mt
, level
, slice
);
3621 intel_miptree_unmap(struct brw_context
*brw
,
3622 struct intel_mipmap_tree
*mt
,
3626 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
3628 assert(mt
->num_samples
== 1 || mt
->surf
.samples
== 1);
3633 DBG("%s: mt %p (%s) level %d slice %d\n", __func__
,
3634 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
3636 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3637 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
3638 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
3639 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3640 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
3641 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
3642 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
3643 } else if (map
->linear_mt
) {
3644 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
3645 #if defined(USE_SSE41)
3646 } else if (map
->buffer
&& cpu_has_sse4_1
) {
3647 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
3650 intel_miptree_unmap_gtt(mt
);
3653 intel_miptree_release_map(mt
, level
, slice
);
3657 get_isl_surf_dim(GLenum target
)
3661 case GL_TEXTURE_1D_ARRAY
:
3662 return ISL_SURF_DIM_1D
;
3665 case GL_TEXTURE_2D_ARRAY
:
3666 case GL_TEXTURE_RECTANGLE
:
3667 case GL_TEXTURE_CUBE_MAP
:
3668 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3669 case GL_TEXTURE_2D_MULTISAMPLE
:
3670 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3671 case GL_TEXTURE_EXTERNAL_OES
:
3672 return ISL_SURF_DIM_2D
;
3675 return ISL_SURF_DIM_3D
;
3678 unreachable("Invalid texture target");
3682 get_isl_dim_layout(const struct gen_device_info
*devinfo
, uint32_t tiling
,
3683 GLenum target
, enum miptree_array_layout array_layout
)
3685 if (array_layout
== GEN6_HIZ_STENCIL
)
3686 return ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
;
3690 case GL_TEXTURE_1D_ARRAY
:
3691 return (devinfo
->gen
>= 9 && tiling
== I915_TILING_NONE
?
3692 ISL_DIM_LAYOUT_GEN9_1D
: ISL_DIM_LAYOUT_GEN4_2D
);
3695 case GL_TEXTURE_2D_ARRAY
:
3696 case GL_TEXTURE_RECTANGLE
:
3697 case GL_TEXTURE_2D_MULTISAMPLE
:
3698 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
3699 case GL_TEXTURE_EXTERNAL_OES
:
3700 return ISL_DIM_LAYOUT_GEN4_2D
;
3702 case GL_TEXTURE_CUBE_MAP
:
3703 case GL_TEXTURE_CUBE_MAP_ARRAY
:
3704 return (devinfo
->gen
== 4 ? ISL_DIM_LAYOUT_GEN4_3D
:
3705 ISL_DIM_LAYOUT_GEN4_2D
);
3708 return (devinfo
->gen
>= 9 ?
3709 ISL_DIM_LAYOUT_GEN4_2D
: ISL_DIM_LAYOUT_GEN4_3D
);
3712 unreachable("Invalid texture target");
3716 intel_miptree_get_isl_tiling(const struct intel_mipmap_tree
*mt
)
3718 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3719 return ISL_TILING_W
;
3721 switch (mt
->tiling
) {
3722 case I915_TILING_NONE
:
3723 return ISL_TILING_LINEAR
;
3725 return ISL_TILING_X
;
3727 return ISL_TILING_Y0
;
3729 unreachable("Invalid tiling mode");
3735 intel_miptree_get_isl_surf(struct brw_context
*brw
,
3736 const struct intel_mipmap_tree
*mt
,
3737 struct isl_surf
*surf
)
3739 surf
->dim
= get_isl_surf_dim(mt
->target
);
3740 surf
->dim_layout
= get_isl_dim_layout(&brw
->screen
->devinfo
,
3741 mt
->tiling
, mt
->target
,
3743 surf
->msaa_layout
= mt
->surf
.msaa_layout
;
3744 surf
->tiling
= intel_miptree_get_isl_tiling(mt
);
3746 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
3747 /* The ISL definition of row_pitch matches the surface state pitch field
3748 * a bit better than intel_mipmap_tree. In particular, ISL incorporates
3749 * the factor of 2 for W-tiling in row_pitch.
3751 surf
->row_pitch
= 2 * mt
->pitch
;
3753 surf
->row_pitch
= mt
->pitch
;
3756 surf
->format
= translate_tex_format(brw
, mt
->format
, false);
3758 if (brw
->gen
>= 9) {
3759 if (surf
->dim
== ISL_SURF_DIM_1D
&& surf
->tiling
== ISL_TILING_LINEAR
) {
3760 /* For gen9 1-D surfaces, intel_mipmap_tree has a bogus alignment. */
3761 surf
->image_alignment_el
= isl_extent3d(64, 1, 1);
3763 /* On gen9+, intel_mipmap_tree stores the horizontal and vertical
3764 * alignment in terms of surface elements like we want.
3766 surf
->image_alignment_el
= isl_extent3d(mt
->halign
, mt
->valign
, 1);
3769 /* On earlier gens it's stored in pixels. */
3771 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3772 surf
->image_alignment_el
=
3773 isl_extent3d(mt
->halign
/ bw
, mt
->valign
/ bh
, 1);
3776 surf
->logical_level0_px
.width
= mt
->logical_width0
;
3777 surf
->logical_level0_px
.height
= mt
->logical_height0
;
3778 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3779 surf
->logical_level0_px
.depth
= mt
->logical_depth0
;
3780 surf
->logical_level0_px
.array_len
= 1;
3782 surf
->logical_level0_px
.depth
= 1;
3783 surf
->logical_level0_px
.array_len
= mt
->logical_depth0
;
3786 surf
->phys_level0_sa
.width
= mt
->physical_width0
;
3787 surf
->phys_level0_sa
.height
= mt
->physical_height0
;
3788 if (surf
->dim
== ISL_SURF_DIM_3D
) {
3789 surf
->phys_level0_sa
.depth
= mt
->physical_depth0
;
3790 surf
->phys_level0_sa
.array_len
= 1;
3792 surf
->phys_level0_sa
.depth
= 1;
3793 surf
->phys_level0_sa
.array_len
= mt
->physical_depth0
;
3796 surf
->levels
= mt
->last_level
- mt
->first_level
+ 1;
3797 surf
->samples
= mt
->num_samples
;
3799 surf
->size
= 0; /* TODO */
3800 surf
->alignment
= 0; /* TODO */
3802 switch (surf
->dim_layout
) {
3803 case ISL_DIM_LAYOUT_GEN4_2D
:
3804 case ISL_DIM_LAYOUT_GEN4_3D
:
3805 case ISL_DIM_LAYOUT_GEN6_STENCIL_HIZ
:
3806 if (brw
->gen
>= 9) {
3807 surf
->array_pitch_el_rows
= mt
->qpitch
;
3810 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
3811 assert(mt
->qpitch
% bh
== 0);
3812 surf
->array_pitch_el_rows
= mt
->qpitch
/ bh
;
3815 case ISL_DIM_LAYOUT_GEN9_1D
:
3816 surf
->array_pitch_el_rows
= 1;
3820 switch (mt
->array_layout
) {
3821 case ALL_LOD_IN_EACH_SLICE
:
3822 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_FULL
;
3824 case ALL_SLICES_AT_EACH_LOD
:
3825 case GEN6_HIZ_STENCIL
:
3826 surf
->array_pitch_span
= ISL_ARRAY_PITCH_SPAN_COMPACT
;
3829 unreachable("Invalid array layout");
3832 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
3833 switch (base_format
) {
3834 case GL_DEPTH_COMPONENT
:
3835 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_TEXTURE_BIT
;
3837 case GL_STENCIL_INDEX
:
3838 surf
->usage
= ISL_SURF_USAGE_STENCIL_BIT
;
3840 surf
->usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
3842 case GL_DEPTH_STENCIL
:
3843 /* In this case we only texture from the depth part */
3844 surf
->usage
= ISL_SURF_USAGE_DEPTH_BIT
| ISL_SURF_USAGE_STENCIL_BIT
|
3845 ISL_SURF_USAGE_TEXTURE_BIT
;
3848 surf
->usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
3849 if (brw
->mesa_format_supports_render
[mt
->format
])
3850 surf
->usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
3854 if (_mesa_is_cube_map_texture(mt
->target
))
3855 surf
->usage
|= ISL_SURF_USAGE_CUBE_BIT
;
3859 intel_miptree_get_aux_isl_usage(const struct brw_context
*brw
,
3860 const struct intel_mipmap_tree
*mt
)
3863 return ISL_AUX_USAGE_HIZ
;
3866 return ISL_AUX_USAGE_NONE
;
3868 return mt
->aux_usage
;