1 /**************************************************************************
3 * Copyright 2006 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include <GL/internal/dri_interface.h>
31 #include "intel_batchbuffer.h"
32 #include "intel_chipset.h"
33 #include "intel_mipmap_tree.h"
34 #include "intel_resolve_map.h"
35 #include "intel_tex.h"
36 #include "intel_blit.h"
37 #include "intel_fbo.h"
39 #include "brw_blorp.h"
40 #include "brw_context.h"
42 #include "main/enums.h"
43 #include "main/fbobject.h"
44 #include "main/formats.h"
45 #include "main/glformats.h"
46 #include "main/texcompress_etc.h"
47 #include "main/teximage.h"
48 #include "main/streaming-load-memcpy.h"
49 #include "x86/common_x86_asm.h"
51 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
54 * Determine which MSAA layout should be used by the MSAA surface being
55 * created, based on the chip generation and the surface type.
57 static enum intel_msaa_layout
58 compute_msaa_layout(struct brw_context
*brw
, mesa_format format
, GLenum target
)
60 /* Prior to Gen7, all MSAA surfaces used IMS layout. */
62 return INTEL_MSAA_LAYOUT_IMS
;
64 /* In Gen7, IMS layout is only used for depth and stencil buffers. */
65 switch (_mesa_get_format_base_format(format
)) {
66 case GL_DEPTH_COMPONENT
:
67 case GL_STENCIL_INDEX
:
68 case GL_DEPTH_STENCIL
:
69 return INTEL_MSAA_LAYOUT_IMS
;
71 /* From the Ivy Bridge PRM, Vol4 Part1 p77 ("MCS Enable"):
73 * This field must be set to 0 for all SINT MSRTs when all RT channels
76 * In practice this means that we have to disable MCS for all signed
77 * integer MSAA buffers. The alternative, to disable MCS only when one
78 * of the render target channels is disabled, is impractical because it
79 * would require converting between CMS and UMS MSAA layouts on the fly,
82 if (brw
->gen
== 7 && _mesa_get_format_datatype(format
) == GL_INT
) {
83 return INTEL_MSAA_LAYOUT_UMS
;
85 return INTEL_MSAA_LAYOUT_CMS
;
92 * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
93 * scaled-down bitfield representation of the color buffer which is capable of
94 * recording when blocks of the color buffer are equal to the clear value.
95 * This function returns the block size that will be used by the MCS buffer
96 * corresponding to a certain color miptree.
98 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
99 * beneath the "Fast Color Clear" bullet (p327):
101 * The following table describes the RT alignment
115 * This alignment has the following uses:
117 * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
118 * buffer contains 128 blocks horizontally and 256 blocks vertically.
120 * - For figuring out alignment restrictions for a fast clear operation. Fast
121 * clear operations must always clear aligned multiples of 16 blocks
122 * horizontally and 32 blocks vertically.
124 * - For scaling down the coordinates sent through the render pipeline during
125 * a fast clear. X coordinates must be scaled down by 8 times the block
126 * width, and Y coordinates by 16 times the block height.
128 * - For scaling down the coordinates sent through the render pipeline during
129 * a "Render Target Resolve" operation. X coordinates must be scaled down
130 * by half the block width, and Y coordinates by half the block height.
133 intel_get_non_msrt_mcs_alignment(struct brw_context
*brw
,
134 struct intel_mipmap_tree
*mt
,
135 unsigned *width_px
, unsigned *height
)
137 switch (mt
->tiling
) {
139 unreachable("Non-MSRT MCS requires X or Y tiling");
140 /* In release builds, fall through */
142 *width_px
= 32 / mt
->cpp
;
146 *width_px
= 64 / mt
->cpp
;
153 * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
156 * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
157 * beneath the "Fast Color Clear" bullet (p326):
159 * - Support is limited to tiled render targets.
160 * - Support is for non-mip-mapped and non-array surface types only.
162 * And then later, on p327:
164 * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
168 intel_is_non_msrt_mcs_buffer_supported(struct brw_context
*brw
,
169 struct intel_mipmap_tree
*mt
)
171 /* MCS support does not exist prior to Gen7 */
172 if (brw
->gen
< 7 || brw
->gen
>= 8)
175 /* MCS is only supported for color buffers */
176 switch (_mesa_get_format_base_format(mt
->format
)) {
177 case GL_DEPTH_COMPONENT
:
178 case GL_DEPTH_STENCIL
:
179 case GL_STENCIL_INDEX
:
183 if (mt
->tiling
!= I915_TILING_X
&&
184 mt
->tiling
!= I915_TILING_Y
)
186 if (mt
->cpp
!= 4 && mt
->cpp
!= 8 && mt
->cpp
!= 16)
188 if (mt
->first_level
!= 0 || mt
->last_level
!= 0)
190 if (mt
->physical_depth0
!= 1)
193 /* There's no point in using an MCS buffer if the surface isn't in a
196 if (!brw
->format_supported_as_render_target
[mt
->format
])
204 * Determine depth format corresponding to a depth+stencil format,
205 * for separate stencil.
208 intel_depth_format_for_depthstencil_format(mesa_format format
) {
210 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
211 return MESA_FORMAT_Z24_UNORM_X8_UINT
;
212 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
213 return MESA_FORMAT_Z_FLOAT32
;
221 * @param for_bo Indicates that the caller is
222 * intel_miptree_create_for_bo(). If true, then do not create
225 struct intel_mipmap_tree
*
226 intel_miptree_create_layout(struct brw_context
*brw
,
237 struct intel_mipmap_tree
*mt
= calloc(sizeof(*mt
), 1);
241 DBG("%s target %s format %s level %d..%d slices %d <-- %p\n", __FUNCTION__
,
242 _mesa_lookup_enum_by_nr(target
),
243 _mesa_get_format_name(format
),
244 first_level
, last_level
, depth0
, mt
);
246 if (target
== GL_TEXTURE_1D_ARRAY
) {
247 /* For a 1D Array texture the OpenGL API will treat the height0
248 * parameter as the number of array slices. For Intel hardware, we treat
249 * the 1D array as a 2D Array with a height of 1.
251 * So, when we first come through this path to create a 1D Array
252 * texture, height0 stores the number of slices, and depth0 is 1. In
253 * this case, we want to swap height0 and depth0.
255 * Since some miptrees will be created based on the base miptree, we may
256 * come through this path and see height0 as 1 and depth0 being the
257 * number of slices. In this case we don't need to do the swap.
259 assert(height0
== 1 || depth0
== 1);
268 mt
->first_level
= first_level
;
269 mt
->last_level
= last_level
;
270 mt
->logical_width0
= width0
;
271 mt
->logical_height0
= height0
;
272 mt
->logical_depth0
= depth0
;
273 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
274 exec_list_make_empty(&mt
->hiz_map
);
276 /* The cpp is bytes per (1, blockheight)-sized block for compressed
277 * textures. This is why you'll see divides by blockheight all over
280 _mesa_get_format_block_size(format
, &bw
, &bh
);
281 assert(_mesa_get_format_bytes(mt
->format
) % bw
== 0);
282 mt
->cpp
= _mesa_get_format_bytes(mt
->format
) / bw
;
284 mt
->num_samples
= num_samples
;
285 mt
->compressed
= _mesa_is_format_compressed(format
);
286 mt
->msaa_layout
= INTEL_MSAA_LAYOUT_NONE
;
289 if (num_samples
> 1) {
290 /* Adjust width/height/depth for MSAA */
291 mt
->msaa_layout
= compute_msaa_layout(brw
, format
, mt
->target
);
292 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
293 /* In the Sandy Bridge PRM, volume 4, part 1, page 31, it says:
295 * "Any of the other messages (sample*, LOD, load4) used with a
296 * (4x) multisampled surface will in-effect sample a surface with
297 * double the height and width as that indicated in the surface
298 * state. Each pixel position on the original-sized surface is
299 * replaced with a 2x2 of samples with the following arrangement:
304 * Thus, when sampling from a multisampled texture, it behaves as
305 * though the layout in memory for (x,y,sample) is:
307 * (0,0,0) (0,0,2) (1,0,0) (1,0,2)
308 * (0,0,1) (0,0,3) (1,0,1) (1,0,3)
310 * (0,1,0) (0,1,2) (1,1,0) (1,1,2)
311 * (0,1,1) (0,1,3) (1,1,1) (1,1,3)
313 * However, the actual layout of multisampled data in memory is:
315 * (0,0,0) (1,0,0) (0,0,1) (1,0,1)
316 * (0,1,0) (1,1,0) (0,1,1) (1,1,1)
318 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
319 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
321 * This pattern repeats for each 2x2 pixel block.
323 * As a result, when calculating the size of our 4-sample buffer for
324 * an odd width or height, we have to align before scaling up because
325 * sample 3 is in that bottom right 2x2 block.
327 switch (num_samples
) {
329 assert(brw
->gen
>= 8);
330 width0
= ALIGN(width0
, 2) * 2;
331 height0
= ALIGN(height0
, 2);
334 width0
= ALIGN(width0
, 2) * 2;
335 height0
= ALIGN(height0
, 2) * 2;
338 width0
= ALIGN(width0
, 2) * 4;
339 height0
= ALIGN(height0
, 2) * 2;
342 /* num_samples should already have been quantized to 0, 1, 2, 4, or
345 unreachable("not reached");
348 /* Non-interleaved */
349 depth0
*= num_samples
;
353 /* array_spacing_lod0 is only used for non-IMS MSAA surfaces. TODO: can we
356 switch (mt
->msaa_layout
) {
357 case INTEL_MSAA_LAYOUT_NONE
:
358 case INTEL_MSAA_LAYOUT_IMS
:
359 mt
->array_spacing_lod0
= false;
361 case INTEL_MSAA_LAYOUT_UMS
:
362 case INTEL_MSAA_LAYOUT_CMS
:
363 mt
->array_spacing_lod0
= true;
367 if (target
== GL_TEXTURE_CUBE_MAP
) {
372 mt
->physical_width0
= width0
;
373 mt
->physical_height0
= height0
;
374 mt
->physical_depth0
= depth0
;
377 _mesa_get_format_base_format(format
) == GL_DEPTH_STENCIL
&&
378 (brw
->must_use_separate_stencil
||
379 (brw
->has_separate_stencil
&& brw_is_hiz_depth_format(brw
, format
)))) {
380 mt
->stencil_mt
= intel_miptree_create(brw
,
390 INTEL_MIPTREE_TILING_ANY
);
391 if (!mt
->stencil_mt
) {
392 intel_miptree_release(&mt
);
396 /* Fix up the Z miptree format for how we're splitting out separate
397 * stencil. Gen7 expects there to be no stencil bits in its depth buffer.
399 mt
->format
= intel_depth_format_for_depthstencil_format(mt
->format
);
402 if (format
== mt
->format
) {
403 _mesa_problem(NULL
, "Unknown format %s in separate stencil mt\n",
404 _mesa_get_format_name(mt
->format
));
408 brw_miptree_layout(brw
, mt
);
414 * \brief Helper function for intel_miptree_create().
417 intel_miptree_choose_tiling(struct brw_context
*brw
,
420 uint32_t num_samples
,
421 enum intel_miptree_tiling_mode requested
,
422 struct intel_mipmap_tree
*mt
)
424 if (format
== MESA_FORMAT_S_UINT8
) {
425 /* The stencil buffer is W tiled. However, we request from the kernel a
426 * non-tiled buffer because the GTT is incapable of W fencing.
428 return I915_TILING_NONE
;
431 /* Some usages may want only one type of tiling, like depth miptrees (Y
432 * tiled), or temporary BOs for uploading data once (linear).
435 case INTEL_MIPTREE_TILING_ANY
:
437 case INTEL_MIPTREE_TILING_Y
:
438 return I915_TILING_Y
;
439 case INTEL_MIPTREE_TILING_NONE
:
440 return I915_TILING_NONE
;
443 if (num_samples
> 1) {
444 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
447 * [DevSNB+]: For multi-sample render targets, this field must be
448 * 1. MSRTs can only be tiled.
450 * Our usual reason for preferring X tiling (fast blits using the
451 * blitting engine) doesn't apply to MSAA, since we'll generally be
452 * downsampling or upsampling when blitting between the MSAA buffer
453 * and another buffer, and the blitting engine doesn't support that.
454 * So use Y tiling, since it makes better use of the cache.
456 return I915_TILING_Y
;
459 GLenum base_format
= _mesa_get_format_base_format(format
);
460 if (base_format
== GL_DEPTH_COMPONENT
||
461 base_format
== GL_DEPTH_STENCIL_EXT
)
462 return I915_TILING_Y
;
464 int minimum_pitch
= mt
->total_width
* mt
->cpp
;
466 /* If the width is much smaller than a tile, don't bother tiling. */
467 if (minimum_pitch
< 64)
468 return I915_TILING_NONE
;
470 if (ALIGN(minimum_pitch
, 512) >= 32768 ||
471 mt
->total_width
>= 32768 || mt
->total_height
>= 32768) {
472 perf_debug("%dx%d miptree too large to blit, falling back to untiled",
473 mt
->total_width
, mt
->total_height
);
474 return I915_TILING_NONE
;
477 /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
479 return I915_TILING_X
;
481 /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
482 * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
484 * 128 bits per pixel translates to 16 bytes per pixel. This is necessary
485 * all the way back to 965, but is explicitly permitted on Gen7.
487 if (brw
->gen
!= 7 && mt
->cpp
>= 16)
488 return I915_TILING_X
;
490 /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
491 * messages), on p64, under the heading "Surface Vertical Alignment":
493 * This field must be set to VALIGN_4 for all tiled Y Render Target
496 * So if the surface is renderable and uses a vertical alignment of 2,
497 * force it to be X tiled. This is somewhat conservative (it's possible
498 * that the client won't ever render to this surface), but it's difficult
499 * to know that ahead of time. And besides, since we use a vertical
500 * alignment of 4 as often as we can, this shouldn't happen very often.
502 if (brw
->gen
== 7 && mt
->align_h
== 2 &&
503 brw
->format_supported_as_render_target
[format
]) {
504 return I915_TILING_X
;
507 return I915_TILING_Y
| I915_TILING_X
;
512 * Choose an appropriate uncompressed format for a requested
513 * compressed format, if unsupported.
516 intel_lower_compressed_format(struct brw_context
*brw
, mesa_format format
)
518 /* No need to lower ETC formats on these platforms,
519 * they are supported natively.
521 if (brw
->gen
>= 8 || brw
->is_baytrail
)
525 case MESA_FORMAT_ETC1_RGB8
:
526 return MESA_FORMAT_R8G8B8X8_UNORM
;
527 case MESA_FORMAT_ETC2_RGB8
:
528 return MESA_FORMAT_R8G8B8X8_UNORM
;
529 case MESA_FORMAT_ETC2_SRGB8
:
530 case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC
:
531 case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1
:
532 return MESA_FORMAT_B8G8R8A8_SRGB
;
533 case MESA_FORMAT_ETC2_RGBA8_EAC
:
534 case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1
:
535 return MESA_FORMAT_R8G8B8A8_UNORM
;
536 case MESA_FORMAT_ETC2_R11_EAC
:
537 return MESA_FORMAT_R_UNORM16
;
538 case MESA_FORMAT_ETC2_SIGNED_R11_EAC
:
539 return MESA_FORMAT_R_SNORM16
;
540 case MESA_FORMAT_ETC2_RG11_EAC
:
541 return MESA_FORMAT_R16G16_UNORM
;
542 case MESA_FORMAT_ETC2_SIGNED_RG11_EAC
:
543 return MESA_FORMAT_R16G16_SNORM
;
545 /* Non ETC1 / ETC2 format */
551 struct intel_mipmap_tree
*
552 intel_miptree_create(struct brw_context
*brw
,
560 bool expect_accelerated_upload
,
562 enum intel_miptree_tiling_mode requested_tiling
)
564 struct intel_mipmap_tree
*mt
;
565 mesa_format tex_format
= format
;
566 mesa_format etc_format
= MESA_FORMAT_NONE
;
567 GLuint total_width
, total_height
;
569 format
= intel_lower_compressed_format(brw
, format
);
571 etc_format
= (format
!= tex_format
) ? tex_format
: MESA_FORMAT_NONE
;
573 mt
= intel_miptree_create_layout(brw
, target
, format
,
574 first_level
, last_level
, width0
,
578 * pitch == 0 || height == 0 indicates the null texture
580 if (!mt
|| !mt
->total_width
|| !mt
->total_height
) {
581 intel_miptree_release(&mt
);
585 total_width
= mt
->total_width
;
586 total_height
= mt
->total_height
;
588 if (format
== MESA_FORMAT_S_UINT8
) {
589 /* Align to size of W tile, 64x64. */
590 total_width
= ALIGN(total_width
, 64);
591 total_height
= ALIGN(total_height
, 64);
594 uint32_t tiling
= intel_miptree_choose_tiling(brw
, format
, width0
,
595 num_samples
, requested_tiling
,
599 if (tiling
== (I915_TILING_Y
| I915_TILING_X
)) {
601 mt
->tiling
= I915_TILING_Y
;
607 mt
->etc_format
= etc_format
;
608 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
609 total_width
, total_height
, mt
->cpp
,
611 (expect_accelerated_upload
?
612 BO_ALLOC_FOR_RENDER
: 0));
615 /* If the BO is too large to fit in the aperture, we need to use the
616 * BLT engine to support it. The BLT paths can't currently handle Y-tiling,
617 * so we need to fall back to X.
619 if (y_or_x
&& mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
620 perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
621 mt
->total_width
, mt
->total_height
);
623 mt
->tiling
= I915_TILING_X
;
624 drm_intel_bo_unreference(mt
->bo
);
625 mt
->bo
= drm_intel_bo_alloc_tiled(brw
->bufmgr
, "miptree",
626 total_width
, total_height
, mt
->cpp
,
628 (expect_accelerated_upload
?
629 BO_ALLOC_FOR_RENDER
: 0));
636 intel_miptree_release(&mt
);
641 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) {
642 if (!intel_miptree_alloc_mcs(brw
, mt
, num_samples
)) {
643 intel_miptree_release(&mt
);
648 /* If this miptree is capable of supporting fast color clears, set
649 * fast_clear_state appropriately to ensure that fast clears will occur.
650 * Allocation of the MCS miptree will be deferred until the first fast
651 * clear actually occurs.
653 if (intel_is_non_msrt_mcs_buffer_supported(brw
, mt
))
654 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
659 struct intel_mipmap_tree
*
660 intel_miptree_create_for_bo(struct brw_context
*brw
,
668 struct intel_mipmap_tree
*mt
;
669 uint32_t tiling
, swizzle
;
671 drm_intel_bo_get_tiling(bo
, &tiling
, &swizzle
);
673 /* Nothing will be able to use this miptree with the BO if the offset isn't
676 if (tiling
!= I915_TILING_NONE
)
677 assert(offset
% 4096 == 0);
679 /* miptrees can't handle negative pitch. If you need flipping of images,
680 * that's outside of the scope of the mt.
684 mt
= intel_miptree_create_layout(brw
, GL_TEXTURE_2D
, format
,
687 true, 0 /* num_samples */);
693 drm_intel_bo_reference(bo
);
703 * For a singlesample renderbuffer, this simply wraps the given BO with a
706 * For a multisample renderbuffer, this wraps the window system's
707 * (singlesample) BO with a singlesample miptree attached to the
708 * intel_renderbuffer, then creates a multisample miptree attached to irb->mt
709 * that will contain the actual rendering (which is lazily resolved to
710 * irb->singlesample_mt).
713 intel_update_winsys_renderbuffer_miptree(struct brw_context
*intel
,
714 struct intel_renderbuffer
*irb
,
716 uint32_t width
, uint32_t height
,
719 struct intel_mipmap_tree
*singlesample_mt
= NULL
;
720 struct intel_mipmap_tree
*multisample_mt
= NULL
;
721 struct gl_renderbuffer
*rb
= &irb
->Base
.Base
;
722 mesa_format format
= rb
->Format
;
723 int num_samples
= rb
->NumSamples
;
725 /* Only the front and back buffers, which are color buffers, are allocated
726 * through the image loader.
728 assert(_mesa_get_format_base_format(format
) == GL_RGB
||
729 _mesa_get_format_base_format(format
) == GL_RGBA
);
731 singlesample_mt
= intel_miptree_create_for_bo(intel
,
738 if (!singlesample_mt
)
741 /* If this miptree is capable of supporting fast color clears, set
742 * mcs_state appropriately to ensure that fast clears will occur.
743 * Allocation of the MCS miptree will be deferred until the first fast
744 * clear actually occurs.
746 if (intel_is_non_msrt_mcs_buffer_supported(intel
, singlesample_mt
))
747 singlesample_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_RESOLVED
;
749 if (num_samples
== 0) {
750 intel_miptree_release(&irb
->mt
);
751 irb
->mt
= singlesample_mt
;
753 assert(!irb
->singlesample_mt
);
755 intel_miptree_release(&irb
->singlesample_mt
);
756 irb
->singlesample_mt
= singlesample_mt
;
759 irb
->mt
->logical_width0
!= width
||
760 irb
->mt
->logical_height0
!= height
) {
761 multisample_mt
= intel_miptree_create_for_renderbuffer(intel
,
769 irb
->need_downsample
= false;
770 intel_miptree_release(&irb
->mt
);
771 irb
->mt
= multisample_mt
;
777 intel_miptree_release(&irb
->singlesample_mt
);
778 intel_miptree_release(&irb
->mt
);
782 struct intel_mipmap_tree
*
783 intel_miptree_create_for_renderbuffer(struct brw_context
*brw
,
787 uint32_t num_samples
)
789 struct intel_mipmap_tree
*mt
;
792 GLenum target
= num_samples
> 1 ? GL_TEXTURE_2D_MULTISAMPLE
: GL_TEXTURE_2D
;
794 mt
= intel_miptree_create(brw
, target
, format
, 0, 0,
795 width
, height
, depth
, true, num_samples
,
796 INTEL_MIPTREE_TILING_ANY
);
800 if (brw_is_hiz_depth_format(brw
, format
)) {
801 ok
= intel_miptree_alloc_hiz(brw
, mt
);
809 intel_miptree_release(&mt
);
814 intel_miptree_reference(struct intel_mipmap_tree
**dst
,
815 struct intel_mipmap_tree
*src
)
820 intel_miptree_release(dst
);
824 DBG("%s %p refcount now %d\n", __FUNCTION__
, src
, src
->refcount
);
832 intel_miptree_release(struct intel_mipmap_tree
**mt
)
837 DBG("%s %p refcount will be %d\n", __FUNCTION__
, *mt
, (*mt
)->refcount
- 1);
838 if (--(*mt
)->refcount
<= 0) {
841 DBG("%s deleting %p\n", __FUNCTION__
, *mt
);
843 drm_intel_bo_unreference((*mt
)->bo
);
844 intel_miptree_release(&(*mt
)->stencil_mt
);
845 intel_miptree_release(&(*mt
)->hiz_mt
);
846 intel_miptree_release(&(*mt
)->mcs_mt
);
847 intel_resolve_map_clear(&(*mt
)->hiz_map
);
849 for (i
= 0; i
< MAX_TEXTURE_LEVELS
; i
++) {
850 free((*mt
)->level
[i
].slice
);
859 intel_miptree_get_dimensions_for_image(struct gl_texture_image
*image
,
860 int *width
, int *height
, int *depth
)
862 switch (image
->TexObject
->Target
) {
863 case GL_TEXTURE_1D_ARRAY
:
864 *width
= image
->Width
;
866 *depth
= image
->Height
;
869 *width
= image
->Width
;
870 *height
= image
->Height
;
871 *depth
= image
->Depth
;
877 * Can the image be pulled into a unified mipmap tree? This mirrors
878 * the completeness test in a lot of ways.
880 * Not sure whether I want to pass gl_texture_image here.
883 intel_miptree_match_image(struct intel_mipmap_tree
*mt
,
884 struct gl_texture_image
*image
)
886 struct intel_texture_image
*intelImage
= intel_texture_image(image
);
887 GLuint level
= intelImage
->base
.Base
.Level
;
888 int width
, height
, depth
;
890 /* glTexImage* choose the texture object based on the target passed in, and
891 * objects can't change targets over their lifetimes, so this should be
894 assert(image
->TexObject
->Target
== mt
->target
);
896 mesa_format mt_format
= mt
->format
;
897 if (mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
&& mt
->stencil_mt
)
898 mt_format
= MESA_FORMAT_Z24_UNORM_S8_UINT
;
899 if (mt
->format
== MESA_FORMAT_Z_FLOAT32
&& mt
->stencil_mt
)
900 mt_format
= MESA_FORMAT_Z32_FLOAT_S8X24_UINT
;
901 if (mt
->etc_format
!= MESA_FORMAT_NONE
)
902 mt_format
= mt
->etc_format
;
904 if (image
->TexFormat
!= mt_format
)
907 intel_miptree_get_dimensions_for_image(image
, &width
, &height
, &depth
);
909 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
912 int level_depth
= mt
->level
[level
].depth
;
913 if (mt
->num_samples
> 1) {
914 switch (mt
->msaa_layout
) {
915 case INTEL_MSAA_LAYOUT_NONE
:
916 case INTEL_MSAA_LAYOUT_IMS
:
918 case INTEL_MSAA_LAYOUT_UMS
:
919 case INTEL_MSAA_LAYOUT_CMS
:
920 level_depth
/= mt
->num_samples
;
925 /* Test image dimensions against the base level image adjusted for
926 * minification. This will also catch images not present in the
927 * tree, changed targets, etc.
929 if (width
!= minify(mt
->logical_width0
, level
- mt
->first_level
) ||
930 height
!= minify(mt
->logical_height0
, level
- mt
->first_level
) ||
931 depth
!= level_depth
) {
935 if (image
->NumSamples
!= mt
->num_samples
)
943 intel_miptree_set_level_info(struct intel_mipmap_tree
*mt
,
945 GLuint x
, GLuint y
, GLuint d
)
947 mt
->level
[level
].depth
= d
;
948 mt
->level
[level
].level_x
= x
;
949 mt
->level
[level
].level_y
= y
;
951 DBG("%s level %d, depth %d, offset %d,%d\n", __FUNCTION__
,
954 assert(mt
->level
[level
].slice
== NULL
);
956 mt
->level
[level
].slice
= calloc(d
, sizeof(*mt
->level
[0].slice
));
957 mt
->level
[level
].slice
[0].x_offset
= mt
->level
[level
].level_x
;
958 mt
->level
[level
].slice
[0].y_offset
= mt
->level
[level
].level_y
;
963 intel_miptree_set_image_offset(struct intel_mipmap_tree
*mt
,
964 GLuint level
, GLuint img
,
967 if (img
== 0 && level
== 0)
968 assert(x
== 0 && y
== 0);
970 assert(img
< mt
->level
[level
].depth
);
972 mt
->level
[level
].slice
[img
].x_offset
= mt
->level
[level
].level_x
+ x
;
973 mt
->level
[level
].slice
[img
].y_offset
= mt
->level
[level
].level_y
+ y
;
975 DBG("%s level %d img %d pos %d,%d\n",
976 __FUNCTION__
, level
, img
,
977 mt
->level
[level
].slice
[img
].x_offset
,
978 mt
->level
[level
].slice
[img
].y_offset
);
982 intel_miptree_get_image_offset(const struct intel_mipmap_tree
*mt
,
983 GLuint level
, GLuint slice
,
984 GLuint
*x
, GLuint
*y
)
986 assert(slice
< mt
->level
[level
].depth
);
988 *x
= mt
->level
[level
].slice
[slice
].x_offset
;
989 *y
= mt
->level
[level
].slice
[slice
].y_offset
;
993 * This function computes masks that may be used to select the bits of the X
994 * and Y coordinates that indicate the offset within a tile. If the BO is
995 * untiled, the masks are set to 0.
998 intel_miptree_get_tile_masks(const struct intel_mipmap_tree
*mt
,
999 uint32_t *mask_x
, uint32_t *mask_y
,
1000 bool map_stencil_as_y_tiled
)
1003 uint32_t tiling
= mt
->tiling
;
1005 if (map_stencil_as_y_tiled
)
1006 tiling
= I915_TILING_Y
;
1010 unreachable("not reached");
1011 case I915_TILING_NONE
:
1012 *mask_x
= *mask_y
= 0;
1015 *mask_x
= 512 / cpp
- 1;
1019 *mask_x
= 128 / cpp
- 1;
1026 * Compute the offset (in bytes) from the start of the BO to the given x
1027 * and y coordinate. For tiled BOs, caller must ensure that x and y are
1028 * multiples of the tile size.
1031 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree
*mt
,
1032 uint32_t x
, uint32_t y
,
1033 bool map_stencil_as_y_tiled
)
1036 uint32_t pitch
= mt
->pitch
;
1037 uint32_t tiling
= mt
->tiling
;
1039 if (map_stencil_as_y_tiled
) {
1040 tiling
= I915_TILING_Y
;
1042 /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
1043 * gets transformed into a 32-high Y-tile. Accordingly, the pitch of
1044 * the resulting surface is twice the pitch of the original miptree,
1045 * since each row in the Y-tiled view corresponds to two rows in the
1046 * actual W-tiled surface. So we need to correct the pitch before
1047 * computing the offsets.
1054 unreachable("not reached");
1055 case I915_TILING_NONE
:
1056 return y
* pitch
+ x
* cpp
;
1058 assert((x
% (512 / cpp
)) == 0);
1059 assert((y
% 8) == 0);
1060 return y
* pitch
+ x
/ (512 / cpp
) * 4096;
1062 assert((x
% (128 / cpp
)) == 0);
1063 assert((y
% 32) == 0);
1064 return y
* pitch
+ x
/ (128 / cpp
) * 4096;
1069 * Rendering with tiled buffers requires that the base address of the buffer
1070 * be aligned to a page boundary. For renderbuffers, and sometimes with
1071 * textures, we may want the surface to point at a texture image level that
1072 * isn't at a page boundary.
1074 * This function returns an appropriately-aligned base offset
1075 * according to the tiling restrictions, plus any required x/y offset
1079 intel_miptree_get_tile_offsets(const struct intel_mipmap_tree
*mt
,
1080 GLuint level
, GLuint slice
,
1085 uint32_t mask_x
, mask_y
;
1087 intel_miptree_get_tile_masks(mt
, &mask_x
, &mask_y
, false);
1088 intel_miptree_get_image_offset(mt
, level
, slice
, &x
, &y
);
1090 *tile_x
= x
& mask_x
;
1091 *tile_y
= y
& mask_y
;
1093 return intel_miptree_get_aligned_offset(mt
, x
& ~mask_x
, y
& ~mask_y
, false);
1097 intel_miptree_copy_slice_sw(struct brw_context
*brw
,
1098 struct intel_mipmap_tree
*dst_mt
,
1099 struct intel_mipmap_tree
*src_mt
,
1106 int src_stride
, dst_stride
;
1107 int cpp
= dst_mt
->cpp
;
1109 intel_miptree_map(brw
, src_mt
,
1113 GL_MAP_READ_BIT
| BRW_MAP_DIRECT_BIT
,
1116 intel_miptree_map(brw
, dst_mt
,
1120 GL_MAP_WRITE_BIT
| GL_MAP_INVALIDATE_RANGE_BIT
|
1124 DBG("sw blit %s mt %p %p/%d -> %s mt %p %p/%d (%dx%d)\n",
1125 _mesa_get_format_name(src_mt
->format
),
1126 src_mt
, src
, src_stride
,
1127 _mesa_get_format_name(dst_mt
->format
),
1128 dst_mt
, dst
, dst_stride
,
1131 int row_size
= cpp
* width
;
1132 if (src_stride
== row_size
&&
1133 dst_stride
== row_size
) {
1134 memcpy(dst
, src
, row_size
* height
);
1136 for (int i
= 0; i
< height
; i
++) {
1137 memcpy(dst
, src
, row_size
);
1143 intel_miptree_unmap(brw
, dst_mt
, level
, slice
);
1144 intel_miptree_unmap(brw
, src_mt
, level
, slice
);
1146 /* Don't forget to copy the stencil data over, too. We could have skipped
1147 * passing BRW_MAP_DIRECT_BIT, but that would have meant intel_miptree_map
1148 * shuffling the two data sources in/out of temporary storage instead of
1149 * the direct mapping we get this way.
1151 if (dst_mt
->stencil_mt
) {
1152 assert(src_mt
->stencil_mt
);
1153 intel_miptree_copy_slice_sw(brw
, dst_mt
->stencil_mt
, src_mt
->stencil_mt
,
1154 level
, slice
, width
, height
);
1159 intel_miptree_copy_slice(struct brw_context
*brw
,
1160 struct intel_mipmap_tree
*dst_mt
,
1161 struct intel_mipmap_tree
*src_mt
,
1167 mesa_format format
= src_mt
->format
;
1168 uint32_t width
= minify(src_mt
->physical_width0
, level
- src_mt
->first_level
);
1169 uint32_t height
= minify(src_mt
->physical_height0
, level
- src_mt
->first_level
);
1177 assert(depth
< src_mt
->level
[level
].depth
);
1178 assert(src_mt
->format
== dst_mt
->format
);
1180 if (dst_mt
->compressed
) {
1181 height
= ALIGN(height
, dst_mt
->align_h
) / dst_mt
->align_h
;
1182 width
= ALIGN(width
, dst_mt
->align_w
);
1185 /* If it's a packed depth/stencil buffer with separate stencil, the blit
1186 * below won't apply since we can't do the depth's Y tiling or the
1187 * stencil's W tiling in the blitter.
1189 if (src_mt
->stencil_mt
) {
1190 intel_miptree_copy_slice_sw(brw
,
1197 uint32_t dst_x
, dst_y
, src_x
, src_y
;
1198 intel_miptree_get_image_offset(dst_mt
, level
, slice
, &dst_x
, &dst_y
);
1199 intel_miptree_get_image_offset(src_mt
, level
, slice
, &src_x
, &src_y
);
1201 DBG("validate blit mt %s %p %d,%d/%d -> mt %s %p %d,%d/%d (%dx%d)\n",
1202 _mesa_get_format_name(src_mt
->format
),
1203 src_mt
, src_x
, src_y
, src_mt
->pitch
,
1204 _mesa_get_format_name(dst_mt
->format
),
1205 dst_mt
, dst_x
, dst_y
, dst_mt
->pitch
,
1208 if (!intel_miptree_blit(brw
,
1209 src_mt
, level
, slice
, 0, 0, false,
1210 dst_mt
, level
, slice
, 0, 0, false,
1211 width
, height
, GL_COPY
)) {
1212 perf_debug("miptree validate blit for %s failed\n",
1213 _mesa_get_format_name(format
));
1215 intel_miptree_copy_slice_sw(brw
, dst_mt
, src_mt
, level
, slice
,
1221 * Copies the image's current data to the given miptree, and associates that
1222 * miptree with the image.
1224 * If \c invalidate is true, then the actual image data does not need to be
1225 * copied, but the image still needs to be associated to the new miptree (this
1226 * is set to true if we're about to clear the image).
1229 intel_miptree_copy_teximage(struct brw_context
*brw
,
1230 struct intel_texture_image
*intelImage
,
1231 struct intel_mipmap_tree
*dst_mt
,
1234 struct intel_mipmap_tree
*src_mt
= intelImage
->mt
;
1235 struct intel_texture_object
*intel_obj
=
1236 intel_texture_object(intelImage
->base
.Base
.TexObject
);
1237 int level
= intelImage
->base
.Base
.Level
;
1238 int face
= intelImage
->base
.Base
.Face
;
1239 GLuint depth
= intelImage
->base
.Base
.Depth
;
1242 for (int slice
= 0; slice
< depth
; slice
++) {
1243 intel_miptree_copy_slice(brw
, dst_mt
, src_mt
, level
, face
, slice
);
1247 intel_miptree_reference(&intelImage
->mt
, dst_mt
);
1248 intel_obj
->needs_validate
= true;
1252 intel_miptree_alloc_mcs(struct brw_context
*brw
,
1253 struct intel_mipmap_tree
*mt
,
1256 assert(brw
->gen
>= 7); /* MCS only used on Gen7+ */
1257 assert(mt
->mcs_mt
== NULL
);
1259 /* Choose the correct format for the MCS buffer. All that really matters
1260 * is that we allocate the right buffer size, since we'll always be
1261 * accessing this miptree using MCS-specific hardware mechanisms, which
1262 * infer the correct format based on num_samples.
1265 switch (num_samples
) {
1268 /* 8 bits/pixel are required for MCS data when using 4x MSAA (2 bits for
1271 format
= MESA_FORMAT_R_UNORM8
;
1274 /* 32 bits/pixel are required for MCS data when using 8x MSAA (3 bits
1275 * for each sample, plus 8 padding bits).
1277 format
= MESA_FORMAT_R_UINT32
;
1280 unreachable("Unrecognized sample count in intel_miptree_alloc_mcs");
1283 /* From the Ivy Bridge PRM, Vol4 Part1 p76, "MCS Base Address":
1285 * "The MCS surface must be stored as Tile Y."
1287 mt
->mcs_mt
= intel_miptree_create(brw
,
1293 mt
->logical_height0
,
1296 0 /* num_samples */,
1297 INTEL_MIPTREE_TILING_Y
);
1299 /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
1301 * When MCS buffer is enabled and bound to MSRT, it is required that it
1302 * is cleared prior to any rendering.
1304 * Since we don't use the MCS buffer for any purpose other than rendering,
1305 * it makes sense to just clear it immediately upon allocation.
1307 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
1309 void *data
= intel_miptree_map_raw(brw
, mt
->mcs_mt
);
1310 memset(data
, 0xff, mt
->mcs_mt
->total_height
* mt
->mcs_mt
->pitch
);
1311 intel_miptree_unmap_raw(brw
, mt
->mcs_mt
);
1312 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_CLEAR
;
1319 intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw
,
1320 struct intel_mipmap_tree
*mt
)
1322 assert(mt
->mcs_mt
== NULL
);
1324 /* The format of the MCS buffer is opaque to the driver; all that matters
1325 * is that we get its size and pitch right. We'll pretend that the format
1326 * is R32. Since an MCS tile covers 128 blocks horizontally, and a Y-tiled
1327 * R32 buffer is 32 pixels across, we'll need to scale the width down by
1328 * the block width and then a further factor of 4. Since an MCS tile
1329 * covers 256 blocks vertically, and a Y-tiled R32 buffer is 32 rows high,
1330 * we'll need to scale the height down by the block height and then a
1331 * further factor of 8.
1333 const mesa_format format
= MESA_FORMAT_R_UINT32
;
1334 unsigned block_width_px
;
1335 unsigned block_height
;
1336 intel_get_non_msrt_mcs_alignment(brw
, mt
, &block_width_px
, &block_height
);
1337 unsigned width_divisor
= block_width_px
* 4;
1338 unsigned height_divisor
= block_height
* 8;
1339 unsigned mcs_width
=
1340 ALIGN(mt
->logical_width0
, width_divisor
) / width_divisor
;
1341 unsigned mcs_height
=
1342 ALIGN(mt
->logical_height0
, height_divisor
) / height_divisor
;
1343 assert(mt
->logical_depth0
== 1);
1344 mt
->mcs_mt
= intel_miptree_create(brw
,
1353 0 /* num_samples */,
1354 INTEL_MIPTREE_TILING_Y
);
1361 * Helper for intel_miptree_alloc_hiz() that sets
1362 * \c mt->level[level].has_hiz. Return true if and only if
1363 * \c has_hiz was set.
1366 intel_miptree_level_enable_hiz(struct brw_context
*brw
,
1367 struct intel_mipmap_tree
*mt
,
1372 if (brw
->gen
>= 8 || brw
->is_haswell
) {
1373 uint32_t width
= minify(mt
->physical_width0
, level
);
1374 uint32_t height
= minify(mt
->physical_height0
, level
);
1376 /* Disable HiZ for LOD > 0 unless the width is 8 aligned
1377 * and the height is 4 aligned. This allows our HiZ support
1378 * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
1379 * we can grow the width & height to allow the HiZ op to
1380 * force the proper size alignments.
1382 if (level
> 0 && ((width
& 7) || (height
& 3))) {
1383 DBG("mt %p level %d: HiZ DISABLED\n", mt
, level
);
1388 DBG("mt %p level %d: HiZ enabled\n", mt
, level
);
1389 mt
->level
[level
].has_hiz
= true;
1396 intel_miptree_alloc_hiz(struct brw_context
*brw
,
1397 struct intel_mipmap_tree
*mt
)
1399 assert(mt
->hiz_mt
== NULL
);
1400 mt
->hiz_mt
= intel_miptree_create(brw
,
1406 mt
->logical_height0
,
1410 INTEL_MIPTREE_TILING_ANY
);
1415 /* Mark that all slices need a HiZ resolve. */
1416 for (int level
= mt
->first_level
; level
<= mt
->last_level
; ++level
) {
1417 if (!intel_miptree_level_enable_hiz(brw
, mt
, level
))
1420 for (int layer
= 0; layer
< mt
->level
[level
].depth
; ++layer
) {
1421 struct intel_resolve_map
*m
= malloc(sizeof(struct intel_resolve_map
));
1422 exec_node_init(&m
->link
);
1425 m
->need
= GEN6_HIZ_OP_HIZ_RESOLVE
;
1427 exec_list_push_tail(&mt
->hiz_map
, &m
->link
);
1435 * Does the miptree slice have hiz enabled?
1438 intel_miptree_level_has_hiz(struct intel_mipmap_tree
*mt
, uint32_t level
)
1440 intel_miptree_check_level_layer(mt
, level
, 0);
1441 return mt
->level
[level
].has_hiz
;
1445 intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree
*mt
,
1449 if (!intel_miptree_level_has_hiz(mt
, level
))
1452 intel_resolve_map_set(&mt
->hiz_map
,
1453 level
, layer
, GEN6_HIZ_OP_HIZ_RESOLVE
);
1458 intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree
*mt
,
1462 if (!intel_miptree_level_has_hiz(mt
, level
))
1465 intel_resolve_map_set(&mt
->hiz_map
,
1466 level
, layer
, GEN6_HIZ_OP_DEPTH_RESOLVE
);
1470 intel_miptree_set_all_slices_need_depth_resolve(struct intel_mipmap_tree
*mt
,
1474 uint32_t end_layer
= mt
->level
[level
].depth
;
1476 for (layer
= 0; layer
< end_layer
; layer
++) {
1477 intel_miptree_slice_set_needs_depth_resolve(mt
, level
, layer
);
1482 intel_miptree_slice_resolve(struct brw_context
*brw
,
1483 struct intel_mipmap_tree
*mt
,
1486 enum gen6_hiz_op need
)
1488 intel_miptree_check_level_layer(mt
, level
, layer
);
1490 struct intel_resolve_map
*item
=
1491 intel_resolve_map_get(&mt
->hiz_map
, level
, layer
);
1493 if (!item
|| item
->need
!= need
)
1496 intel_hiz_exec(brw
, mt
, level
, layer
, need
);
1497 intel_resolve_map_remove(item
);
1502 intel_miptree_slice_resolve_hiz(struct brw_context
*brw
,
1503 struct intel_mipmap_tree
*mt
,
1507 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1508 GEN6_HIZ_OP_HIZ_RESOLVE
);
1512 intel_miptree_slice_resolve_depth(struct brw_context
*brw
,
1513 struct intel_mipmap_tree
*mt
,
1517 return intel_miptree_slice_resolve(brw
, mt
, level
, layer
,
1518 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1522 intel_miptree_all_slices_resolve(struct brw_context
*brw
,
1523 struct intel_mipmap_tree
*mt
,
1524 enum gen6_hiz_op need
)
1526 bool did_resolve
= false;
1528 foreach_list_typed_safe(struct intel_resolve_map
, map
, link
, &mt
->hiz_map
) {
1529 if (map
->need
!= need
)
1532 intel_hiz_exec(brw
, mt
, map
->level
, map
->layer
, need
);
1533 intel_resolve_map_remove(map
);
1541 intel_miptree_all_slices_resolve_hiz(struct brw_context
*brw
,
1542 struct intel_mipmap_tree
*mt
)
1544 return intel_miptree_all_slices_resolve(brw
, mt
,
1545 GEN6_HIZ_OP_HIZ_RESOLVE
);
1549 intel_miptree_all_slices_resolve_depth(struct brw_context
*brw
,
1550 struct intel_mipmap_tree
*mt
)
1552 return intel_miptree_all_slices_resolve(brw
, mt
,
1553 GEN6_HIZ_OP_DEPTH_RESOLVE
);
1558 intel_miptree_resolve_color(struct brw_context
*brw
,
1559 struct intel_mipmap_tree
*mt
)
1561 switch (mt
->fast_clear_state
) {
1562 case INTEL_FAST_CLEAR_STATE_NO_MCS
:
1563 case INTEL_FAST_CLEAR_STATE_RESOLVED
:
1564 /* No resolve needed */
1566 case INTEL_FAST_CLEAR_STATE_UNRESOLVED
:
1567 case INTEL_FAST_CLEAR_STATE_CLEAR
:
1568 /* Fast color clear resolves only make sense for non-MSAA buffers. */
1569 if (mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
)
1570 brw_blorp_resolve_color(brw
, mt
);
1577 * Make it possible to share the BO backing the given miptree with another
1578 * process or another miptree.
1580 * Fast color clears are unsafe with shared buffers, so we need to resolve and
1581 * then discard the MCS buffer, if present. We also set the fast_clear_state
1582 * to INTEL_FAST_CLEAR_STATE_NO_MCS to ensure that no MCS buffer gets
1583 * allocated in the future.
1586 intel_miptree_make_shareable(struct brw_context
*brw
,
1587 struct intel_mipmap_tree
*mt
)
1589 /* MCS buffers are also used for multisample buffers, but we can't resolve
1590 * away a multisample MCS buffer because it's an integral part of how the
1591 * pixel data is stored. Fortunately this code path should never be
1592 * reached for multisample buffers.
1594 assert(mt
->msaa_layout
== INTEL_MSAA_LAYOUT_NONE
);
1597 intel_miptree_resolve_color(brw
, mt
);
1598 intel_miptree_release(&mt
->mcs_mt
);
1599 mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_NO_MCS
;
1605 * \brief Get pointer offset into stencil buffer.
1607 * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
1608 * must decode the tile's layout in software.
1611 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
1613 * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
1615 * Even though the returned offset is always positive, the return type is
1617 * commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
1618 * mesa: Fix return type of _mesa_get_format_bytes() (#37351)
1621 intel_offset_S8(uint32_t stride
, uint32_t x
, uint32_t y
, bool swizzled
)
1623 uint32_t tile_size
= 4096;
1624 uint32_t tile_width
= 64;
1625 uint32_t tile_height
= 64;
1626 uint32_t row_size
= 64 * stride
;
1628 uint32_t tile_x
= x
/ tile_width
;
1629 uint32_t tile_y
= y
/ tile_height
;
1631 /* The byte's address relative to the tile's base addres. */
1632 uint32_t byte_x
= x
% tile_width
;
1633 uint32_t byte_y
= y
% tile_height
;
1635 uintptr_t u
= tile_y
* row_size
1636 + tile_x
* tile_size
1637 + 512 * (byte_x
/ 8)
1639 + 32 * ((byte_y
/ 4) % 2)
1640 + 16 * ((byte_x
/ 4) % 2)
1641 + 8 * ((byte_y
/ 2) % 2)
1642 + 4 * ((byte_x
/ 2) % 2)
1647 /* adjust for bit6 swizzling */
1648 if (((byte_x
/ 8) % 2) == 1) {
1649 if (((byte_y
/ 8) % 2) == 0) {
1661 intel_miptree_updownsample(struct brw_context
*brw
,
1662 struct intel_mipmap_tree
*src
,
1663 struct intel_mipmap_tree
*dst
)
1666 brw_blorp_blit_miptrees(brw
,
1667 src
, 0 /* level */, 0 /* layer */,
1668 dst
, 0 /* level */, 0 /* layer */,
1670 src
->logical_width0
, src
->logical_height0
,
1672 dst
->logical_width0
, dst
->logical_height0
,
1673 GL_NEAREST
, false, false /*mirror x, y*/);
1674 } else if (src
->format
== MESA_FORMAT_S_UINT8
) {
1675 brw_meta_stencil_updownsample(brw
, src
, dst
);
1677 brw_meta_updownsample(brw
, src
, dst
);
1680 if (src
->stencil_mt
) {
1681 if (brw
->gen
>= 8) {
1682 brw_meta_stencil_updownsample(brw
, src
->stencil_mt
, dst
);
1686 brw_blorp_blit_miptrees(brw
,
1687 src
->stencil_mt
, 0 /* level */, 0 /* layer */,
1688 dst
->stencil_mt
, 0 /* level */, 0 /* layer */,
1690 src
->logical_width0
, src
->logical_height0
,
1692 dst
->logical_width0
, dst
->logical_height0
,
1693 GL_NEAREST
, false, false /*mirror x, y*/);
1698 intel_miptree_map_raw(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
)
1700 /* CPU accesses to color buffers don't understand fast color clears, so
1701 * resolve any pending fast color clears before we map.
1703 intel_miptree_resolve_color(brw
, mt
);
1705 drm_intel_bo
*bo
= mt
->bo
;
1707 if (drm_intel_bo_references(brw
->batch
.bo
, bo
))
1708 intel_batchbuffer_flush(brw
);
1710 if (mt
->tiling
!= I915_TILING_NONE
)
1711 brw_bo_map_gtt(brw
, bo
, "miptree");
1713 brw_bo_map(brw
, bo
, true, "miptree");
1719 intel_miptree_unmap_raw(struct brw_context
*brw
,
1720 struct intel_mipmap_tree
*mt
)
1722 drm_intel_bo_unmap(mt
->bo
);
1726 intel_miptree_map_gtt(struct brw_context
*brw
,
1727 struct intel_mipmap_tree
*mt
,
1728 struct intel_miptree_map
*map
,
1729 unsigned int level
, unsigned int slice
)
1731 unsigned int bw
, bh
;
1733 unsigned int image_x
, image_y
;
1737 /* For compressed formats, the stride is the number of bytes per
1738 * row of blocks. intel_miptree_get_image_offset() already does
1741 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
1742 assert(y
% bh
== 0);
1745 base
= intel_miptree_map_raw(brw
, mt
) + mt
->offset
;
1750 /* Note that in the case of cube maps, the caller must have passed the
1751 * slice number referencing the face.
1753 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1757 map
->stride
= mt
->pitch
;
1758 map
->ptr
= base
+ y
* map
->stride
+ x
* mt
->cpp
;
1761 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1762 map
->x
, map
->y
, map
->w
, map
->h
,
1763 mt
, _mesa_get_format_name(mt
->format
),
1764 x
, y
, map
->ptr
, map
->stride
);
1768 intel_miptree_unmap_gtt(struct brw_context
*brw
,
1769 struct intel_mipmap_tree
*mt
,
1770 struct intel_miptree_map
*map
,
1774 intel_miptree_unmap_raw(brw
, mt
);
1778 intel_miptree_map_blit(struct brw_context
*brw
,
1779 struct intel_mipmap_tree
*mt
,
1780 struct intel_miptree_map
*map
,
1781 unsigned int level
, unsigned int slice
)
1783 map
->mt
= intel_miptree_create(brw
, GL_TEXTURE_2D
, mt
->format
,
1787 INTEL_MIPTREE_TILING_NONE
);
1789 fprintf(stderr
, "Failed to allocate blit temporary\n");
1792 map
->stride
= map
->mt
->pitch
;
1794 if (!intel_miptree_blit(brw
,
1796 map
->x
, map
->y
, false,
1799 map
->w
, map
->h
, GL_COPY
)) {
1800 fprintf(stderr
, "Failed to blit\n");
1804 map
->ptr
= intel_miptree_map_raw(brw
, map
->mt
);
1806 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1807 map
->x
, map
->y
, map
->w
, map
->h
,
1808 mt
, _mesa_get_format_name(mt
->format
),
1809 level
, slice
, map
->ptr
, map
->stride
);
1814 intel_miptree_release(&map
->mt
);
1820 intel_miptree_unmap_blit(struct brw_context
*brw
,
1821 struct intel_mipmap_tree
*mt
,
1822 struct intel_miptree_map
*map
,
1826 struct gl_context
*ctx
= &brw
->ctx
;
1828 intel_miptree_unmap_raw(brw
, map
->mt
);
1830 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1831 bool ok
= intel_miptree_blit(brw
,
1835 map
->x
, map
->y
, false,
1836 map
->w
, map
->h
, GL_COPY
);
1837 WARN_ONCE(!ok
, "Failed to blit from linear temporary mapping");
1840 intel_miptree_release(&map
->mt
);
1844 * "Map" a buffer by copying it to an untiled temporary using MOVNTDQA.
1847 intel_miptree_map_movntdqa(struct brw_context
*brw
,
1848 struct intel_mipmap_tree
*mt
,
1849 struct intel_miptree_map
*map
,
1850 unsigned int level
, unsigned int slice
)
1852 assert(map
->mode
& GL_MAP_READ_BIT
);
1853 assert(!(map
->mode
& GL_MAP_WRITE_BIT
));
1855 DBG("%s: %d,%d %dx%d from mt %p (%s) %d,%d = %p/%d\n", __FUNCTION__
,
1856 map
->x
, map
->y
, map
->w
, map
->h
,
1857 mt
, _mesa_get_format_name(mt
->format
),
1858 level
, slice
, map
->ptr
, map
->stride
);
1860 /* Map the original image */
1863 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1867 void *src
= intel_miptree_map_raw(brw
, mt
);
1870 src
+= image_y
* mt
->pitch
;
1871 src
+= image_x
* mt
->cpp
;
1873 /* Due to the pixel offsets for the particular image being mapped, our
1874 * src pointer may not be 16-byte aligned. However, if the pitch is
1875 * divisible by 16, then the amount by which it's misaligned will remain
1876 * consistent from row to row.
1878 assert((mt
->pitch
% 16) == 0);
1879 const int misalignment
= ((uintptr_t) src
) & 15;
1881 /* Create an untiled temporary buffer for the mapping. */
1882 const unsigned width_bytes
= _mesa_format_row_stride(mt
->format
, map
->w
);
1884 map
->stride
= ALIGN(misalignment
+ width_bytes
, 16);
1886 map
->buffer
= _mesa_align_malloc(map
->stride
* map
->h
, 16);
1887 /* Offset the destination so it has the same misalignment as src. */
1888 map
->ptr
= map
->buffer
+ misalignment
;
1890 assert((((uintptr_t) map
->ptr
) & 15) == misalignment
);
1892 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1893 void *dst_ptr
= map
->ptr
+ y
* map
->stride
;
1894 void *src_ptr
= src
+ y
* mt
->pitch
;
1896 _mesa_streaming_load_memcpy(dst_ptr
, src_ptr
, width_bytes
);
1899 intel_miptree_unmap_raw(brw
, mt
);
1903 intel_miptree_unmap_movntdqa(struct brw_context
*brw
,
1904 struct intel_mipmap_tree
*mt
,
1905 struct intel_miptree_map
*map
,
1909 _mesa_align_free(map
->buffer
);
1915 intel_miptree_map_s8(struct brw_context
*brw
,
1916 struct intel_mipmap_tree
*mt
,
1917 struct intel_miptree_map
*map
,
1918 unsigned int level
, unsigned int slice
)
1920 map
->stride
= map
->w
;
1921 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
1925 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
1926 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
1927 * invalidate is set, since we'll be writing the whole rectangle from our
1928 * temporary buffer back out.
1930 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
1931 uint8_t *untiled_s8_map
= map
->ptr
;
1932 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
1933 unsigned int image_x
, image_y
;
1935 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1937 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1938 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1939 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
1940 x
+ image_x
+ map
->x
,
1941 y
+ image_y
+ map
->y
,
1942 brw
->has_swizzling
);
1943 untiled_s8_map
[y
* map
->w
+ x
] = tiled_s8_map
[offset
];
1947 intel_miptree_unmap_raw(brw
, mt
);
1949 DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __FUNCTION__
,
1950 map
->x
, map
->y
, map
->w
, map
->h
,
1951 mt
, map
->x
+ image_x
, map
->y
+ image_y
, map
->ptr
, map
->stride
);
1953 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
1954 map
->x
, map
->y
, map
->w
, map
->h
,
1955 mt
, map
->ptr
, map
->stride
);
1960 intel_miptree_unmap_s8(struct brw_context
*brw
,
1961 struct intel_mipmap_tree
*mt
,
1962 struct intel_miptree_map
*map
,
1966 if (map
->mode
& GL_MAP_WRITE_BIT
) {
1967 unsigned int image_x
, image_y
;
1968 uint8_t *untiled_s8_map
= map
->ptr
;
1969 uint8_t *tiled_s8_map
= intel_miptree_map_raw(brw
, mt
);
1971 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
1973 for (uint32_t y
= 0; y
< map
->h
; y
++) {
1974 for (uint32_t x
= 0; x
< map
->w
; x
++) {
1975 ptrdiff_t offset
= intel_offset_S8(mt
->pitch
,
1978 brw
->has_swizzling
);
1979 tiled_s8_map
[offset
] = untiled_s8_map
[y
* map
->w
+ x
];
1983 intel_miptree_unmap_raw(brw
, mt
);
1990 intel_miptree_map_etc(struct brw_context
*brw
,
1991 struct intel_mipmap_tree
*mt
,
1992 struct intel_miptree_map
*map
,
1996 assert(mt
->etc_format
!= MESA_FORMAT_NONE
);
1997 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
) {
1998 assert(mt
->format
== MESA_FORMAT_R8G8B8X8_UNORM
);
2001 assert(map
->mode
& GL_MAP_WRITE_BIT
);
2002 assert(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
);
2004 map
->stride
= _mesa_format_row_stride(mt
->etc_format
, map
->w
);
2005 map
->buffer
= malloc(_mesa_format_image_size(mt
->etc_format
,
2006 map
->w
, map
->h
, 1));
2007 map
->ptr
= map
->buffer
;
2011 intel_miptree_unmap_etc(struct brw_context
*brw
,
2012 struct intel_mipmap_tree
*mt
,
2013 struct intel_miptree_map
*map
,
2019 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2024 uint8_t *dst
= intel_miptree_map_raw(brw
, mt
)
2025 + image_y
* mt
->pitch
2026 + image_x
* mt
->cpp
;
2028 if (mt
->etc_format
== MESA_FORMAT_ETC1_RGB8
)
2029 _mesa_etc1_unpack_rgba8888(dst
, mt
->pitch
,
2030 map
->ptr
, map
->stride
,
2033 _mesa_unpack_etc2_format(dst
, mt
->pitch
,
2034 map
->ptr
, map
->stride
,
2035 map
->w
, map
->h
, mt
->etc_format
);
2037 intel_miptree_unmap_raw(brw
, mt
);
2042 * Mapping function for packed depth/stencil miptrees backed by real separate
2043 * miptrees for depth and stencil.
2045 * On gen7, and to support HiZ pre-gen7, we have to have the stencil buffer
2046 * separate from the depth buffer. Yet at the GL API level, we have to expose
2047 * packed depth/stencil textures and FBO attachments, and Mesa core expects to
2048 * be able to map that memory for texture storage and glReadPixels-type
2049 * operations. We give Mesa core that access by mallocing a temporary and
2050 * copying the data between the actual backing store and the temporary.
2053 intel_miptree_map_depthstencil(struct brw_context
*brw
,
2054 struct intel_mipmap_tree
*mt
,
2055 struct intel_miptree_map
*map
,
2056 unsigned int level
, unsigned int slice
)
2058 struct intel_mipmap_tree
*z_mt
= mt
;
2059 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2060 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2061 int packed_bpp
= map_z32f_x24s8
? 8 : 4;
2063 map
->stride
= map
->w
* packed_bpp
;
2064 map
->buffer
= map
->ptr
= malloc(map
->stride
* map
->h
);
2068 /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no
2069 * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless
2070 * invalidate is set, since we'll be writing the whole rectangle from our
2071 * temporary buffer back out.
2073 if (!(map
->mode
& GL_MAP_INVALIDATE_RANGE_BIT
)) {
2074 uint32_t *packed_map
= map
->ptr
;
2075 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2076 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2077 unsigned int s_image_x
, s_image_y
;
2078 unsigned int z_image_x
, z_image_y
;
2080 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2081 &s_image_x
, &s_image_y
);
2082 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2083 &z_image_x
, &z_image_y
);
2085 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2086 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2087 int map_x
= map
->x
+ x
, map_y
= map
->y
+ y
;
2088 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2091 brw
->has_swizzling
);
2092 ptrdiff_t z_offset
= ((map_y
+ z_image_y
) *
2094 (map_x
+ z_image_x
));
2095 uint8_t s
= s_map
[s_offset
];
2096 uint32_t z
= z_map
[z_offset
];
2098 if (map_z32f_x24s8
) {
2099 packed_map
[(y
* map
->w
+ x
) * 2 + 0] = z
;
2100 packed_map
[(y
* map
->w
+ x
) * 2 + 1] = s
;
2102 packed_map
[y
* map
->w
+ x
] = (s
<< 24) | (z
& 0x00ffffff);
2107 intel_miptree_unmap_raw(brw
, s_mt
);
2108 intel_miptree_unmap_raw(brw
, z_mt
);
2110 DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
2112 map
->x
, map
->y
, map
->w
, map
->h
,
2113 z_mt
, map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2114 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2115 map
->ptr
, map
->stride
);
2117 DBG("%s: %d,%d %dx%d from mt %p = %p/%d\n", __FUNCTION__
,
2118 map
->x
, map
->y
, map
->w
, map
->h
,
2119 mt
, map
->ptr
, map
->stride
);
2124 intel_miptree_unmap_depthstencil(struct brw_context
*brw
,
2125 struct intel_mipmap_tree
*mt
,
2126 struct intel_miptree_map
*map
,
2130 struct intel_mipmap_tree
*z_mt
= mt
;
2131 struct intel_mipmap_tree
*s_mt
= mt
->stencil_mt
;
2132 bool map_z32f_x24s8
= mt
->format
== MESA_FORMAT_Z_FLOAT32
;
2134 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2135 uint32_t *packed_map
= map
->ptr
;
2136 uint8_t *s_map
= intel_miptree_map_raw(brw
, s_mt
);
2137 uint32_t *z_map
= intel_miptree_map_raw(brw
, z_mt
);
2138 unsigned int s_image_x
, s_image_y
;
2139 unsigned int z_image_x
, z_image_y
;
2141 intel_miptree_get_image_offset(s_mt
, level
, slice
,
2142 &s_image_x
, &s_image_y
);
2143 intel_miptree_get_image_offset(z_mt
, level
, slice
,
2144 &z_image_x
, &z_image_y
);
2146 for (uint32_t y
= 0; y
< map
->h
; y
++) {
2147 for (uint32_t x
= 0; x
< map
->w
; x
++) {
2148 ptrdiff_t s_offset
= intel_offset_S8(s_mt
->pitch
,
2149 x
+ s_image_x
+ map
->x
,
2150 y
+ s_image_y
+ map
->y
,
2151 brw
->has_swizzling
);
2152 ptrdiff_t z_offset
= ((y
+ z_image_y
+ map
->y
) *
2154 (x
+ z_image_x
+ map
->x
));
2156 if (map_z32f_x24s8
) {
2157 z_map
[z_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 0];
2158 s_map
[s_offset
] = packed_map
[(y
* map
->w
+ x
) * 2 + 1];
2160 uint32_t packed
= packed_map
[y
* map
->w
+ x
];
2161 s_map
[s_offset
] = packed
>> 24;
2162 z_map
[z_offset
] = packed
;
2167 intel_miptree_unmap_raw(brw
, s_mt
);
2168 intel_miptree_unmap_raw(brw
, z_mt
);
2170 DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
2172 map
->x
, map
->y
, map
->w
, map
->h
,
2173 z_mt
, _mesa_get_format_name(z_mt
->format
),
2174 map
->x
+ z_image_x
, map
->y
+ z_image_y
,
2175 s_mt
, map
->x
+ s_image_x
, map
->y
+ s_image_y
,
2176 map
->ptr
, map
->stride
);
2183 * Create and attach a map to the miptree at (level, slice). Return the
2186 static struct intel_miptree_map
*
2187 intel_miptree_attach_map(struct intel_mipmap_tree
*mt
,
2196 struct intel_miptree_map
*map
= calloc(1, sizeof(*map
));
2201 assert(mt
->level
[level
].slice
[slice
].map
== NULL
);
2202 mt
->level
[level
].slice
[slice
].map
= map
;
2214 * Release the map at (level, slice).
2217 intel_miptree_release_map(struct intel_mipmap_tree
*mt
,
2221 struct intel_miptree_map
**map
;
2223 map
= &mt
->level
[level
].slice
[slice
].map
;
2229 can_blit_slice(struct intel_mipmap_tree
*mt
,
2230 unsigned int level
, unsigned int slice
)
2234 intel_miptree_get_image_offset(mt
, level
, slice
, &image_x
, &image_y
);
2235 if (image_x
>= 32768 || image_y
>= 32768)
2238 if (mt
->pitch
>= 32768)
2245 intel_miptree_map(struct brw_context
*brw
,
2246 struct intel_mipmap_tree
*mt
,
2257 struct intel_miptree_map
*map
;
2259 assert(mt
->num_samples
<= 1);
2261 map
= intel_miptree_attach_map(mt
, level
, slice
, x
, y
, w
, h
, mode
);
2268 intel_miptree_slice_resolve_depth(brw
, mt
, level
, slice
);
2269 if (map
->mode
& GL_MAP_WRITE_BIT
) {
2270 intel_miptree_slice_set_needs_hiz_resolve(mt
, level
, slice
);
2273 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2274 intel_miptree_map_s8(brw
, mt
, map
, level
, slice
);
2275 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2276 !(mode
& BRW_MAP_DIRECT_BIT
)) {
2277 intel_miptree_map_etc(brw
, mt
, map
, level
, slice
);
2278 } else if (mt
->stencil_mt
&& !(mode
& BRW_MAP_DIRECT_BIT
)) {
2279 intel_miptree_map_depthstencil(brw
, mt
, map
, level
, slice
);
2281 /* See intel_miptree_blit() for details on the 32k pitch limit. */
2282 else if (brw
->has_llc
&&
2283 !(mode
& GL_MAP_WRITE_BIT
) &&
2285 (mt
->tiling
== I915_TILING_X
||
2286 (brw
->gen
>= 6 && mt
->tiling
== I915_TILING_Y
)) &&
2287 can_blit_slice(mt
, level
, slice
)) {
2288 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2289 } else if (mt
->tiling
!= I915_TILING_NONE
&&
2290 mt
->bo
->size
>= brw
->max_gtt_map_object_size
) {
2291 assert(can_blit_slice(mt
, level
, slice
));
2292 intel_miptree_map_blit(brw
, mt
, map
, level
, slice
);
2293 } else if (!(mode
& GL_MAP_WRITE_BIT
) && !mt
->compressed
&& cpu_has_sse4_1
) {
2294 intel_miptree_map_movntdqa(brw
, mt
, map
, level
, slice
);
2296 intel_miptree_map_gtt(brw
, mt
, map
, level
, slice
);
2299 *out_ptr
= map
->ptr
;
2300 *out_stride
= map
->stride
;
2302 if (map
->ptr
== NULL
)
2303 intel_miptree_release_map(mt
, level
, slice
);
2307 intel_miptree_unmap(struct brw_context
*brw
,
2308 struct intel_mipmap_tree
*mt
,
2312 struct intel_miptree_map
*map
= mt
->level
[level
].slice
[slice
].map
;
2314 assert(mt
->num_samples
<= 1);
2319 DBG("%s: mt %p (%s) level %d slice %d\n", __FUNCTION__
,
2320 mt
, _mesa_get_format_name(mt
->format
), level
, slice
);
2322 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
2323 intel_miptree_unmap_s8(brw
, mt
, map
, level
, slice
);
2324 } else if (mt
->etc_format
!= MESA_FORMAT_NONE
&&
2325 !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2326 intel_miptree_unmap_etc(brw
, mt
, map
, level
, slice
);
2327 } else if (mt
->stencil_mt
&& !(map
->mode
& BRW_MAP_DIRECT_BIT
)) {
2328 intel_miptree_unmap_depthstencil(brw
, mt
, map
, level
, slice
);
2329 } else if (map
->mt
) {
2330 intel_miptree_unmap_blit(brw
, mt
, map
, level
, slice
);
2331 } else if (map
->buffer
&& cpu_has_sse4_1
) {
2332 intel_miptree_unmap_movntdqa(brw
, mt
, map
, level
, slice
);
2334 intel_miptree_unmap_gtt(brw
, mt
, map
, level
, slice
);
2337 intel_miptree_release_map(mt
, level
, slice
);